A Family of Bidirectional DC–DC Converters for Battery Storage System with High Voltage Gain

Abstract

In low power energy storage systems, to match the voltage levels of the low-voltage battery side and high-voltage direct current (DC) bus, a high voltage gain converter with bidirectional operation is required. In this system, the cost effectiveness of the design is a critical factor; therefore, the system should be designed using a small number of components. This paper proposes a set of bidirectional converters with high voltage gain range based on the integration of the boost converter with a Ćuk converter, single ended primary inductor converter (Sepic), and buck-boost converter. The proposed converters consist of a small number of components with a high voltage gain ratio. Detailed comparisons are made with respect to the operating mode, number of components, voltage, and current ripple and efficiency. The efficiency of proposed converters are higher than the conventional converters in entire power range, and 6% higher efficiency can be achieved in large duty cycle by calculating loss analysis. To verify performances of the proposed converters, three 200-W prototypes of the converters are developed under the same experimental conditions. The results revealed that converter I exhibits the highest efficiency in the boost mode (92%) and buck mode (92.2%). The experimental results are shown to verify the feasibility and performances of the set of converters.

1. Introduction

Energy storage systems (ESS) with DC–DC converters operating in bidirectional is indispensable in microgrids, electric vehicles (EVs), and transportation systems based on the renewable energy [1,2]. Bidirectional DC–DC converters are essential for the transfer and conversion of the electrical energy of the storage units, which operate the charge and discharge processes. Hence, bidirectional converters are the vital elements for the realization of efficient energy management. In general, the voltage of the storage units is relatively low due to safety problems. Therefore, a converter operating in bidirectional is available to connect the storage elements to the dc bus [3,4]. The realization of highly efficient converters with large conversion ratios and high power densities is a significant challenge in the power electronics field.

With respect to the high voltage conversion ratio bi-direction DC–DC converters, they can be divided into isolated converters and non-isolated converters. According to the conventional bidirectional converters with transformer [5,6,7], this type of converter benefits from a simple structure and easy to operate. However, the leakage inductor loss due to the high-frequency transformer results in a low converter efficiency. For most transformerless bidirectional converters [8,9,10,11,12,13], although the high frequency loss is lower, the voltage gain ratio is relatively low. In addition, there are more active components in several non-isolated converters. For example, the Ćuk converter, SEPIC converter, and Zeta converter can also be changed into double direction form; however, the inherent structure of these converters determined to be inefficient at high duty cycles [14,15,16]. In references [17] and [18,19,20], DC–DC converters operating in bidirectional with high conversion ratio are proposed. Practically, there have more power switches in these converters which led to increasing the conduction losses and the cost efficiency, lead to decrease the efficiency. In reference [21], a novel buck-boost converter without transformer is proposed. The converter has only one power switch is utilized. However, for this converter, three inductors are applied to the topology, which may result in a low power density. In reference [22], a novel quasi-Z-source DC–DC converter is presented for EVs, which attained a high voltage conversion ratio and low voltage stress across the power switches. However, the ripple rate on the inductance is relatively high.

To overcome these problems, converters based on the integration of the boost converter with the Ćuk, Sepic, and buck-boost converters are presented in [23,24,25]. This attained a high voltage gain ratio and low voltage stress across the power switches. However, the converters operate only in unidirectional mode, and furthermore, the voltage and current stresses on the switches are not analyzed in detail. Therefore, a set of DC–DC converters operating in bi-direction with high voltage conversion ratio based on [23,24,25] are proposed in this paper.

In order to analyze the proposed converters, detailed comparisons are made with respect to the operating mode, number of components, voltage and current ripple and efficiency. The voltage ripple of the proposed converters is relatively low, which increases design flexibility for the passive component. In addition, the loss and efficiency of the proposed converters and the conventional converters are compared by calculation under the same conditions. The calculation results shown that the efficiency of proposed converters is higher than the conventional converters in the entire power range, especially in large duty cycle, because the proposed converter is less affected by parasitic elements. For experimental validation, three 200-W prototypes are built under the same experimental conditions. The experimental results demonstrate a 92.2% peak efficiency for the buck mode and 92% peak efficiency for the boost mode.

2. Bidirectional DC–DC Converters with Wide Voltage Conversion Ratio

The structure of the proposed converters are presented from Figure 1, Figure 2 and Figure 3. The proposed converters consist of three power switches Q₁, Q₂, and Q₃; capacitors C₁, C₂, and C₃ (I and II), in addition, there are two inductors L₁ and L₂ in these converters. The proposed converters are analyzed based on the assumption that the converters operate in continuous conduction mode (CCM), and that all the components are analyzed in the ideal condition.

2.1. Construction of the Converter I

The main theoretical waveforms of the proposed converter I in CCM are presented in Figure 4a,b, and the steady-state analyses with respect to the switching states of the converter I are shown as follows.

(1) Boost mode of the converter I:

When the converter I operates in the boost mode, the power flows from the battery side to the dc bus side. In this mode, the switch Q₁ is shown as the main power switch, and Q₂ and Q₃ are shown as the synchronous rectifiers. The gate signal of Q₁ is complementary to Q₂ and Q₃; thus, d₁ = 1 − d₂ = 1 − d₃ = d_Boost. The topological states are described in Figure 5a,b.

[t₀–t₁]: When the circuit operates in this case. Switch Q₁ is turned ON, and switches Q₂ and Q₃ are turned OFF, as described in Figure 5a, the battery voltage flows through inductor L₁, while inductor L₂ and C₃ are charging through C₂. With reference to Figure 5a, in addition, by applying the Kirchhoff voltage law (KVL) and Kirchhoff current law (KCL) to the circuit, the formulas below are obtained for this state.

$$\{\begin{array}{l}{U}_{L1}=U_{low}\\ U_{L2}=U_{C2}-U_{C3}\\ U_{C1}+U_{C2}=U_{high}\end{array}$$

(1)

$$\{\begin{array}{l}{i}_{L2}=-i_{C2}\\ i_{C3}=i_{L2}\\ i_{C1}=-i_{high}\end{array}$$

(2)

where U_L1, U_L2 represent the voltage on the inductors. U_C1, U_C2 and U_C3 are the voltage on the capacitors. U_high and U_low are shown as the voltage on the DC bus side and battery side. I_high and I_low are shown as the current on the DC bus side and battery side. These symbols are applicable to all of the converters in this paper.

[t₁–t₂]: By contrast, the second topological state is depicted in Figure 5b. In this case, the input voltage and the indictor L₁ are discharged to capacitor C₂ in series. Moreover, inductor L₂ is also discharged to C₁ through Q₃, and C₂ is charged through Q₂. The output voltage is boosting by connecting the capacitors C₁ and C₂ in stack. With reference to Figure 5b, by applying the same principle, the formulas below are derived for this state.

$$\{\begin{array}{l}{U}_{L1}=U_{low}-U_{C2}\\ U_{L2}=-U_{C3}=-U_{C1}\\ U_{C1}+U_{C2}=U_{high}\end{array}$$

(3)

$$\{\begin{array}{l}{i}_{L1}+i_{C3}-i_{L2}=i_{C2}\\ -i_{C3}+i_{L2}-i_{C1}=i_{high}\end{array}$$

(4)

By employing the volt-second balance theory of inductors L₁ and L₂ on the basis of (1) and (3), the voltage gain rate M_Boost of suggested converter I in CCM can be expressed as

$$M_{Boost}=\frac{1+d_{Boost}}{1-d_{Boost}}$$

(5)

Moreover, the voltage stresses across capacitors C₁ and C₂ can be written as

$$\{\begin{array}{l}{U}_{C1}=\frac{d_{Boost}{U}_{low}}{1-d_{Boost}}=\frac{d_{Boost}{U}_{high}}{1+d_{Boost}}\\ U_{C2}=\frac{U_{low}}{1-d_{Boost}}=\frac{U_{high}}{1+d_{Boost}}\end{array}$$

(6)

By employing the ampere-second balance law to the capacitors on the basis of Equation (2) and Equation (4), the average value of the inductor currents I_L1 and I_L2 can be achieved as

$$\{\begin{array}{l}{I}_{L1}=\frac{1+d_{Boost}}{1-d_{Boost}}{I}_{high}\\ I_{L2}=I_{high}\end{array}$$

(7)

(2) Buck mode of the converter I:

When the proposed converter I is applied to the buck mode, this is reverse to the boost mode, in which the gate signal of Q₁ is complementary to Q₂ and Q₃; thus, d₁ = 1 − d₂ = 1 − d₃ = d_Buck. The topological stages are depicted in Figure 6a,b.

[t₀–t₁]: When Q₁ is turned OFF, and Q₂ and Q₃ are turned ON. The switching state is presented in Figure 6a. As for this state, L₁, L₂, and C₃ are charged by C₁ and C₂, respectively, through Q₂ and Q₃. The following formulas are derived for this state.

$$\{\begin{array}{l}{U}_{L1}=U_{C2}-U_{low}\\ U_{L2}=U_{C3}=U_{C1}\\ U_{C1}+U_{C2}=U_{high}\end{array}$$

(8)

$$\{\begin{array}{l}{i}_{C3}=i_{L2}\\ i_{L2}=i_{C2}\\ i_{high}=i_{C1}\end{array}$$

(9)

[t₁–t₂]: In this state, switching state is opposed to previous operation. The switching state is presented in Figure 6b. In this case, C₃ and L₂ are in series connection to charge C₂ by Q₁. Moreover, L₁ also discharges to C₀ through Q₁, on the basis of Figure 6b. The formulas below are then calculated for this case.

$$\{\begin{array}{l}{U}_{L1}=-U_{low}\\ U_{L2}=U_{C3}-U_{C2}\\ U_{C1}+U_{C2}=U_{high}\end{array}$$

(10)

$$\{\begin{array}{l}{i}_{C1}=i_{L1}+i_{C3}-i_{L2}\\ i_{high}=i_{L2}-i_{C2}\end{array}$$

(11)

Taking into account the volt-second balance law on L₁ and L₂ according to Equation (8) and Equation (10), the boost conversion M_Boost of the proposed converter I in CCM can be obtained as

$$M_{Buck}=\frac{d_{Buck}}{2-d_{Buck}}$$

(12)

Moreover, it is concluded that the capacitor voltage can be deduced as

$$\{\begin{array}{l}{U}_{C1}=\frac{U_{low}}{d_{Buck}}=\frac{U_{high}}{2-d_{Buck}}\\ U_{C2}=\frac{(1-d_{Buck})U_{low}}{d_{Buck}}=\frac{(1-d_{Buck})U_{high}}{2-d_{Boost}}\end{array}$$

(13)

Using the ampere-second balance law of capacitors with Equation (9) and Equation (11), the average inductor currents I_L1 and I_L2 of inductors L₁ and L₂ can be obtained as

$$\{\begin{array}{l}{I}_{L1}=I_{low}\\ I_{L2}=\frac{d_{Buck}}{2-d_{Buck}}{I}_{low}\end{array}$$

(14)

(3) Voltage and current stresses of the power switches (converter I):

Voltage stress across the power switches: In accordance with the above analysis, as shown in Figure 5 and Figure 6. In addition, by employing the Kirchhoff voltage law (KVL) to the switches, it can be derived that.

$$\begin{array}{l}{U}_{Q1\_Boost}=U_{Q2\_Boost}=U_{Q3\_Boost}=\frac{U_{low}}{1-d_{Boost}}=\frac{U_{high}}{1+d_{Boost}}\\ U_{Q1\_Buck}=U_{Q2\_Buck}=U_{Q3\_Buck}=\frac{U_{low}}{d_{Buck}}=\frac{U_{high}}{2-d_{Buck}}\end{array}$$

(15)

By using above analysis and the Kirchhoff voltage law (KVL) to the switches, the voltage stress on the switches can be obtained as

$$\begin{gathered} \hspace{1em}\{\begin{array}{l}{I}_{Q1\_Boost}=\frac{2}{1-d_{Boost}}{I}_{high}\\ I_{Q2\_Boost}=I_{Q3\_Boost}=-\frac{1}{1-d_{Boost}}{I}_{high}\end{array} \\ \{\begin{array}{l}{I}_{Q1\_Buck}=-\frac{2}{2-d_{Buck}}{I}_{low}\\ I_{Q2\_Buck}=I_{Q3\_Buck}=\frac{1}{2-d_{Boost}}{I}_{low}\end{array} \end{gathered}$$

(16)

2.2. Construction of Presented Converter II

The main theoretical waveforms of the converter II in CCM are identical with the converter I. The steady-state analyses with respect to the operating direction of the converter II are shown as below.

(1) Boost mode of the converter II:

Similar to converter I, converter II also has two modes in the boost mode. The operating conditions of the switches are the same as those of converter I. Detailed analysis is presented in [23], when the power switch Q₁ is ON, and Q₂ and Q₃ are turned OFF. The symbolic representation is the same as the converter I. In light of Figure 7a, by using the KVL and KCL laws to the circuit, the following equations based on this state can be formed as

$$\{\begin{array}{l}{U}_{L1}=U_{low}\\ U_{L2}=U_{C3}-U_{C2}\\ U_{C1}+U_{C2}=U_{high}\end{array}$$

(17)

$$\{\begin{array}{l}{i}_{C3}=-i_{L2}\\ i_{L2}=i_{C2}\\ i_{high}=i_{C1}\end{array}$$

(18)

when the switching state is opposed to previous operation. As shown in Figure 7b. It can be concluded that

$$\{\begin{array}{l}{U}_{L1}=U_{low}-U_{C3}=U_{low}-U_{C1}\\ U_{L2}=-U_{C2}\\ U_{C1}+U_{C2}=U_{high}\end{array}$$

(19)

$$\{\begin{array}{l}{i}_{L1}-i_{C1}-i_{high}=i_{C3}\\ i_{L2}=i_{C2}+i_{high}\end{array}$$

(20)

By applying the volt-second balance law to L₁ and L₂ according to Equations (17) and (19), the voltage gain M_Boost of the proposed converter II in CCM can be obtained as

$$M_{Boost}=\frac{1+d_{Boost}}{1-d_{Boost}}$$

(21)

Moreover, the voltage stresses across capacitors C₁ and C₂ can be expressed as

$$\{\begin{array}{l}{U}_{C1}=\frac{U_{low}}{1-d_{Boost}}=\frac{U_{high}}{1+d_{Boost}}\\ U_{C2}=\frac{d_{Boost}{U}_{low}}{1-d_{Boost}}=\frac{d_{Boost}{U}_{high}}{1+d_{Boost}}\end{array}$$

(22)

By using the ampere-second balance law of capacitors with Equations (18) and (20), the average inductor currents I_L1 and I_L2 on the inductors L₁ and L₂ can be expressed as

$$\{\begin{array}{l}{I}_{L1}=\frac{1+d_{Boost}}{1-d_{Boost}}{I}_{high}\\ I_{L2}=I_{high}\end{array}$$

(23)

(2) Buck mode of the Converter II:

Similar to converter I, converter II also has two modes in the buck mode. The operating conditions of the switches are same as converter I.

[t₀–t₁]: This operating mode is effective when the power switch Q₁ is OFF and Switches Q₂ and Q₃ are ON. The inductors L₁ and L₂ are in charging mode while capacitor C₃ is discharging. In accordance with Figure 8a, by using the KVL and KCL laws to the circuit, the formulas below are derived for this case

$$\{\begin{array}{l}{U}_{L1}=U_{C1}-U_{low}=U_{C3}-U_{low}\\ U_{L2}=U_2\\ U_{C1}+U_{C2}=U_{high}\end{array}$$

(24)

$$\{\begin{array}{l}{i}_{high}+i_{C3}-i_{L1}=i_{C1}\\ i_{C2}=i_{L2}\end{array}$$

(25)

[t₁–t₂]: The switching state is reverse to the previous state. Both inductors are in discharge mode, and Capacitors C₁ and C₃ are charged by the current that flows through the inductor L₂. Similarly, from Figure 8b, the following equations is derived.

$$\{\begin{array}{l}{U}_{L1}=-U_{low}\\ U_{L2}=U_{C2}-U_{C3}\\ U_{C1}+U_{C2}=U_{high}\end{array}$$

(26)

$$\{\begin{array}{l}{i}_{C3}=i_{L2}=i_{C2}\\ i_{C1}=i_{high}\end{array}$$

(27)

According to Equations (24) and (26), the voltage conversion ratio M_Boost and voltage stresses on the capacitors of the proposed Converter II in CCM can be expressed as

$$M_{Buck}=\frac{d_{Buck}}{2-d_{Buck}}$$

(28)

$$\{\begin{array}{l}{U}_{C1}=\frac{U_{low}}{d_{Buck}}=\frac{U_{high}}{2-d_{Buck}}\\ U_{C2}=\frac{(1-d_{Buck})U_{low}}{d_{Buck}}=\frac{(1-d_{Buck})U_{high}}{2-d_{Boost}}\end{array}$$

(29)

According to Equations (25) and (27), average currents I_L1 and I_L2 on inductors L₁ and L₂ can be obtained as

$$\{\begin{array}{l}{I}_{L1}=I_{low}\\ I_{L2}=\frac{d_{Buck}}{2-d_{Buck}}{I}_{low}\end{array}$$

(30)

(3) Voltage and current stresses of the power switches (converter II):

It can be deduced that the voltage and current stress of the power switches about converter II are identical with converter I, which is shown below

$$\begin{array}{l}{U}_{Q1\_Boost}=U_{Q2\_Boost}=U_{Q3\_Boost}=\frac{U_{low}}{1-d_{Boost}}=\frac{U_{high}}{1+d_{Boost}}\\ U_{Q1\_Buck}=U_{Q2\_Buck}=U_{Q3\_Buck}=\frac{U_{low}}{d_{Buck}}=\frac{U_{high}}{2-d_{Boost}}\end{array}$$

(31)

$$\begin{gathered} \hspace{1em}\{\begin{array}{l}{I}_{Q1\_Boost}=\frac{2}{1-d_{Boost}}{I}_{high}\\ I_{Q2\_Boost}=I_{Q3\_Boost}=-\frac{1}{1-d_{Boost}}{I}_{high}\end{array} \\ \{\begin{array}{l}{I}_{Q1\_Buck}=-\frac{2}{2-d_{Buck}}{I}_{low}\\ I_{Q2\_Buck}=I_{Q3\_Buck}=\frac{1}{2-d_{Boost}}{I}_{low}\end{array} \end{gathered}$$

(32)

2.3. Construction of the Proposed Converter III

The main theoretical waveforms of proposed converter III in CCM are presented in Figure 9a,b, and the steady-state analyses with respect to the operating modes of converter III are shown below.

(1) Boost mode of the converter III:

Q₁ and Q₂ are turned ON, Q₃ is turned OFF, thus, d₁ = d₂ = 1 − d₃ = d_Boost. The switching states are depicted in Figure 10a,b.

When switches Q₁ and Q₂ are turned ON, and switch Q₃ is turned OFF. By the detailed analysis about Reference [24], the voltages stresses across L₁ and L₂ can be expressed as

$$v_{L1}=v_{L2}=V_{low}$$

(33)

When the switching state is opposed to previous operation. From reference [24], the voltage stresses across L₁ and L₂ can be expressed as

$$v_{L1}=v_{L2}=\frac{V_{high}-V_{low}}{2}$$

(34)

Applying the volt–second balance law to L₁ and L₂, the voltage gain can be expressed as

$$M_{Boost}=\frac{V_{low}}{V_{high}}=\frac{1+D_{Boost}}{1-D_{Boost}}$$

(35)

According to the switching state as shown in Figure 10a,b, and the KVL. The voltage across Q₁, Q₂, and Q₃ can be expressed as

$$\{\begin{array}{l}{V}_{Q1}=V_{Q2}=\frac{V_{high}+V_{low}}{2}\\ V_{Q3}=V_{low}+V_{high}\end{array}$$

(36)

Similarly, according to the switching state as shown in Figure 10a,b, in addition to the KCL, the current across Q₁–Q₃ can be expressed as

$$\{\begin{array}{l}{I}_{Q1\_Boost}=I_{Q2\_Boost}=\frac{1}{2}{I}_{low}\\ I_{Q3\_Boost}=-I_{low}\end{array}$$

(37)

(2) Buck mode of the converter III:

This is reverse to the boost mode, the gate signal of Q₁ is complementary to Q₂ and Q₃; thus, d₃ = 1 − d₁ = 1 − d₂ = d_Buck. The topological states are presented in detail in Figure 11a,b.

[t₀–t₁]. When switch Q₃ is ON, and Switches Q₁ and Q₂ are OFF, the switching state is presented in Figure 11a. DC bus voltage is charging the inductors L₁ and L₂, and the output capacitor C_o discharging energy to the load. Consequently, it can be calculated that

$$v_{L1}=v_{L2}=\frac{V_{high}-V_{low}}{2}$$

(38)

[t₁–t₂]. In this state, switching state is opposed to previous operation. The equivalent current flow circuit is shown in Figure 11b. The battery voltage, inductors L₁ and L₂ are discharging energy to the output capacitor C_o and the load. Therefore, voltage stresses across inductors L₁ and L₂ can be expressed as

$$v_{L1}=v_{L2}=-V_{high}$$

(39)

By using the same theory to L₁ and L₂, the voltage gain can be expressed as

$$M_{Buck}=\frac{V_{high}}{V_{low}}=\frac{D_{Buck}}{2-D_{Buck}}$$

(40)

According to the switching state of the buck mode, as shown in Figure 11a,b, in addition to the KVL, the voltage stress can be expressed as

$$\{\begin{array}{l}{V}_{Q1}=V_{Q2}=\frac{V_{low}+V_{high}}{2}\\ V_{Q3}=V_{low}+V_{high}\end{array}$$

(41)

Similarly, in the light of the switching state of the buck mode, as shown in Figure 11a,b, in addition to the KCL, the current stress can be derived as

$$\{\begin{array}{l}{I}_{Q3\_Buck}=-I_{high}\\ I_{Q1\_Buck}=I_{Q2\_Buck}=\frac{1}{2}{I}_{high}\end{array}$$

(42)

2.4. Voltage and Current Ripple Calculation of the Proposed Converters

In terms of the conventional Boost converter, it can be concluded that the current ripple (Δi_L) on the inductance is calculated by

$$\Delta i_L=\frac{V_{low}\cdot D}{L\cdot f}$$

(43)

where f is the switching frequency, and L is the inductance.

In addition, the output voltage ripple (∆v_c) can be obtained from the output capacitor.

$$\Delta v_C=\frac{V_{high}\cdot D}{R\cdot f\cdot C}$$

(44)

where R is the output resistance, C is the output capacitance.

According to the above analysis, the voltage ripple on the output voltage and current ripple on the inductances L₁ and L₂ about proposed converter III are equal to the boost converter because of the similar topological states.

As for converter I and II, it can be concluded from the previous analysis, the output capacitors are connected in stack, so the voltage ripple ratio of the converter I and II is half of the boost converter (1/2∆v_c). That means converter I and II are easier to select the output capacitor due to the small voltage ripple.

In terms of the current ripple on the inductance, it is equal to the boost converter because of the connectively style for the inductor is the same with the boost converter.

2.5. Comparisons with Conventional Converters

In general, the losses of the inductor, capacitor, and switch cause the parasitic effects on the converter. In these components, the inductor parasitic resistance has the greatest influence on the converter voltage conversion ratio. Therefore, when considering the influence of the inductance parasitic resistance, the voltage gain ratio of the conventional converter, and the proposed converters can be expressed as follows

$$M_B{}_{oost}=\frac{1}{1-D}(\frac{1}{1+\frac{r_l}{{(1-D)}^{2}R}})$$

(45)

$$M_{Buck-B}{}_{oost}=\frac{D}{1-D}(\frac{1}{1+\frac{r_l}{{(1-D)}^{2}R}})$$

(46)

$$M_{p-converters}=\frac{1+D}{1-D}(\frac{1}{1+\frac{r_l}{{(1-D)}^{2}R}})$$

(47)

which D is the duty cycle, and r_l represent as the inductor parasitic resistance, R is the load resistance.

These three equations are derived by applying the volt–second balance law to inductors, if R/r_l is set to 0.01, the voltage gain ratio can be obtained under different duty cycle.

The comparison between the voltage conversion ratio and duty cycle of the conventional converters and the proposed converters are shown in Figure 12. It can be seen that when considering the influence of parasitic components, voltage gain ratio sharply decrease at large duty cycle. However, under the same duty cycle, the voltage gain ratio of the proposed converters is higher than conventional converters. Therefore, under large duty cycle, the proposed converters have a better step-up voltage performance than the conventional converters.

2.6. Efficiency and Power Loss Calculation

In order to compare the efficiency of the proposed converters with the traditional converters, the losses of the converters can be calculated by using the actual parameters of the components. The system efficiency can be attained by calculating the loss distribution.

Conduction and switching losses of the metal oxide semiconductor field effect transistor (MOSFETs) are defined as

$$P_{loss\_mosfet}=R_{ds(on)}{I}_{mosfet\_rms}^2+2V_{dc}{I}_{mosfet}f(t_r+t_f)$$

(48)

where R_ds is the conduction resistance, t_r and t_f represent the rise time and fall time of the switch.

The copper loss and the core loss of the inductor can be calculated as

$$P_{C\_L}=R_{win}{I}_L^2+P_{core\_L}$$

(49)

$$P_{Core\_L}=k_i{f}^{\alpha }{B}^{\beta }V$$

(50)

where R_win is the ac resistance of the windings. k_i, α, and β are empirical constants determined by the core material characteristic. k_i = 0.33, α = 1.98, and β = 1.64. f, B, and V are operating frequency, flux density and volume of the core [26].

By considering the dielectric characteristic of capacitors, the loss of capacitors is given by Equation (51), where tan δ(f) is the dissipation factor of capacitors and I indicate the current stress on the capacitors [26].

$$P_{loss\_cap}=\frac{\tan \delta (f)}{2\pi f}(\frac{I_{low}^2}{C_0}+\frac{I_{high}^2}{C_1}+\frac{I_{high}^2}{C_2}+\frac{I_3^2}{C_3})$$

(51)

Thus, the total loss can be calculated as

$$P_{T\_L}=P_{loss\_mosfet}+P_{core\_L}+P_{c\_L}+P_{loss\_cap}+P_{extra\_L}$$

(52)

which P_{extra_L} represent the extra loss of the converters.

Based on the above analysis, the efficiency of conventional converters and proposed converters with different duty cycle is calculated and presented in Figure 13.

The efficiency comparison between proposed converters and traditional converters are shown in Figure 13. The efficiency of the converters decreases gradually with the increase of the duty cycle. It is noted that the efficiency of the traditional converters is lower than efficiency of the proposed converters in the case of a large duty cycle. Under the large duty cycle, due to the influence of parasitic elements, voltage conversion ratio and efficiency about traditional converters is rapidly falling off. It is obtained that efficiency of the proposed converters is 6% higher than the conventional converters when the converters operate in large duty cycle.

From

Table 1. Comparison of proposed converters and conventional converters.

Topology	Converter I	Converter II	Converter III	Buck-Boost	SEPIC	Ćuk
Input current	Continuous	Continuous	Discontinuous	Discontinuous	Continuous	Continuous
Switch voltage stress	Vhigh/(1 + DBoost) 1 Vhigh/(2 − DBuck) 2	Vhigh/(1 + DBoost) 1 Vhigh/(2 − DBuck) 2	(Vlow + Vhigh)/2 3 Vlow + Vhigh 4	Vin	Vin	Vin
Voltage gain ratio	(1 + D)/(1 − D) D/(2 − D)	(1 + D)/(1 − D) D/(2 − D)	(1 + D)/(1 − D) D/(2 − D)	D/(1 − D)	D/(1 − D)	D/(1 − D)
Common ground	YES	NO	YES	YES	YES	YES
Num. of switches	3	3	3	1	1	1
Num. of inductors	2	2	2	1	2	2
Voltage Ripple	$\frac{V_{high}\cdot D}{2\ast R\cdot f\cdot C}$	$\frac{V_{high}\cdot D}{2\ast R\cdot f\cdot C}$	$\frac{V_{high}\cdot D}{R\cdot f\cdot C}$	$\frac{V_{high}\cdot D}{R\cdot f\cdot C}$	$\frac{V_{high}\cdot D}{R\cdot f\cdot C}$	$\frac{V_{high}\cdot D}{R\cdot f\cdot C}$
Current Ripple	$\frac{V_{low}\cdot D}{L\cdot f}$	$\frac{V_{low}\cdot D}{L\cdot f}$	$\frac{V_{low}\cdot D}{L\cdot f}$	$\frac{V_{low}\cdot D}{L\cdot f}$	$\frac{V_{low}\cdot D}{L\cdot f}$	$\frac{V_{low}\cdot D}{L\cdot f}$

¹ Switch voltage stress in Boost mode. ² Switch voltage stress in Buck mode. ³ Switch voltage stress on Q₁ and Q₂. ⁴ Switch voltage stress on Q₃.

, each topology has three power switches. With respect to Converter III, the voltage stress on the high voltage side switch is relatively high than Converters I and II. However, Converter III is also suitable for high voltage gain applications because of the input voltage is relatively low compared with the output voltage. In addition, the current stress on the switches are lower than converter I and II. With respect to Converter II, the voltage and current stress on the switches and voltage gain ratio are equal to those of Converter I. However, the input and output are not common ground, which can lead to an extra dv/dt issue between the battery side and dc voltage side. The detailed comparison of proposed converters and conventional converters is also listed in Table 1.

3. Experiment Results

3.1. Experimental Results in the Boost/Buck Mode

To verify the theoretical analysis of the proposed converters, three 200-W prototypes are developed in the laboratory, as shown in Figure 14. The parameters of the test prototypes are presented in

Table 2. Parameters of the test converter.

Parameters	Symbol	Value
Battery voltage	Vlow	40–130 [Vdc]
Output voltage	Vhigh	250 [Vdc]
Inductor	L1L2	102 [uH]
Output Capacitor	C1C2	50 [uF]
Capacitor	C3	3.37 [uF]
Output power	PO	200 [W]

. A double loop proportional-integral (PI) control, (inner current control loop and outer voltage control loop), as shown in Figure 15, is applied to the experiment.

Under the test conditions V_in = 40 V, V_o = 250 V, f_s = 25 KHz, and P_o = 200 W; experimental results with respect to converter I are presented in Figure 16.

The voltage stress waveform of Q₁, Q₂ and Q₃ in the boost mode are presented in Figure 16a. It can be seen that the voltage stresses on Q₁–Q₃ are approximately 150 V, which indicates that the voltage stresses on Q₁–Q₃ are equal to V_high/(1 + D). Under the same situation, Figure 16c shown the inductors current under the boost mode.

The voltage stress waveforms of Q₂ and Q₃, and Q₁ in buck mode are presented in Figure 16b. It can be revealed that the voltage stresses on Q₁–Q₃ are approximately 150 V, which indicates that the voltage stresses on Q₁–Q₃ are equal to V_high/(1 + D). Under the same conditions, Figure 16d shown the inductors current under the buck mode.

According to the previous analysis, in boost mode and buck mode, the current ripple rates of L₁ and L₂ are lower than those of the converters in [22], which makes it easier to design inductance.

Under the same experimental conditions, Converters II and III are evaluated in regard to the input and output voltages, voltage stress on the switches, and current stress on the inductors. Based on their similar characteristics, Converters I and II have similar waveforms. With respect to Converter III, the results of the experiment are presented in Figure 17.

The voltage stress waveforms of Q₁ and Q₂, and Q₃ in the boost mode are presented in Figure 17a. The voltage stresses on Q₁–Q₂ are 150 V, which indicates that the voltage stresses on Q₁–Q₃ are equal to (V_o + V_in)/2. On the other hand, the voltage stress on Q₃ is 300 V, which indicates that the voltage stresses on Q₃ are equal to V_o + V_in. Under the same situation, Figure 17c shown the inductors current under the boost mode.

The voltage stress waveforms of Q₂ and Q₃, and Q₁ in buck mode are presented in Figure 17b. The voltage stresses on Q₁–Q₂ are 150 V, which indicates that the voltage stresses on Q₁–Q₂ are equal to (V_o + V_in)/2. On the contrary, the voltage stress on Q₃ is 300 V, which indicates that the voltage stresses on Q₃ are equal to V_o + V_in. Under the same conditions, Figure 17d shown the inductors current under the buck mode.

It can be seen that the current ripple rate about inductors L₁ and L₂ are identical because of the same operating mode.

3.2. Measured Efficiency Analysis of the Converters

To analyze the performances of the proposed converters, the efficiencies of experimental under different input voltage are presented in Figure 18. From the Figure 18, it can be revealed that the maximum efficiencies of converter I in boost mode and buck mode are 92% and 92.2%, respectively. In addition, converter II has similar efficiency rates with converter I because the two prototypes have identical components count and similar topological states. With respect to Converter III, it exhibits a lower efficiency because the high-voltage stress on the switch.

Efficiency comparison between calculated results and experiment results are shown in Figure 19, when the proposed converters operating in boost mode, the calculated efficiency is similar with the experiment results, which confirm the correctness of the formula calculation of Equations (48)–(52) and verify the accuracy of experiment results. In the case of high voltage gain ratio, the experimental results are lower than the calculation results. Because the calculated results are approximate value, and the temperature changes of switches and other components have an influence on the experiment efficiency. However, these changes are ignored in the case of calculation.

3.3. Power Loss Distribution Analysis of Proposed Converters

The power loss analysis are calculated under the experiment condition with U_low = 120 V, U_high = 250 V, and P_o = 200 W. When the suggested converters operate in boost mode, the comparison of loss analysis is presented in Figure 20a. According to analyzing results of the power losses distribution, the maximum power loss is calculated as 20.95 W, which is due to Converter III. It can be convinced that the dominant sources of power losses are due to the switching losses, which account for 25%, 26%, and 30% of the total losses, respectively. In case of the presented converters operate in buck mode, the loss distribution is presented in Figure 20b. By analyzing the distribution of power losses, the maximum power loss is found to be 20.4 W, which is due to Converter III. It can be maintained that the dominant sources of power losses are due to the switching losses.

4. Conclusions

In this study, three novel bidirectional DC–DC converters without transformers and with high voltage gains are developed. The set of converters benefit from a high voltage conversion ratio in the boost and buck modes. Detailed comparisons are made with respect to the operating mode, number of components, current and voltage ripple and efficiency. According to the losses calculation results, the power efficiency is 6% higher than traditional converter when converters operate in large duty cycle. In addition, the voltage ripple is relatively low, which increases design flexibility for the passive component. Finally, the experimental results are presented to verify the feasibility of the proposed converters. The results reveal that converter I demonstrated the highest efficiency in boost (92%) and buck (92.2%) modes. The final experimental results confirm that the converters provide a good trade-off between the voltage gain ratio, voltage, and current stresses, and the components count.