A Coupled-Inductor Interleaved LLC Resonant Converter for Wide Operation Range

Abstract

In this paper, a coupled-inductor interleaved LLC resonant converter (CI-ILLC) was proposed, which can achieve extensive operation range applications by multiplexing inductors and switches. In this proposed CI-ILLC, the coupled-inductor not only serves as a filter inductor but also plays the role of transformer to improve the power density. By changing the modulation methods, the proposed converter can work at three modes for a wide operation range, namely high gain (HG) mode, medium gain (MG) mode, and low gain (LG) mode. Moreover, the interleaved structure greatly reduces the current ripple and current stress of switches. Besides, in HG and MG modes, all switches can realize zero-voltage switching, with high energy transmission efficiency. Finally, the simulation and experiment results of the prototype with 120–200 V input and 50–200 V output are presented to verify the viability of the proposed converter.

1. Introduction

In recent years, a large amount of literature has emerged on the topic of achieving high efficiency in a wide operation range due to the urgent needs of complex applications, such as renewable energy generation, hybrid electric vehicles, and undersea cabled observatories [1,2]. On the other hand, special requirements, such as low current ripple, would be crucial technical indicators for undersea cabled observatories because the current ripple may greatly affect the service life of equipment [3,4]. Therefore, wide-voltage-gain DC/DC converters with low current ripple and high-power density have become an indispensable part of such applications in order to realize the subsea source interface.

The LLC resonant converter has been paid much attention because of its zero-voltage switching (ZVS) of main switches, wide operation range, low electromagnetic interference, and high-power density [5,6,7,8,9,10]. Normally, the switching frequency range needs to be expanded to achieve a wide operation range when the traditional frequency modulation (FM) is applied to the LLC resonant converter. Then, the ZVS is hard to realize under light-loaded and the current reflow decreases the efficiency for the PWM controlled LLC converter. These shortcomings hinder the LLC converter’s application to a wider operation occasion.

Compared with the traditional voltage-fed DC/DC converters, current-fed converters have demonstrated superior performance in low input current ripples, inherent short circuit protection, lower high-frequency transformer turns ratio, no duty cycle loss, and easier current controllability [11,12,13]. In addition to helping reduce switching loss, the current-fed converters have the ability of high switching frequency, leading to a significant decrease in the passive devices and transformer size. However, the high voltage stress across the main switches of the topologies is inevitable. Rathore et al. [14] and Al-Atbee et al. [15] have proposed two active-clamped L-L type current-fed converters. The active clamp circuit provides a path for the capacitor to absorb the turn-off voltage spike, and the energy stored in the series inductor assists in achieving ZVS of main switches. Resonant current-fed converters take advantage of the transformer’s parasitic elements as a part of the resonant tank to decrease voltage spikes [16,17]. A novel fixed-frequency PWM-controlled LC series-resonant converter was proposed in [18]; the duty cycle is the only degree of freedom and changes around 0.5 to obtain a wider voltage gain. The amplitude and direction of power flow can be adjusted conveniently by using a simple PWM method. Moreover, interleaved topologies are commonly regarded as a promising solution to further reduce the current ripple [19,20,21]. Ref. [22] has proposed an interleaved coupled-inductor-based bidirectional converter, and the interleaved topology is adopted to reduce the current ripple. Besides, the coupled inductors are applied to improve the voltage gain when no other devices are required.

At present, some combinational circuits have attracted more and more attention because they can meet a wide working range. A ZVS converter was proposed in [23], which connects a flyback unit and a voltage-double-unit into a boost converter. However, the lack of galvanic isolation limits the potential for further expansion. Moreover, an improved buck-boost + LLC cascaded converter was proposed in [24], which has two modes, including constant current mode and constant voltage mode. The power density can be improved by sharing the switches in the boost converter and LLC resonant converter. Additionally, by combining the advantages of the boost, LCL resonant, and flyback converter, a current-fed LCL resonant converter was proposed in [25], which can work at three voltage gain modes with three different PWM methods, and it provide ZVS for all the switches over a wide output voltage range.

A novel coupled-inductor interleaved LLC resonant converter (CI-ILLC), featuring a wide operation range, wide ZVS range, and low current ripple, has been proposed in this paper as shown in Figure 1. Interleaved configuration is adopted to ensure that low current ripple and low current stress can be achieved. The coupled inductor not only operates as a filter inductor but also plays the role of transformer simultaneously, which improves the power density. Besides, the proposed converter can work at three modes, namely high gain (HG) mode, medium gain (MG) mode, and low gain (LG) mode, through the different modulation methods. Moreover, the ZVS is realized due to the characteristic of LLC resonance under the proper design.

The rest of the paper is organized as follows: Section 2 gives a brief description of the proposed CI-ILLC and analyzes the operating principles in different modes. The steady-state analysis, input current ripple suppression mechanism, and ZVS condition are discussed in Section 3. The control block diagram and topologies comparison are given in Section 4 and Section 5. Section 6 provides simulation and experiment results of a 1200 W prototype designed for 120–200 V input and 50–200 V output to demonstrate the validity of CI-ILLC and the accuracy of the analysis.

2. Circuit and Principle of Operation

Figure 1a,b shows the topology of the proposed CI-ILLC and its equivalent circuit. As shown in Figure 1b, coupled-inductor L₁ is composed of the leakage inductor L_s1, magnetic inductor L_m1, primary winding N_p1, N_p11, and secondary winding N_s1; coupled-inductor L₂ is composed of the leakage inductor L_s2, magnetic inductor L_m2, primary winding N_p2, N_p21, and secondary winding N_s2. In HG mode, two boost half-bridges are operating with interleaving and are composed of four switches (S₁, S₂, S₃, S₄) and two leakage inductors L_s1, L_s2. The proposed CI-ILLC works as a traditional LLC resonant converter. The resonant tank is composed of the magnetizing inductor L_m, resonant inductor L_r, and resonant capacitor C_r. I₁, I₂, I_Lr, and I_Lm are the current flows through L_s1, L_s2, L_r, and L_m, respectively. V_i and V_o are input and output voltage, V_Cc is the voltage across the clamp capacitor Cc, and V_L and V_H are the minimum and maximum voltage across the L_m1 and L_m2. I_i is the input current, and R is the load. The turns ratio of the transformer is defined as n = n₁:n₂. A control variable D_s is introduced to adjust voltage gain in MG mode. In LG mode, there is no phase shift between two half bridges. two coupled inductors work as transformers of the forward converter, and primary winding N_p11, N_p21 are the magnetic flux reset winding, secondary winding N_s1, N_s2 provides the energy to load. L_f is used as a filter inductor, and the current flow through it is defined as I_Lf. n_IC = n_s1:n_p1 = n_s2:n_p2, n_IC2 = n_p11:n_p1 = n_p21:n_p2.

Through the change of the modulation strategy, three different modes can be realized.

2.1. HG Mode

Fixed-frequency pulse-width-modulation control method with frequency f_s is applied in the HG mode, and the switching frequency is equal to the LLC resonant frequency f_r at rated condition.

The switches on the same bridge arm operate complementarily. S₁ and S₃ have the same duty cycle D but have 180° phase-shift angles (β = 180°), and the same is for S₂ and S₄. The input voltage of resonant tank V_AB is AC voltage with nearly rectangular waveform; the duty cycle equals to the minimum of D and 1-D, the maximum voltage equals to the V_i/D, and the sum voltage across the N_s1 and N_s2 equals to 0. The average value of I₁, I₂ are the same and equal to I_i/2 due to the same value of coupled inductor L₁, L₂. The current ripple of I₁ and I_i are denoted as ΔI_Ls and ΔI_i, respectively. Then, we obtain the following parameter definitions:

$$m=L_m/L_r$$

(1)

$${\omega }_r=2\pi f_r$$

(2)

$$Z_r=L_r/C_r$$

(3)

$${\omega }_{rm}=2\pi f_r/\sqrt{1+m}$$

(4)

$$Z_{rm}=L_r\sqrt{1+m}/C_r$$

(5)

$$f_m=f_r/\sqrt{1+m}$$

(6)

A switching cycle can be divided into 10 operational stages, and only the first five stages are analyzed in detail because the last five stages are symmetrical operations. The operating principles can be analyzed according to the key operational waveforms shown in Figure 2 and Figure 3, and they illustrate the corresponding equivalent circuits at the first five stages for D > 0.5.

Stage 1 [t₀, t₁]: S₃ has been conducted before this stage and S₁ turns on under ZVS at t₀. The magnetizing voltage V_Lm is clamped by the negative output voltage and I_Lm decreases. The input voltage of resonant tank V_AB is equal to zero, and the resonant current I_Lr increases in a sinusoidal manner at the resonant frequency f_r. In addition, the voltage across the L_s1, L_s2 is equal to V_i–V_Cc–V_L, and both of them are being discharged. S₁ and S₃ have been turned on, so S₂ and S₄ are clamped by the V_Cc. The currents I_Lr, I_Lm and the voltage V_Cr can be described as

$$\{\begin{array}{c}{I}_{Lr}(t)=I_{Lr}(t_0)\cos {\omega }_r(t-t_0)-((V_{Cr}(t_0)-n{V}_o)/Z_r)\sin {\omega }_r(t-t_0)\\ I_{Lm}(t)=I_{Lm}(t_0)-n{V}_o(t-t_0)/L_m\\ V_{Cr}(t)=n{V}_o+(V_{Cr}(t_0)-n{V}_o)\cos {\omega }_r(t-t_0)+I_{Lr}(t_0)Z_r\sin {\omega }_r(t-t_0)\end{array}$$

(7)

Stage 2 [t₁, t₂]: At t₁, I_Lr equals to I_Lm. There are no current flows through the transformer’s winding during this stage, and there is no power transfer to the secondary side. Resonance begins between L_r, L_m, and C_r at resonant frequency f_m. I_Lr barely changes during this stage due to L_m being greater than four times that of L_r. Since S₁ and S₃ keep conducting in this stage, boost inductors L_s1, L_s2 are still being discharged, and S₂ and S₄ are still being clamped by the capacitor voltage V_Cc. The currents I_Lr, I_Lm and the voltage V_Cr can be obtained by

$$\{\begin{array}{c}{I}_{Lr}(t)=I_{Lr}(t_1)\cos {\omega }_{rm}(t-t_1)-(V_{Cr}(t_1)/Z_{rm})\sin {\omega }_{rm}(t-t_1)\\ I_{Lm}(t)=I_{Lr}(t)\\ V_{Cr}(t)=V_{Cr}(t_1)\cos {\omega }_{rm}(t-t_1)+I_{Lr}(t_1)Z_{rm}\sin {\omega }_{rm}(t-t_1)\end{array}$$

(8)

Stage 3 [t₂, t₃]: At the moment of t₂, the drive signal of S₃ drops to zero, S₃ is turned off, and S₁ still conducts. The converter enters the dead-time between S₃ and S₄. There is still no energy transfer to the secondary side, and the secondary diodes are in the off state. The junction capacitors of S₃ and S₄ begin to be charged and discharged, respectively.

Stage 4 [t₃, t₄]: At t₃, the voltage across the junction capacitor of S₄ declines to zero, and S₄ realizes the ZVS turn-on. During this stage, the input voltage of resonant tank V_AB is equal to the V_Cc, and V_Lm is clamped by the output voltage. Resonance happens between L_r and C_r, and primary resonant current I_Lr increases in a sinusoidal manner at the resonant frequency f_r. The voltage across the L_s1 and L_s2 are V_Cc–V_i + V_H, V_i–V_H, respectively. Moreover, L_s1, L_s2 are being discharged and charged, respectively, because S₁ and S₄ are turned on. And S₂, S₃ are being clamped by the capacitor voltage V_Cc. Currents I_Lr, I_Lm, and the voltage across the resonant capacitor V_Cr can be expressed as

$$\{\begin{array}{c}{I}_{Lr}(t)=I_{Lr}(t_3)\cos {\omega }_r(t-t_3)+((V_{Cc}-n{V}_o-V_{Cr}(t_3))/Z_r)\sin {\omega }_r(t-t_3)\\ I_{Lm}(t)=I_{Lr}(t_3)+n{V}_o(t-t_3)/L_m\\ V_{Cr}(t)=(V_{Cc}-n{V}_o)-(V_{Cc}-n{V}_o-V_{Cr}(t_3))\cos {\omega }_r(t-t_3)+I_{Lr}(t_3)Z_r\sin {\omega }_r(t-t_3)\end{array}$$

(9)

Stage 5 [t₄, t₅]: At the moment of t₄, S₄ is turned off while S₁ keeps on conducting. The converter enters the dead-time between S₃ and S₄ again. During this stage, the junction capacitors of S₃ and S₄ begin to be discharged and charged, respectively, by virtue of I_Lr and I₂. The body diode of S₃ starts conducting at the moment the voltage across junction capacitors of S₃ decreases to zero. Thus, the ZVS turn-on of S₃ can be realized.

The operation principles for the case D ≤ 0.5 are symmetrical to the analysis above.

2.2. MG Mode

The MG mode expands the zone of dead time D_s between the switches on the same arm to obtain a lower voltage gain with D > 0.5, and D_s is defined as the phase shift angle from the falling edge of the gating signal of S₂ to the rising edge of that of S₁. S₁ and S₃ have the same duty cycle but have 180° phase-shift angles (β = 180°), and the same is for S₂ and S₄. the key operational waveforms are shown in Figure 4.

Stage 1 [t₀, t₁]: Before this stage, S₃ has been conducted, S₂ is turned off, the voltage across the L_s1, L_s2 is equal to V_Cc–V_i–V_L, and both of them are being discharged. After t₀, S₁ is turned on, this stage is similar to Stage 2 of the HG mode, I_Lr is equal to I_Lm at t₀, and resonance begins between L_r, L_m, and C_r at resonant frequency f_m. There are no current flows through the transformer’s winding during this stage and no power transfer to the secondary side. The currents I_Lr, I_Lm and the voltage V_Cr can be obtained by

$$\{\begin{array}{c}{I}_{Lr}(t)=I_{Lr}(t_0)\cos {\omega }_{rm}(t-t_0)-(V_{Cr}(t_0)/Z_{rm})\sin {\omega }_{rm}(t-t_0)\\ I_{Lm}(t)=I_{Lr}(t)\\ V_{Cr}(t)=V_{Cr}(t_0)\cos {\omega }_{rm}(t-t_0)+I_{Lr}(t_0)Z_{rm}\sin {\omega }_{rm}(t-t_0)\end{array}$$

(10)

Stage 2 [t₁, t₂]: This interval is dead time between S₃ and S₄, which has not been expanded compared to HG mode.

Stage 3 [t₂, t₃]: At t₂, S₄ realizes the ZVS turn-on. This stage corresponds to Stage 4 of the HG mode. The voltage across the L_s1 and L_s2 are V_Cc–V_i + V₁, V_i–V₁, respectively. L_s1, L_s2 are being discharged and charged, respectively, because S₁ and S₄ are turned on. Currents I_Lr, I_Lm, and the voltage across the resonant capacitor V_Cr can be expressed as

$$\{\begin{array}{c}{I}_{Lr}(t)=I_{Lr}(t_2)\cos {\omega }_r(t-t_2)+((V_{Cc}-n{V}_o-V_{Cr}(t_2))/Z_r)\sin {\omega }_r(t-t_2)\\ I_{Lm}(t)=I_{Lr}(t_2)+n{V}_o(t-t_2)/L_m\\ V_{Cr}(t)=(V_{Cc}-n{V}_o)-(V_{Cc}-n{V}_o-V_{Cr}(t_2))\cos {\omega }_r(t-t_2)+I_{Lr}(t_2)Z_r\sin {\omega }_r(t-t_2)\end{array}$$

(11)

Stage 4 [t₃, t₄]: At the moment of t₃, S₄ is turned off and only S₁ still conducts. This stage is the main difference between HG mode and MG mode. During this stage, V_AB comes back to zero, the voltage across the L_s1, L_s2 is equal to V_Cc–V_i–V_L, and both of them are being discharged. I_Lr decreases linearly and rapidly. Currents I_Lr, I_Lm, and the voltage across the resonant capacitor V_Cr can be expressed as

$$\{\begin{array}{c}{I}_{Lr}(t)=I_{Lr}(t_0)\cos {\omega }_r(t-t_3)-((V_{Cr}(t_0)-n{V}_o)/Z_r)\sin {\omega }_r(t-t_3)\\ I_{Lm}(t)=I_{Lm}(t_3)-n{V}_o(t-t_3)/L_m\\ V_{Cr}(t)=n{V}_o+(V_{Cr}(t_3)-n{V}_o)\cos {\omega }_r(t-t_3)+I_{Lr}(t_3)Z_r\sin {\omega }_r(t-t_3)\end{array}$$

(12)

After t₄, the circuit enters the next half working state, and the working principle is similar to the first half cycle.

2.3. LG Mode

S₁ and S₃ are turned on and off at the same time in the LG mode (β = 0°), and so are S₂ and S₄, D_s = 0. The input voltage of resonant tank V_AB is zero, and the output voltage is regulated by the variable duty cycle D. The operation principles of this circuit are somewhat similar to that of a forward converter.

A switching cycle can be divided into six operational stages, and the operating principles can be analyzed according to key operational waveforms in LG mode that are shown in Figure 5 and Figure 6. They illustrate the corresponding equivalent circuits at each stage in a switching cycle.

Stage 1 [t₀, t₁]: S₁, S₃ have been conducted before this stage. During this deadtime interval, the junction capacitors of S₁ and S₃ begin to charge and the junction capacitors of S₂ and S₄ begin to discharge. The voltage across the L_s1 and L_m1 are V_L2, V_i–V_Cc–V_L2, respectively. The magnetic reset circuit (composed of diode D₁, winding N_p11, N_p21) is in an on state and stores the energy back into the power supply (charging the input capacitor C₁), which also prevents the winding N_p1, N_p2 from generating too high reverse peak voltage and breaking down the switches. The voltage sum of winding N_S1 and N_S2 is negative, D₃ conducts, and D₂ is in off-state. The voltage across L_f is –V_o.

Stage 2 [t₁, t₂]: At t₁, S₂, S₄ turn on. During this stage, diodes D₂, D₃ still conduct, the voltage of winding N_S1, N_S2 are clamped to zero, and the current flow through them is increasing. At the same time, the voltage across the L_f, L_m1, and L_s1 are –V_o, 0, and V_i, respectively. The current flow through D₂ and L_f is I_D2, I_Lf, respectively.

Stage 3 [t₂, t₃]: At the beginning of this stage, I_D2 equals to I_Lf; that is, diode D₃ is turned off. The power transferred to the load side is provided by the coupled-inductor L₁ and L₂. The voltage across the L_f, L_s1 are 2n_IC(V_i–V_H2)–V_o and V_H2, respectively.

Stage 4 [t₃, t₄]: This time is deadtime interval, the junction capacitors of S₁ and S₃ begin to discharge and the junction capacitors of S₂ and S₄ begin to charge.

Stage 5 [t₄, t₅]: At the beginning of this stage, S₁, S₃ turn on. During this stage, diode D₃ still conducts, the voltage of winding N_S1, N_S2 are clamped to 0, and the current flow through them is decreasing. At the same time, the voltage across the L_f, L_m1, and L_s1 are –V_o, 0, and V_i–V_Cc, respectively.

Stage 6 [t₅, t₆]: At the moment of t₂, the current flow through the D₂ equals zero; that is, diode D₂ is turned off. The voltage across the L_f, L_m1, and L_s1 are –V_o, V_i–V_Cc–V_L2, and V_L2, respectively. The diode D₁ conducts, and the magnetic reset circuit works again.

3. Steady Analysis of the Proposed CI-ILLC

3.1. Voltage Gain

According to the above analysis, the resonant circuit and forward circuit are connected in parallel at the load end. The voltage gain of the three modes is independent.

3.1.1. HG Mode

The proposed converter in HG mode can be seen as the combination of the boost converter and the full-bridge LLC converter, and the voltage gain of them do not affect each other. Thus, this paper analyzes the voltage gain characteristics of the CI-ILLC by deducing the boost circuit and the LLC converter characteristics separately.

The volt-second balance principle is applied to L₁ and L₂ to acquire the gain of the boost circuit. The voltage across C_C can be calculated as:

$$V_{Cc}=V_i/D$$

(13)

Define the voltage gain of the LLC resonant circuit as M_LLC = nV_o/V_Cc, and then the gain of the CI-ILLC M_DC can be calculated by (14).

$$M_{DC}=\frac{V_o}{V_i}=M_{LLC}{M}_{BOOST}=\frac{M_{LLC}}{nD}$$

(14)

The steady-state equivalent circuit of the proposed converter is presented in Figure 7. The following assumptions are made to simplify the analysis of circuit operation:

(1)

All the devices, including switches and capacitors, are ideal components.

(2)

The ripple in the DC voltage across the output capacitors is neglected.

Figure 7. Steady-state equivalent circuit of the CI-ILLC.

Figure 7. Steady-state equivalent circuit of the CI-ILLC.

At first, we obtain the following parameter definitions:

Equivalent impedance:

$$R_{eq}=n^2{R}_{o.ac}=\frac{8n^2}{{\pi }^2}{R}_o$$

(15)

Quality factor:

$$Q=\frac{1}{R_{eq}}\sqrt{\frac{L_r}{C_r}}$$

(16)

Normalized switching frequency:

$$f_n=f_s/f_{sn}$$

(17)

Normalized power:

$$P_n=P_O/P_O^{*}$$

(18)

According to the steady-state equivalent circuit in Figure 7 with D = 0.5:

$$Z_{in}(j\omega )=jh\omega L_r-\frac{j}{h\omega C_r}+jh\omega L_m//R_{eq}$$

(19)

The hth harmonic transfer functions of the AC resonant tank can be given by (20) from the definitions above.

$$H_h(j\omega )=\frac{jh\omega L_m//R_{eq}}{(jh\omega L_m//R_{eq})+jh\omega L_r-\frac{j}{h\omega C_r}}$$

(20)

The gain of the LLC resonant circuit M_LLC can be expressed as (21).

$$M_{LLC}=\frac{n{V}_o}{V_{Cc}}=\Vert H_1(j2\pi f_s)\Vert =\frac{1}{\sqrt{(1+\frac{1}{m}-\frac{1}{m{f}_n^2}{)}^2+Q^2\cdot (f_n-\frac{1}{f_n}{)}^2}}$$

(21)

As analyzed previously, the duty cycle variation from 0.5 would decrease the voltage gain, substituting parameters into (7)–(9), (13), and (14). The curves of M_DC versus duty cycle D for different quality factor Q can be calculated, as presented in Figure 8.

For the convenience of parameter design, the duty cycle is limited to the range of 0.3–0.7.

3.1.2. MG Mode

In MG mode, the duty cycle D is fixed at 0.7, the control variable is D_s. Similarly, the boost circuit and the LLC circuit can be analyzed separately in MG mode.

The volt-second balance principle is applied, then the voltage across C_C can be calculated as:

$$V_{Cc}=V_i\cdot \frac{1-D_s}{D}$$

(22)

The existence of D_s also decreases the duty cycle of the input voltage of resonant tank V_AB from 1–D to 1–D–D_s, which further reduces the voltage gain. According to the operation principle of MG mode and the solution to the Equations (10)–(14), the curves of M_DC versus D_s with D = 0.7 can be calculated, as presented in Figure 9.

3.1.3. LG Mode

Define the period of Stage 3 and Stage 6 as X/f_s and Y/f_s.

According to the analysis above, the voltage across the L_m1, L_m2 is negative when S₂, S₄ are turned off, and the key waveforms are different from the conventional forward converter. By applying the volt-second balance principle to L_f, we can obtain (23).

$$(2n_{IC}(V_i-V_{H2})-V_o)\cdot X-V_o\cdot (1-X)=0$$

(23)

By applying the volt-second balance principle to L_s1, we can obtain (24).

$$V_i\cdot (1-D-X)+V_{H2}\cdot X+(V_i-V_{Cc})\cdot (D-Y)+V_{L2}\cdot Y=0$$

(24)

In Stage 2, diodes D₂, D₃ still conduct, and the voltage of winding N_S1, N_S2 are clamped to 0. The slope of current flow through the winding N_p1 and N_s1 satisfies k_ILS1:k_ID2 = n_s1:n_p1. The current ripple of I_Lf is defined as ΔI_Lf. Combined with the analysis above, (23) and (24) can be deduced.

$$\frac{V_o}{R}-\frac{\Delta I_{Lf}}{2}=\frac{n_{p1}\cdot (1-D-X)V_i}{n_{s1}{f}_s{L}_{s1}}$$

(25)

$$\Delta I_{Lf}=\frac{(1-X)V_o}{f_{s}Lf}$$

(26)

In stage6, there is no energy transfer to the load side from the primary side. The voltage across L_s1 can be calculated by (27):

$$V_{LS1}=V_{L2}=(V_i-V_{cc})\cdot \frac{L_{S1}}{L_{S1}+L_{m1}}$$

(27)

From (23)–(27), we can obtain:

$$X=\frac{2(1-D)R{L}_f{V}_i-2n_{IC}{L}_{S1}{L}_f{f}_s+n_{IC}{L}_{S1}R{V}_o}{R(n_{IC}{L}_{S1}{V}_o+2L_f{V}_i)}$$

(28)

$$Y=\frac{D(L_{S1}+L_{m1})V_o}{2(1-2D)n_{IC}{L}_{m1}{V}_i}$$

(29)

$$M_{DC-LG}=\frac{V_o}{V_i}=\frac{1-D-X}{f_s{L}_{s1}{n}_{IC}(\frac{1}{R}+\frac{X-1}{2f_s{L}_f})}$$

(30)

It is obvious that the voltage gain is related to load status closely.

During a switching cycle, the increase of magnetic flux ΔΦ₊ can be calculated as:

$$\Delta {\mathsf{\Phi }}_{+}=\frac{V_i(1-D-X)+V_{H2}X}{f_s\cdot n_{p1}}$$

(31)

The maximum reduction of the magnetic flux ΔΦ_m− by magnetic reset circuit can be expressed by (32).

$$\Delta {\mathsf{\Phi }}_{m-}=\frac{V_{i}Y}{f_s\cdot n_{p11}}$$

(32)

To ensure the normal operation of the circuit, inequality (33) needs to be satisfied.

$$\Delta {\mathsf{\Phi }}_{+}\le \Delta {\mathsf{\Phi }}_{m-}$$

(33)

So,

$$D\ge \frac{n_{IC2}{V}_O-2n_{IC}{n}_{IC2}{V}_i+2n_{IC}{V}_{i}Y}{2n_{IC2}{n}_{IC}{V}_i}$$

(34)

3.2. Input Current Ripple

This section emphasizes on discussing the current ripple suppression mechanism. The input current ripple can be significantly reduced in HG and MG mode due to the fact that inductor currents I₁ and I₂ cancel each other out. This section mainly discusses the current ripple in HG mode because of the similar waveforms in the two modes. According to the principle of operation, the current ripples of I₁ and I₂ both can be expressed as follows:

$$\Delta I_1=\Delta I_2=\Delta I_{LS}=\{\begin{array}{c}\frac{(1-D)(V_i-V_H)}{f_s{L}_{S1}}\cdots \cdots (D>0.5)\\ \frac{D(V_i-V_{Cc}-V_L)}{f_s{L}_{S1}}\cdots \cdots (D\le 0.5)\end{array}$$

(35)

We can obtain (36)–(38) through the volt-second balance principle applied to L_m1 and L_s1 with D > 0.5,

$$V_H\cdot (2-2D)+V_L\cdot (2D-1)=0$$

(36)

$$(V_i-V_{Cc}-V_L)(2D-1)+(V_i-V_H)(1-D)+(V_i-V_{Cc}-V_H)(1-D)=0$$

(37)

$$\frac{V_i-V_{Cc}-V_L}{V_L}=\frac{L_{S1}}{L_{m1}}$$

(38)

For D ≤ 0.5, we can obtain:

$$V_H\cdot (1-2D)+V_L\cdot 2D=0$$

(39)

$$(V_i-V_L-V_H)(1-2D)+(V_i-V_L)D+(V_i-V_L-V_{Cc})D=0$$

(40)

$$\frac{V_i-V_H-V_L}{V_H}=\frac{L_{S1}}{L_{m1}}$$

(41)

Substituting (36)–(40) into (35), (35) can be further simplified as:

$$\Delta I_1=\Delta I_2=\Delta I_{LS}=\{\begin{array}{c}\frac{(1-D)}{f_s{L}_{S1}}(1-\frac{L_{m1}(2D-1)}{2(L_{m1}+L_{S1})D})V_i\cdots \cdots (D>0.5)\\ \frac{D}{f_s{L}_{S1}}(1-\frac{1}{D}+\frac{(1-2D)L_{m1}}{2D(2L_{m1}+L_{S1})-L_{m1}})V_i\cdots \cdots (D\le 0.5)\end{array}$$

(42)

According to the operation principle above, the waveforms of I_i, I₁, and I₂ are illustrated in Figure 10. The input current I_i will decrease in region A and increase in region B for D > 0.5. For D ≤ 0.5, the reverse applies. Therefore, the current ripple of I_i can be expressed as follow:

$$\Delta I_i=\left|I_{1a}-I_{1b}\right|+\left|I_{2a}-I_{2b}\right|=\{\begin{array}{c}\frac{(2D^2-3D-1)(2L_{m1}+L_{S1})V_i}{D{f}_s{L}_{S1}(L_{m1}+L_{S1})}\cdots \cdots (D>0.5)\\ \frac{2D(1-2D)V_i}{f_s(4D{L}_{m1}-L_{m1}+2D{L}_{S1})}\cdots \cdots (D\le 0.5)\end{array}$$

(43)

Define the current ripple ratio of ΔI_i to ΔI_LS as λ, which can be derived from (42) and (43) to verify the effect of current ripple suppression.

$$\lambda =\frac{\Delta I_i}{\Delta I_{\mathrm{LS}}}=\{\begin{array}{c}\frac{2(2D-1)(2L_{m1}+L_{S1})}{L_{m1}+2D{L}_{S1}}\cdots \cdots (D>0.5)\\ \frac{2D(1-2D)L_{S1}}{L_{m1}(4D-2D^2-1)+L_{S1}(2D-2D^2)}\cdots \cdots (D\le 0.5)\end{array}$$

(44)

Based on (42) and the analysis above, the ripple ratio λ is always less than 1. When D approaches 0.5 in HG mode, the ripple ratio λ is close to 0.

3.3. ZVS Condition

The soft-switching performance of the proposed CI-ILLC in HG mode for D ≤ 0.5 or D > 0.5 and MG mode are different. Therefore, the situation needs to be analyzed separately. The waveforms of I₁, I₂, I_Lr, and I_Lm are presented in Figure 11. There are four switching commutation instants, namely t_S1, t_S2, t_S3, and t_S4, during a switching cycle, which represent S₁, S₂, S₃, S₄ turn on, respectively. The turn-on currents of switches should be satisfied with the condition below to achieve ZVS.

$$I_{S1-on}=I_{Lr}(t_{S1})-I_1(t_{S1})<0$$

(45)

$$I_{S2-on}=I_{Lr}(t_{S2})-I_1(t_{S2})>0$$

(46)

$$I_{S3-on}=I_{Lr}(t_{S3})+I_2(t_{S3})>0$$

(47)

$$I_{S4-on}=I_{Lr}(t_{S4})+I_2(t_{S4})<0$$

(48)

It is obvious that I_Lr(t_S1) is always less than 0 and I_Lr(t_S3), I₁(t_S1), I₂(t_S3) are always greater than 0 for both HG mode and MG mode. So, the turn-on current of S₁, S₃ always satisfies the ZVS condition. Due to the symmetrical operations, (46) and (48) are the same. Therefore, the (46) is the final ZVS condition.

During the dead-time interval, the junction capacitors of switches begin to be discharged or charged by virtue of I_Lr and I₁, I₂. The smaller inductors lead to larger ZVS commutation currents, making it easier to realize the ZVS condition. On the other hand, the larger currents will cause a higher conduction loss.

Additionally, the turn-on current of the switches needs to be negative enough to charge or discharge the junction capacitor C_OSS of switches completely. The minimum dead time interval t_dead can be calculated from the literature [26].

$$t_{dead}\ge \frac{4C_{OSS}{V}_{Cc}}{I_{Lr}(t_{S2})}=16C_{OSS}{f}_s{L}_m$$

(49)

4. Control Methods of the Proposed CI-ILLC

The proposed CI-ILLC adopts fixed-frequency PWM to achieve output voltage regulation. Referring to Figure 12, three modes are divided as follows:

(1)

The boundary operation points of HG mode satisfy D = 0.7, D_s = 0.

(2)

The boundary operation points of LG mode satisfy D = 0.57.

Figure 12. Working range of three modes.

Figure 12. Working range of three modes.

From the analysis in Section 3.1, the boundary voltage gain of HG mode M_HGB with D = 0.7, Q = 0.4 can be calculated as about 0.814, and the boundary voltage gain of LG mode M_LGB is obtained by substituting D = 0.57 and load condition into (28)–(30).

The control block diagram is given in Figure 13, and it uses a single-loop voltage controller. The controller is TMS320F28062; the input voltage V_i and output voltage reference V_o^* are sent to the mode register to determine the gain mode. The output voltage V_o is sampled and compared with voltage reference V_o^*, and their difference is transferred to a proportional-integral (PI) controller. Then, the output signal V_con is sent to the duty cycle register to adjust D or D_s. The duty cycle register corresponds to the modulation mode of different gain modes. When the V_i and V_o^* change, the circuit will smoothly switch between HG, MG, and LG modes.

5. Topologies Comparison

A comparison with the current existing references and the proposed CI-ILLC is presented in

Table 1. Topological comparison among converters in references and the proposed converter.

Refs	[8]	[16]	[23]	[21,26]	The Proposed CI-ILLC
Number of active switches	4	8	8	6	4
Voltage stress	(nVo + Vi + VLk)/2	VH/n1 + VH/2n2	S1–S4,Q3–Q4: nVL/(1–Dp) Q1–Q2:2nVL/(1–Dp)	VDC	Vi/D
Structure	Boost + LCL + Flyback	Dual-transformer current-fed DAB	Interleaved coupled inductor based bidirectional converter	Interleaved-boost-cascaded LLC converter	Interleaved coupled-inductor LLC resonant converter
Soft switching	ZVS turn-on	ZVS turn-on	ZVS turn-on	Boost: hard switching; LLC: ZVS turn-on	ZVS turn-on
Modulation	PWM	PWM + PSM	PWM + PSM	PWM + PFM	PWM
Work range	Wide	Wide	Medium	Narrow	Wide

. The main superiorities of the CI-ILLC are as follows:

(3)

Low current ripple:

High current ripple is one of the main disadvantages of the voltage-fed converter, which will hinder the improvement of efficiency. The interleaved structure is adopted in the proposed CI-ILLC, which does not only reduce the current ripple dramatically as proven in Ⅲ.B but also divides the input current into two transmission paths to reduce the current stress of switches.

(4)

Wide operation range:

The proposed CI-ILLC can work with a wide operation range. The wide voltage gain range is achieved by the variable duty cycle. Besides, the proposed converter can work as a forward circuit at low power (low voltage) output conditions without the complex energy-flowing stage.

(5)

High efficiency and power density:

A wide ZVS range can be achieved without the current reflow because CI-ILLC inherits the beneficial features of the LLC converter. Moreover, CI-ILLC obtains high power density based on multiplexing of coupled-inductors and switches with a simple structure.

In summary, the proposed CI-ILLC can be seen as a promising solution with a wide input voltage, wide output voltage, and high efficiency.

6. Simulation and Experiment Results

After simulating the proposed converter in SIMULINK, an experimental prototype has been built and tested with parameters listed in Table 2. The experimental prototype pictures are presented in Figure 14. The design steps of the converter’s circuit components are given in the following:

(1)

The equivalent frequency operates around resonant frequency; the voltage gain M_DC is equal to 1/nD in HG mode according to (14). Under the consideration of the input and output voltage, n is chosen to be 1.6.

(2)

The equivalent output resistance can be obtained by (15). The rated resonant frequency is set as 80 kHz, m and Q are chosen to be 10 and 0.4, respectively. Hence, the resonant capacitor C_r is calculated accordingly from (48)

$$C_r=\frac{1}{2\pi Q{f}_r{R}_{eq}}=102.26\mathrm{nF}$$

(50)

(3)

C_r is selected to be 110 nF, and resonant inductor L_r is obtained in the following equation:

$$L_r=\frac{1}{2\pi Q{f}_r{C}_r}=36.98\mu \mathrm{H}$$

(51)

Due to the limitation of the transformer, L_r is selected to be 38 µH, and L_m is equal to about 400 µH with m = 10.

(4)

The magnetic reset circuit is composed of diode D₁, winding N_p11, N_p21. In order to facilitate magnetic reset, n_IC2 = n_p11:n_p1= n_p21:n_p2 is chosen to be 1:1 according to (31)–(34).

(5)

The voltage gain of LG mode can be obtained from (28)–(30), and the minimum value of D can be calculated from (34). In order to regulate the output voltage in LG mode zone as shown in Figure 12, n_IC = n_s1:n_p1= n_s2:n_p2 is chosen to be 0.8:1.

Figure 14. (a) Experimental platform; (b) prototype hardware.

Figure 14. (a) Experimental platform; (b) prototype hardware.

Table 2. Parameters of Experimental Prototype.

Parameters	Values	Parameters	Values
Input voltage (Vi)	120–200 V	Rated power (Po*)	75–1200 W
Output voltage (Vo)	50–200 V	Rated switching frequency (fsn)	80 kHz
Turns ratio of transformer (n)	1.6:1	Turns ratio of coupled inductor (nIC)	0.8:1
Turns ratio of coupled inductor (nIC2)	1:1	Leakage inductors of coupled inductor (Ls1, Ls2)	130 μH
Magnetic inductor of transformer (Lm)	400 μH	Magnetic inductors of coupled inductor (Lm1, Lm2)	1 mH
Resonant capacitor (Cr)	110 nF	Resonant inductor (Lr)	38 μH
Output inductor (Lf)	1 mH	Clamp capacitor (Cc)	220 μF

Table 2. Parameters of Experimental Prototype.

Parameters	Values	Parameters	Values
Input voltage (Vi)	120–200 V	Rated power (Po*)	75–1200 W
Output voltage (Vo)	50–200 V	Rated switching frequency (fsn)	80 kHz
Turns ratio of transformer (n)	1.6:1	Turns ratio of coupled inductor (nIC)	0.8:1
Turns ratio of coupled inductor (nIC2)	1:1	Leakage inductors of coupled inductor (Ls1, Ls2)	130 μH
Magnetic inductor of transformer (Lm)	400 μH	Magnetic inductors of coupled inductor (Lm1, Lm2)	1 mH
Resonant capacitor (Cr)	110 nF	Resonant inductor (Lr)	38 μH
Output inductor (Lf)	1 mH	Clamp capacitor (Cc)	220 μF

Figure 15 demonstrates the simulation waveform of V_Ls1, V_Ls2, I₁, I₂ in HG mode under rated power conditions with different input voltages. I₁ and I₂ are operated at a phase difference of 180° with the same amplitude, and so are V_Ls1 and V_Ls2. The current ripples of I₁, I₂ are about 6–8 A over a wide input voltage range of 120–200 V. The simulated and experimental waveforms of HG mode under rated power conditions with different input voltages are presented in Figure 16. The output voltage of the proposed CI-ILLC is regulated by fixed-frequency PWM control. The duty cycle of the input voltage of resonant tank V_AB in HG mode is equal to the minimum value between the D and 1–D. The duty cycle range of CI-ILLC at full-loaded is 0.37–0.62 over the input voltage range of 120–200 V. Though the current ripple of I₁ and I₂ is relatively large, the current ripple of I_i is reduced dramatically, especially duty cycle close to 0.5, which verifies the current ripple suppression mechanism of the proposed CI-ILLC.

The simulated and experimental waveforms of MG mode under different operation points are presented in Figure 17. The resonant stage of the MG mode corresponds to the HG mode. With the increases of D_s, the duty cycle and magnitude of the input voltage of resonant tank V_AB decreases, which is equal to 1–D–D_s and (1–D_s)V_i/D, respectively. The experimental results manifest that the proposed converter possesses excellent voltage regulation capability by adjusting D_s in the range of 0–0.15 at MG mode.

The simulated and experimental waveforms of LG mode under different operation points are illustrated in Figure 18. The voltage across couple-inductor L₁ increases as the input voltage increases. There are significant differences between the waveforms of the experiment and simulation due to the existence of interlayer capacitors in the coupled inductor. The interaction of interlayer capacitors and leakage inductors causes the voltage oscillation of magnetic inductor L_m1 and L_m2. Then, this oscillation is also reflected in I_Lf, V_Lf, I₁, I₂. However, this oscillation affects the voltage gain slightly, and the variation trend and the average value of them are the same in experiment and simulation, which is verified in Figure 18 and consistent with the analysis in Section 2.

As analyzed above, the ZVS condition of S₃ and S₄ are the same as that of the S₁ and S₂ due to the symmetry of topology and modulation. The experimental results of S₁ and S₂ with different input voltage under full load are provided in Figure 19, meanwhile, their enlarged view is also provided to exhibit the time delay. It is obvious that the drain-source voltages of S₁ and S₂ decrease to zero before the driving signal V_gs1 and V_gs2 start rising, which means that the ZVS condition of S₁ and S₂ is achieved. As can be seen, the delay between the V_ds1 decreases to zero, and V_gs1 start rising is always greater than 120 ns, which means that S₁ can realize ZVS easily over a wide range and agree with the theoretical analysis above. Therefore, the snubber circuit for active switches is not necessary for the proposed CI-ILLC. However, the delay between V_ds2 and V_gs2 is decreasing from 160 ns to 60 ns with the input voltage and load increasing. Moreover, the voltage across switches is also presented in Figure 19, and the voltage stress always equals the V_cc = V_i/D in HG mode, regardless of output load.

The experimental results of S₁ and S₂ in MG mode under different operation points are illustrated in Figure 20. As can be seen, the delay between the V_ds1 decreases to zero and the V_gs1 start rising is always greater than 800 ns due to the existence of D_s, which provides enough time to discharge the junction capacitor. However, the delay between V_ds2 and V_gs2 is less than 60 ns with the input voltage and load increasing, and the ZVS condition becomes harder.

Figure 21 shows the measured efficiencies of the proposed CI-ILLC with the different input voltage in both HG, MG, and LG modes It can be found that the proposed converter has high efficiency more than 92% over the whole operation range. At rated load, the peak efficiency can reach 96.6% in HG mode.

7. Conclusions

To achieve ZVS for a wide variation in input voltage and load, while maintaining high efficiency, has been a challenge, especially for low voltage higher current input applications. An interleaved LLC resonant converter based on a coupled inductor is proposed in this paper, which features a wide operation range, low current ripple, and wide ZVS range. The proposed converter can work in three modes by multiplexing inductors and switches with different modulation methods, which expand the operation range without adding other devices. Then, the interleaved structure is applied to reduce the current ripple and current stress of switches. Moreover, the ZVS is realized due to the characteristic of LLC resonance under the proper design. Finally, the theoretical analysis has been verified through simulation. The experimental results of the prototype further confirmed the validity of CI-ILLC and the accuracy of the analysis. The peak efficiency is more than 92% over the whole operation range. It is expected that the converter can be used at a higher power level as it has high efficiency for a wider range.