A Reconfigurable Fault-Tolerant PV Inverter via Integrating HERIC and H5 Topologies

Abstract

Solar energy is prevalent in many applications, therefore, the reliability of solar energy systems has become an important topic for research communities and industry. High reliability and fault-tolerant capability are particularly vital for the solar energy systems that are mission-critical and/or inaccessible to affordable maintenance. In order to enhance the reliability of a grid-tied PV system, a fault-tolerant Photovoltaic (PV) inverter, termed Integrated Fault-Tolerant PV Inverter (IFTPVI), is proposed in this paper. The IFTPVI is based on the Highly Efficient and Reliable Inverter Concept (HERIC) and H5 inverters that are both popular and commercialized transformerless inverters in grid-tied PV applications. The IFTPVI can tolerate both open-circuit (OC) and short-circuit (SC) faults while maintaining the same voltage and current levels. The system description, reliability analysis, simulation in Matlab/Simulink 2018, and experimental results are provided to verify the feasibility and viability of the proposed inverter topology.

1. Introduction

Renewable energy systems such as solar and wind energy systems have been increasing rapidly in both industry and residential applications worldwide. Among the renewable energy systems, PV based energy generation systems stand out for being clean and quiet without rotating parts and having a reliable operation. The International Energy Agency-Photovoltaic Power Systems Program (IEA-PVPS) 2021 report shows that global PV capacity reached a milestone of 200 GW in 2015. Approximately, 140 GW of PV systems have been installed in 2020, and the total worldwide PV capacity by the end of 2020 reached well above 750 GW [1]. The records suggest that solar energy exploitation has been increasing remarkably in recent years.

PV systems require inverters to interface the PV panels to the loads and/or the grid. The PV inverters are categorized into isolated and non-isolated types. Isolated inverters use transformers in dc and/or ac sides to provide galvanic isolation, so they block the leakage current in the panel, avoid voltage shock, and guarantee the safety. However, non-isolated transformerless inverters are at the center of attention in residential and medium power applications as they offer higher power densities and efficiency as well as lower weight and cost [2,3,4,5,6,7]. The Voltage Source Inverters (VSIs) are most attractive compared to their Current-Source counterparts due to better power densities, efficiency, and lower cost [8]. Numerous single-phase transformerless inverters for PV applications have been introduced in the literature, and efforts have been made to catalog and review these topologies [8,9,10,11,12].

The improvements in size, weight, and cost that transformerless PV inverters provide come at the cost of losing isolation and suffering from higher common-mode currents in the system. A group of transformerless PV inverters, categorized as H-bridge-based in [8], imitate isolated inverters to some degrees and provide partial isolation through decoupling the dc side from the ac side by the use of switches. The HERIC and H5 inverters are two examples of this family and have been successfully commercialized [13,14]. The HERIC and H5, respectively, use two switches on the ac side and one switch on the dc side to decouple the dc side from the ac side during a zero-voltage state. This decoupling prevents the current flow to the dc side during the current freewheeling period and effectively reduces the common-mode current, electromagnetic interference (EMI), total harmonic distortion (THD), and the output filter size.

High reliability and fault-tolerant capability are important for mission-critical PV systems such as those on a space station and for the applications that have no access to affordable maintenance. For example, the need for highly reliable power converters in remote areas is pressing, since a fault in these systems may result in highly expensive or catastrophic system malfunctions. Therefore, the reliability in such applications is given a much higher priority than the overall cost of the system [15] as the maintenance might prove to be difficult to carry out, if not impossible. Even though faults might occur in both PV arrays and inverters, it is reported in the literature that inverters are the most prone-to-failure parts of PV systems [16,17]. For instance, the Mean Time Between Repairs (MTBR) is guaranteed to be more than 20 years for modern PV arrays, while this parameter can drop as low as 2 years for an inverter [18,19]. Consequently, a number of fault-tolerant PV inverter topologies have been developed in the literature as efforts to mitigate the reliability concerns associated with PV systems [18,20,21,22,23,24,25]. A spare-inverter approach was proposed for multi-inverter systems so that the additional inverter can replace the faulty inverter until it is repaired [18]. This method, while applicable to multi-inverter PV systems, may not be very efficient when the PV system only consists of a single inverter as it significantly increases the costs of power converter implementation. The issue of using spare inverter versus using a fault-tolerant inverter to enhance reliability needs further investigation that is out of the scope of the present work. The method presented in [20] adds four TRIACs to an H-bridge in order to provide it with fault tolerance and reconfiguration capabilities. The use of TRIACs adds to the complexity of driver circuits, and their low immunity to dv/dt calls for additional dv/dt filter, which increases the cost and size of the circuit. There are also fault-tolerant methods for multilevel PV inverters that are not applicable to two or three-level single-phase PV inverter systems [21,22,23,24,25]. Hence, there is still a great need for studying fault-tolerant PV inverters to further enhance reliability and alleviate common-mode currents. The common-mode current in grid-tied PV systems has a direct relation with the capacitance of the stray capacitor of the PV panel and switching frequency [26,27].

To address this challenge, a new single-phase fault-tolerant PV inverter is proposed in this paper. The proposed inverter, called Integrated Fault-tolerant PV Inverter (IFTPVI), uses a redundant switch-leg, a fault-managing unit (FMU), and three electromechanical relays. In normal operation, the IFTPVI is in the form of a HERIC inverter. Under a faulty condition, the redundant switch-leg replaces the faulty switch-leg. If the bidirectional switch fails, the IFTPVI is reconfigured, and it takes the shape of an H5. All the mentioned actions are handled by electromechanical relays.

The rest of this paper is organized as follows: the configuration of the proposed inverter is defined in Section 2 where the healthy and faulty conditions are discussed in detail. The fault diagnosis and elimination algorithm are given in Section 3, which also illustrates different parts of the proposed fault tolerant structure. The reliability evaluation and Mean Time to Failure (MTTF) analysis are provided in Section 4. In this section, the reliabilities and the MTTFs of the HERIC, H5 and the proposed inverter are thoroughly investigated. The numerical results and comparisons for reliability and MTTF analysis are given in Section 5, and the simulation and experimental results are provided in Section 6. Finally, the overall work is concluded in Section 7.

2. Topology and Operation Principle of the IFTPVI

2.1. The HERIC and H5 Inverter Topologies

Since the IFTPVI is implemented through the integration of the HERIC and H5 inverters, the topologies of these two inverters are displayed in Figure 1a,b for quick reference. As shown in Figure 1a, the HERIC decouples the ac and dc sides during the zero-voltage state by opening the four switches in the H-bridge and closing S_b. The H5 achieves the same goal by opening S₅ and closing the upper or lower switches in H-bridge during a zero-voltage state.

2.2. The Proposed Fault-Tolerant PV Inverter Topology

The proposed fault-tolerant PV inverter is shown in Figure 2. In this topology, one reserve switch-leg (Leg_R), which is synthesized using two semiconductor switches (S_r1 and S_r2), and three electromechanical relays (R₁, R₂, and R₃) are used to provide the HERIC inverter with the fault-tolerance and reconfiguration abilities in case of Short-Circuit (SC) and Open-Circuit (OC) faults. The FMU is used to diagnose the fault and drive the relays to reconfigure the inverter. As shown in Figure 2, each relay has two metal-ware contacts that are used to remove the faulty part and insert the reserve part into the circuit. Different operation modes are described in the forthcoming subsections. For more clarity of discussion in these subsections, some of the labels shown in Figure 2 are not displayed in Figure 3, Figure 4 and Figure 5.

2.3. Healthy Operation Mode

Assuming the initial condition to be a healthy mode, the converter operates as a HERIC inverter, which is shown in Figure 3. In the healthy mode, the reserve switch-leg is inactive. While operating as the HERIC inverter, a bidirectional switch (S_b) is used to create the zero-voltage state at the output to reduce dv/dt, EMI, power losses, and filter size. During the zero-voltage state, the dc and ac sides are decoupled through S₁, S₂, S₃, and S₄ to reduce the common-mode current.

2.4. Faulty Modes

The faulty mode begins once a short-circuit or open-circuit fault is detected through the FMU. If the fault occurs in one of the switch-legs (Leg₁ or Leg₂ in Figure 2), depending on the location of the faulty switch, the corresponding relay (R₂ for Leg₁ and R₃ for Leg₂) contacts disconnect the faulty leg and replace it with the reserve leg so that the inverter resumes operation as a HERIC inverter with the same input and output characteristics. Figure 4a shows the reconfiguration of the proposed inverter before and after a fault in Leg₁. Similarly, Figure 4b shows the configuration after a fault in Leg₂.

In the case that the fault occurs in the bidirectional switch (S_b), relay R₁ will be activated so that S_b is disconnected from the circuit and S_r1 joins the circuit. In other words, the inverter is reassembled as an H5 inverter in this condition, as displayed in Figure 5. While operating in the H5 mode, S_r1 decouples the dc side from the ac side under the zero- voltage state to mitigate the common-mode current. While the efficiency might be slightly lower, the inverter would still be able to maintain the same operating characteristics and the same output voltage and current as of the pre-fault condition.

It is noteworthy that the maximum switch voltage stress of the IFTPVI in any operation mode is equal to the input voltage (PV voltage), which is the same as the maximum voltage stress in the conventional HERIC and H5 inverters.

3. Fault-Tolerant Structure of IFTPVI

The main parts of the fault-tolerant structure in the proposed topology are the FMU and electromechanical relays. The operation principle of the FMU and the relays are defined in this section.

3.1. Fault Managing Unit (FMU) and Fault Diagnosing Strategy

In order to implement the FMU and diagnose the fault, three current sensors are needed to sense the instantaneous currents of Leg₁, Leg₂ and the bidirectional switch (S_b), as indicated by Ia, Ib, and Ic, accordingly, in Figure 6. The fault is diagnosed through the procedure displayed in the flow-chart of Figure 7. According to this flow-chart, the FMU processes the measured currents along with the switching patterns for every switching period. The currents that each switching pattern should cause to flow in each leg during the normal operation are known. These values can only be equal to the output current or zero under normal conditions. The possible switching patterns and currents under healthy and faulty modes are summarized in

Table 1. Operation modes of the proposed fault tolerant inverter.

Operation Modes		Switching Pattern of the Switches	Current in Legs			Io
		S1, S2, S3, S4, Sb	Ia	Ib	Ic
Healthy Mode		10010	I	0	0	−I
		00001	0	0	I	−I
		01100	0	I	0	I
Faulty modes (faulty switch identification)	OC in Leg1	10010	0	0	0	I
	OC in Leg2	10010	I	−I	0	I
	SC in Leg1	10010	>I	0	0	I
	SC in Leg2	10010	I	>I	0	I
	SC in Sb	10010	>I	0	>I	I
	OC in Sb	00001	0	0	0	0
	OC in Leg1	01100	−I	I	0	I
	OC in Leg2	01100	0	0	0	I
	SC in Leg1	01100	>I	0	0	I
	SC in Leg2	01100	I	>I	0	I
	SC in Sb	01100	0	>I	>I	I

(in this table, “1” and “0” indicate the on and off states of the switches, respectively). In the case that one of the currents does not match the switching pattern, the FMU diagnoses the fault and locates the faulty section. As the faulty section is located, the FMU commands the associated relay R₁, R₂, or R₃ for faults in the bidirectional switch, Leg₁, or Leg₂, respectively. The relay corresponding to the faulty switch decouples the faulty section and adds the respective reserve element (or elements) to the circuit. Once the reconfiguration is successfully accomplished, new switching patterns are provided to the reconfigured configuration.

3.2. Electromechanical Relay

Each of the electromechanical relays in the IFTPVI consists of two normal-open (NO) and two normal-close (NC) metal-ware contacts. Figure 8 shows the structure of the electromechanical relay used in IFTPVI. Since the electromechanical relays in the proposed inverter experience only one switching action, the slow characteristic of these relays is not important. However, the robustness of the structure is of great importance because they are to enhance reliability. Referring to Figure 2, it is seen that the normal-open conductors of the relays isolate the reserve switches from the circuit and avoid having voltage stresses across those switches during the healthy mode. Minimizing the voltage stress on reserve switches is very important since the voltage stress across the reserve switches could damage them before they enter the circuit operation.

4. Reliability and MTTF Analysis

One of the most prominent techniques among many analytical techniques [28] for reliability analysis and evaluation is the Markov chain approach. The Markov method is applicable to the memoryless stationary systems.

As stated in [29,30,31], the lifetime of a power electronic element can be divided into three periods. The first period, often referred to as the debugging phase, is the period that device is most likely to fail in and consequently has high failure rate due to manufacturing errors, improper design or errors occurring due to the operator. The hazard rate in this phase decreases with time. The debugging phase may be short or non-existent for power electronic converters. The second period is referred to as normal operating phase. The hazard rate in this period is almost constant and failures occur by chance. This phase is the only phase in which the exponential distribution is valid. The third phase is termed as fatigue phase in which the hazard rate accelerates with time.

In order to figure out the reliability of an inverter, a Markov chain model of the inverter can be developed. Then, the transition rates of the model should be extracted using the failure rates of the utilized components. Additionally, the differential equations corresponding to the probability of the system being in operational states in the Markov chain model are needed. Finally, the Mean Time to Failure (MTTF) and the reliability of the inverter, which is the sum of the time-dependent probabilities of the operating states in the Markov chain, are calculated. In the following subsections, the reliability analysis of the conventional HERIC and H5 inverter along with the proposed fault-tolerant PV inverter topology is presented.

4.1. Reliability of the Conventional HERIC and H5 Inverter

The conventional HERIC and H5 inverters are both two-state systems [30]. The Markov chain model for these two inverters is shown in Figure 9, where State I is the Up state (operating state) and State II is the Down state (failed or absorbing state).

For the sake of obtaining a more realistic model, the PV panels parallel capacitors C are also taken into consideration as shown in Figure 2. The Markov chain model transition rates of the HERIC (α) and H5 (β) inverters are, respectively, given as

$$\alpha =6{\Lambda }_{s{w}_{HERIC}}+6{\Lambda }_{D_{HERIC}}+{\Lambda }_C$$

(1)

$$\beta =5{\Lambda }_{s{w}_{H5}}+5{\Lambda }_{D_{H5}}+{\Lambda }_C$$

(2)

where, ${\Lambda }_{SW}$, ${\Lambda }_D$, and ${\Lambda }_C$ represent the failure rates of switch, diode, and dc link capacitor, respectively. For the sake of brevity, the devices are all assumed to be in their normal operating phase. Therefore, their reliabilities can be described with exponential distributions [29].

In the initial state, both HERIC and H5 converters are assumed to begin operation in healthy condition. Thus, the initial condition matrix is

$$P\left(0\right)=\left[1 0\right]$$

(3)

The Up states time-dependent probabilities for HERIC and H5 are, respectively, given as Equations (4) and (5).

$$\frac{d}{dt} \left[P_{1_{HERIC}}\left(t\right) P_{2_{HERIC}}\left(t\right)\right]=\left[P_{1_{HERIC}}\left(t\right) P_{2_{HERIC}}\left(t\right)\right]\left[\begin{array}{cc}-\alpha & \alpha \\ 0& 0\end{array}\right]$$

(4)

$$\frac{d}{dt} \left[P_{1_{H5}}\left(t\right) P_{2_{H5}}\left(t\right)\right]=\left[P_{1_{H5}}\left(t\right) P_{2_{H5}}\left(t\right)\right]\left[\begin{array}{cc}-\beta & \beta \\ 0& 0\end{array}\right]$$

(5)

Referring to Equations (1)–(5), the reliabilities of the conventional HERIC and H5 are obtained as

$$P_{1_{HERIC}}\left(t\right)=R_{HERIC}\left(t\right)=e^{-\alpha t}$$

(6)

$$P_{1_{H5}}\left(t\right)=R_{H5}\left(t\right)=e^{-\beta t}$$

(7)

4.2. Reliability of the Proposed Fault-Tolerant Topology

The proposed fault-tolerant PV inverter can keep operating regardless of any kind of fault (OC or SC) in any of its semiconductor switches. The Markov chain model for IFTPVI is displayed in Figure 10. State I is the healthy state, all elements and switches of the converters are healthy and operational. In State II, one of the H-bridge switches in the initial HERIC configuration has failed and its corresponding leg was replaced with the reserve leg. Furthermore, State III represents the situation in which one of the two switches in the bidirectional switch has failed and therefore, was replaced by S_r1. Finally, State IV is the absorbing state. Once the converter enters the absorbing state, it can no longer operate with the original characteristics or cannot operate at all. States I–III are referred to as Up states as the converter maintains normal operation in those states. Oppositely, State IV is known as the Down state since the converter in this state is considered failed.

The transition rates for the Markov chain model given in Figure 10 are

$${\lambda }_{12}=4\left({\Lambda }_{s{w}_{HERIC}}+{\Lambda }_{D_{HERIC}}\right)P_r$$

(8)

$${\lambda }_{13}=2\left({\Lambda }_{s{w}_{HERIC}}+{\Lambda }_{D_{HERIC}}\right)P_r$$

(9)

$${\lambda }_{14}=6\left({\Lambda }_{s{w}_{HERIC}}+{\Lambda }_{D_{HERIC}}\right)\left(1-P_r\right)+{\Lambda }_C$$

(10)

$${\lambda }_{24}=6\left({{\Lambda }^{\prime }}_{s{w}_{HERIC}}+{{\Lambda }^{\prime }}_{D_{HERIC}}\right)+{\Lambda }_C$$

(11)

$${\lambda }_{34}=5\left({{\Lambda }^{\prime }}_{s{w}_{H5}}+{{\Lambda }^{\prime }}_{D_{H5}}\right)+{\Lambda }_C$$

(12)

where ${{\Lambda }^{\prime }}_{s{w}_{HERIC/H5}}$ and ${{\Lambda }^{\prime }}_{D_{HERIC/H5}}$ are, respectively, failure rates of switch and diode for IFTPVI after a fault has occurred, the converter is reconfigured and is operating as HERIC or H5. ${\lambda }_{ij}$ is the transition rate from state i to state j in the Markov chain model of IFTPVI shown in Figure 10. P_r is the probability of successful operation of the relay to remove the faulty part and to replace it by the reserve one. The failure rate of relays is a function of the number of on/off cycles. Thus, if a relay is switched only once in its lifespan, which is the case in IFTPVI, its hazard rate can be assumed to be zero [32]. Therefore, it is assumed that once the relay is turned on, it will keep up the proper operation. In this reliability analysis, the value of P_r is assumed 0.98 instead of 1 in order to have a more realistic analysis [28,31]. The maximum contact resistance for Omron MM series electromechanical power relays is 25 $\mathrm{m}\Omega$. These small relay contact resistances have a minuscule effect on the current and losses and, therefore, are ignored in the failure rate analysis. It is also worth noting that internal resistances of the reserve switches are assumed to be 5% higher than the main switches. This assumption is made in order to have a more realistic analysis by considering the component variations to a degree and to make sure that state I and state II of the Markov chain model in Figure 10, which respectively correspond to IFTPVI operating as HERIC pre-fault and post-fault, would not be rendered identical due to the above simplifications.

Each state change corresponds to the occurrence of a fault in the PV inverter. The IFTPVI can tolerate an SC or OC fault in any of the semiconductor switches as long as the corresponding relay functions properly after the fault is detected through the FMU. Consequently, if a fault occurs while IFTPVI is in State I and the relay responsible for bypassing and replacing the faulty switch fails to switch correctly, the inverter will cease to operate and moves to the State IV, the absorbing state in the IFTPVI Markov chain model. After the first fault has already occurred and the system is reconfigured once, the other two scenarios to enter the absorbing state are the occurrence of a second fault in any of the switches and the dc link capacitor failure. Therefore, the capacitor failure rate should be taken into account in the transition rates. The system is considered initially operational; and thus, all the assumptions in Section 4. A are valid here as well. The initial condition matrix is given as

$$P\left(0\right)=\left[\begin{array}{cccc}1& 0& 0& 0\end{array}\right]$$

(13)

The time-dependent probabilities for each of the states are determined using Equations (8)–(14).

$$\begin{array}{c}\frac{d}{dt}\left[P_1\left(t\right) P_2\left(t\right) \dots P_4\left(t\right)\right]=\left[P_1\left(t\right) P_2\left(t\right) \dots P_4\left(t\right)\right]\\ \times \left[\begin{array}{cccc}-\left( {\lambda }_{12}+{\lambda }_{13}+{\lambda }_{14}\right)& {\lambda }_{12}& {\lambda }_{13}& {\lambda }_{14}\\ 0& -{\lambda }_{24}& 0& {\lambda }_{24}\\ 0& 0& -{\lambda }_{34}& {\lambda }_{34}\\ 0& 0& 0& 0\end{array}\right]\end{array}$$

(14)

As discussed, the (Up) state probabilities in the Markov model in Figure 10 are $P_1, P_2, \mathrm{and} P_3$. Therefore, the reliability of the proposed fault-tolerant PV inverter is obtained as

$$R\left(t\right)=P_1\left(t\right)+P_2\left(t\right)+P_3\left(t\right)={\displaystyle \sum }_{j=1}^3{P}_j\left(t\right)$$

(15)

Solving the differential equations in Equation (14) yields the time-dependent probabilities of the operating (Up) states as

$$P_1\left(t\right)=e^{-\left( {\lambda }_{12}+{\lambda }_{13}+{\lambda }_{14}\right)t}$$

(16)

$$P_2\left(t\right)=\frac{ {\lambda }_{12}}{ {\lambda }_{12}+{\lambda }_{13}+{\lambda }_{14}-{\lambda }_{24}}\left[-e^{-\left( {\lambda }_{12}+{\lambda }_{13}+{\lambda }_{14}\right)t}+e^{-{\lambda }_{24}t}\right]$$

(17)

$$P_3\left(t\right)=\frac{ {\lambda }_{13}}{ {\lambda }_{12}+{\lambda }_{13}+{\lambda }_{14}-{\lambda }_{34}}\left[-e^{-\left( {\lambda }_{12}+{\lambda }_{13}+{\lambda }_{14}\right)t}+e^{-{\lambda }_{34}t}\right]$$

(18)

4.3. MTTF Analysis of the IFTPVI, HERIC and H5 Inverters

Using the coefficient matrices in Equations (4), (5), and (14), the stochastic transitional probability matrix P can be defined [29] for the HERIC, H5, and IFTPVI. In matrix P, each element $P_{ij}$ corresponds to the probability of transition to state j after being in state i for a non-zero time interval.

$$P_{HERIC}=\left[\begin{array}{cc}1-\alpha & \alpha \\ 0& 1\end{array}\right]$$

(19)

$$P_{H5}=\left[\begin{array}{cc}1-\beta & \beta \\ 0& 1\end{array}\right]$$

(20)

$$P_{IFTPVI}=\left[\begin{array}{cccc}1-\left( {\lambda }_{12}+{\lambda }_{13}+{\lambda }_{14}\right)& {\lambda }_{12}& {\lambda }_{13}& {\lambda }_{14}\\ 0& 1-{\lambda }_{24}& 0& {\lambda }_{24}\\ 0& 0& 1-{\lambda }_{34}& {\lambda }_{34}\\ 0& 0& 0& 1\end{array}\right]$$

(21)

The truncated stochastic transitional probability matrix Q can be obtained by omitting the row and column associated with the absorbing state in the stochastic transitional probability matrices given in Equations (19)–(21). The absorbing state for HERIC and H5 is State II, and the absorbing state for IFTPVI is State IV. Therefore, their corresponding truncated stochastic transitional probability matrices are

$$Q_{HERIC}=\left[1-\alpha \right]$$

(22)

$$Q_{H5}=\left[1-\beta \right]$$

(23)

$$Q_{IFTPVI}=\left[\begin{array}{ccc}1-\left( {\lambda }_{12}+{\lambda }_{13}+{\lambda }_{14}\right)& {\lambda }_{12}& {\lambda }_{13}\\ 0& 1-{\lambda }_{24}& 0\\ 0& 0& 1-{\lambda }_{34}\end{array}\right]$$

(24)

The MTTF can be defined as the average time passed before the converter enters the absorbing state, and can be calculated either by the integration of reliability over the time from the starting point of converter operation to infinity or by using the stochastic transitional probability matrix method. The latter obtains the MTTF through inversion of the matrix produced by subtraction of the truncated matrix Q from the corresponding identity matrix [29]. The MTTF matrix (M) of the HERIC and H5 inverters are, accordingly, calculated as

$$MTT{F}_{HERIC}=M_{HERIC}={{\displaystyle \int }}_0^{\infty }{R}_{HERIC}\left(t\right)dt={\left[I-Q_{HERIC}\right]}^{-1}=\frac{1}{\alpha }$$

(25)

$$MTT{F}_{H5}=M_{H5}={{\displaystyle \int }}_0^{\infty }{R}_{H5}\left(t\right)dt={\left[I-Q_{H5}\right]}^{-1}=\frac{1}{\beta }$$

(26)

For of the sake of brevity, the stochastic transitional probability matrix method is used calculating MTTF matrix (M) for the IFTPVI.

$$M_{IFTPVI}={\left[I-Q_{IFTPVI}\right]}^{-1}=\left[\begin{array}{ccc}\frac{1}{{\lambda }_{12}+{\lambda }_{13}+{\lambda }_{14}}& \frac{{\lambda }_{12}}{{\lambda }_{24}\left({\lambda }_{12}+{\lambda }_{13}+{\lambda }_{14}\right)}& \frac{{\lambda }_{13}}{{\lambda }_{34}\left({\lambda }_{12}+{\lambda }_{13}+{\lambda }_{14}\right)}\\ 0& \frac{1}{{\lambda }_{24}}& 0\\ 0& 0& \frac{1}{{\lambda }_{34}}\end{array}\right]$$

(27)

In the matrix M, M_pq indicates the average number of hours spent in state q given that the system began operation from state p [29]. Consequently, the MTTF for the IFTPVI is obtained as

$$MTT{F}_{IFTPVI}=M_{11}+M_{12}+M_{13}$$

(28)

It is the sum of the average number of hours spent in each of the Up States (I–III) given that the converter begins operation in State I, the healthy state.

4.4. Failure Rate Analysis

Failure rate analysis is necessary to obtain the numerical results of reliability and MTTF of the converter. The method reported in [30] is used to calculate the failure rates of the power electronic circuit components. Even though the approach in [30] is criticized from a different point of view [31], it is still used to compare relative MTTF ameliorations [32]. According to [30], the failure rates of the power electronic elements can be estimated using Equation (29).

$${\Lambda }_{component}={\Lambda }_b{{\displaystyle \prod }}_{j=1}^n{\pi }_j (\mathrm{failure}/{10}^6 \mathrm{h})$$

(29)

where ${\Lambda }_{component}$, ${\Lambda }_b$, and ${\pi }_j$ are, respectively, the failure rate of a component, the component basic failure rate, and the special factors that affect the failure rate of the component. These factors may vary for different circuit components. The factors affecting the considered power electronic components in this work are given in

Table 2. Factors Affecting the Failure Rates.

Factor	Definition
${\pi }_s$	Electrical stress factor $\left({\pi }_S\right)=V_S^{2.43},$ voltage stress factor $\left(V_s\right)=\frac{V_{applied}}{V_{rated}}$
${\pi }_c$	Contact contraction factor–takes the values of 1 and 2 for metallurgically-bonded and non-metallurgically-bonded diodes.
${\pi }_Q$	Quality factor = 1 [33]
${\pi }_E$	Environment factor–takes different values based on the operation environment, for instance, space, ground, etc. For ground operation ${\pi }_E=1$.
${\pi }_A$	Application factor–depends on operation power.
${\pi }_V$	Capacitor electrical stress factor. ${\pi }_V=[ {\left(\frac{\raisebox{1ex}{$V_{C_A}$}\!\left/ \!\raisebox{-1ex}{$V_{C_{rated}}$}\right.}{0.5}\right)}^3+1]$ where $V_{C_A}$ and $V_{C_{rated}}$ are maximum applied voltage and the rated voltage, respectively.
${\pi }_{Cap}$	Capacitor factor–depends on the materials used in the capacitor. For exam-ple, the Dielectric for an electrolytic capacitor: ${\pi }_{cap}=0.34C^{0.18}$ where C is the nominal capacitance.
${\pi }_T$	factors in the temperature on failure rates. ${\pi }_T$ is a function of junction temperature in the case of MOSFETs and diodes.

[30].

Equations (30)–(32) provide the formula to calculate the π_T for diodes, MOSFETs, and capacitors, respectively [30].

$${\pi }_{T_D}=exp[-3091\left(\frac{1}{T_j+273}-\frac{1}{298}\right)]$$

(30)

$${\pi }_{T_M}=exp[-1925\left(\frac{1}{T_j+273}-\frac{1}{298}\right)]$$

(31)

$${\pi }_{T_C}=exp[-5.09{\left(\frac{T_a+273}{353}\right)}^5]$$

(32)

where T_a is the ambient temperature, which is assumed to be 25 °C. Moreover, $T_j$ (°C) is the junction temperature of the MOSFET or diode and it is calculated as

$$T_j=T_a+{\theta }_{ca}{P}_l+{\theta }_{jc}{P}_l$$

(33)

where ${\theta }_{ca}$, ${\theta }_{jc}$, and $P_l$ are the case to ambient thermal resistance (°C/W), junction to case thermal resistance (°C/W), and power losses (W), respectively. Other factors affecting failure rates are given in

Table 3. Effective Factors on Components Failure Rates.

Components	Effective Factors $({\mathit{\pi }}_{\mathit{j}})$
Diode	${\pi }_T.{\pi }_S.{\pi }_C.{\pi }_Q.{\pi }_E$
MOSFET	${\pi }_T. {\pi }_A.{\pi }_Q.{\pi }_E$
Capacitor	${\pi }_T.{\pi }_V.{\pi }_{Cap}.{\pi }_Q.{\pi }_E$

.

According to [34], the conduction power loss of a MOSFET and a diode can be calculated using the electrical models as shown in Figure 11.

Where V_T and V_F are MOSFET threshold voltage and diode forward voltage; and $R_{D{S}_{on}}$ and $R_{d_{on}}$ are the MOSFET and diode on-state resistances, respectively. The aforementioned parameters are to be extracted from the component datasheets. Equations (34) and (35) respectively show the average power losses of the diode and MOSFET [30,31,32,33,34,35,36,37,38,39]:

$$P_{D_l}=\frac{1}{T}[{{\displaystyle \int }}_0^T(R_{d_{on}}·i_S^2\left(t\right)+V_F·i_S\left(t\right))dt]$$

(34)

$$P_{s{w}_l}=P_C+P_S=\frac{1}{T}[{{\displaystyle \int }}_0^T(R_{D{S}_{on}}·i_S^2\left(t\right)+V_T·i_S\left(t\right))dt]+[C_{oss}{f}_s{V}_{DS}^2]$$

(35)

where $i_S$, $P_C$, $P_S$, $C_{oss}$, $f_s$ and $V_{DS}$ are the instantaneous MOSFET or diode current, average conduction losses, average switching losses, MOSFET output capacitance, switching frequency, and the applied Drain-Source voltage, respectively. The conduction losses are calculated as the average losses in MOSFET or diode caused by their on-state voltage and internal resistance. The MOSFET average switching loss is calculated by the second term in Equation (35) [30,31,32,33,34,35,36,37,38,39], and the diode switching loss is ignored due to its small value.

5. Numerical Results and Comparison

5.1. Numerical Results

In this section, the numerical values of the reliability and MTTF of the HERIC and H5 inverters are compared with those of the IFTPVI. Furthermore, a comparison study is conducted to demonstrate the enhanced reliability of the proposed fault-tolerant technique. The simulation parameters are given in

Table 4. Circuit Parameters for Simulation.

Parameter	Description	Value
$V_{o_{RMS}}$	Peak load voltage	320 (V)
$P_o$	Load power	2 (kW) and 1.1 (kVar)
P.F.	Power factor (lagging)	0.87
$R_{{DS}_{on}}$	MOSFET on-state resistance	40 $\left(\mathrm{m}\Omega \right)$
$R_{d_{on}}$	Diode on-state resistance	0.1 $\left(\mathrm{m}\Omega \right)$
$V_T$	MOSFET threshold voltage	1.2 (V)
$V_F$	Diode forward voltage	1.2 (V)
$V_{dc}$	PV voltage	350 (V)
$f_s$	Switching frequency	25 (kHz)
C	Parallel capacitor of PV panel	470 $(\mathsf{\mu }\mathrm{F}$)
$C_{oss}$	MOSFET parasitic output capacitance	720 (PF)
$V_c^{rated}$	PV panel capacitor rated voltage	450 (V)

. A power factor of 0.87 was selected since most PV inverters operate with a power factor of close to unity.

Table 5. Numerical Values Necessary for Calculation of Effective Parameters on Failure Rates.

Parameter	Description	Value
${\lambda }_b$	Basic failure rate of diode	0.003 (failure/${10}^6$ h)
	Basic failure rate of MOSFET	0.012 (failure/${10}^6$ h)
	Basic failure rate of capacitor	0.0012 (failure/${10}^6$ h)
${\pi }_c$	Contact contraction factor	1
${\pi }_Q$	Quality factor	1
${\pi }_E$	Environment factor	1
${\pi }_A$	Application factor	10
$T_a$	Ambient temperature	25 (°C)
${\theta }_{ca}$	MOSFET case to ambient temperature	40 $(\frac{°\mathrm{C}}{\mathrm{W}})$
	Diode case to ambient temperature	60 $(\frac{°\mathrm{C}}{\mathrm{W}})$
${\theta }_{jc}$	MOSFET junction to case temperature	0.65 $(\frac{°\mathrm{C}}{\mathrm{W}})$
	Diode junction to case temperature	2 $(\frac{°\mathrm{C}}{\mathrm{W}})$

provides the values of the parameters introduced in Table 2 and Table 3 and Equations (29)–(35), which are required for calculating power electronic circuit components failure rates and, in turn, obtaining the numerical values of Markov chain models transition rates, reliabilities, and MTTFs of the HERIC, H5, and IFTPVI. The values in Table 5 are extracted from [30] and the components’ datasheets. In case of using other types of semiconductor switches, diodes, or capacitors, their corresponding Table 5 parameters can be extracted from [30].

Table 6. Numerical Values Necessary for Effective Parameters on Failure Rates.

Component & Parameters	MOSFET and Parallel Diode				Capacitor
	${\mathit{P}}_{\mathit{l}} \left(\mathbf{W}\right)$ (Average Loss for One MOSFET and Its Parallel Diode)	${\mathit{\pi }}_{\mathit{T}}{}_{\mathit{M}\mathit{O}\mathit{S}\mathit{F}\mathit{E}\mathit{T}}$	${\mathit{\pi }}_{\mathit{S}}$	${\mathit{\pi }}_{\mathit{T}}{}_{\mathit{D}\mathit{i}\mathit{o}\mathit{d}\mathit{e}}$	${\mathit{\pi }}_{\mathit{C}\mathit{a}\mathit{p}}$	${\mathit{\pi }}_{\mathit{V}}$	${\mathit{\pi }}_{\mathit{T}}{}_{\mathit{C}\mathit{a}\mathit{p}\mathit{a}\mathit{c}\mathit{i}\mathit{t}\mathit{o}\mathit{r}}$
HERIC or IFTPVI operating as HERIC before fault	6.5400	17.6800	0.4203	2.3668	0.0856	4.7641	8.8672
H5	9.3400	37.0507	0.4203	1.0894	0.0856	4.7641	8.8672
IFTPVI operating as HERIC after fault	6.5700	17.8244	0.4203	0.9948	0.0856	4.7641	8.8672
IFTPVI operating as H5 after fault	9.4400	37.6867	0.4203	1.0894	0.0856	4.7641	8.8672

presents the numerical values of temperature factor ${\pi }_T$ for MOSFETs, diodes, and capacitors as well as other factors that require calculation for obtaining the power electronic circuit components failure rates. The values in this table are extracted using Table 2, Equations (30)–(32), and the simulation results obtained using Matlab Simulink^TM.

Table 7. Numerical Values for Components Failure Rates in HERIC, H5, and IFTPVI.

Component & Parameters	MOSFET				Diode				Capacitor
	${\mathbf{\Lambda }}_{\mathit{s}{\mathit{w}}_{\mathit{H}\mathit{E}\mathit{R}\mathit{I}\mathit{C}}}$	${\mathbf{\Lambda }}_{\mathit{s}{\mathit{w}}_{\mathit{H}5}}$	${{\Lambda }^{\prime }}_{\mathit{s}{\mathit{w}}_{\mathit{H}\mathit{E}\mathit{R}\mathit{I}\mathit{C}}}$	${{\Lambda }^{\prime }}_{\mathit{s}{\mathit{w}}_{\mathit{H}5}}$	${\mathbf{\Lambda }}_{{\mathit{D}}_{\mathit{H}\mathit{E}\mathit{R}\mathit{I}\mathit{C}}}$	${\mathbf{\Lambda }}_{{\mathit{D}}_{\mathit{H}5}}$	${{\Lambda }^{\prime }}_{{\mathit{D}}_{\mathit{H}\mathit{E}\mathit{R}\mathit{I}\mathit{C}}}$	${{\Lambda }^{\prime }}_{{\mathit{D}}_{\mathit{H}5}}$	${\mathbf{\Lambda }}_{\mathit{C}}$
Values	2.1216	4.4461	2.1389	4.5224	0.0030	0.0014	0.0030	0.0014	0.0043

provides the components failure rates for conventional HERIC and H5, and IFTPVI. These failure rates are calculated using the data given in Table 2, Table 3, Table 4, Table 5 and Table 6. For the purpose of simplification, the effect of heat sinks on losses are not taken into account in the reliabilities evaluations and comparisons.

The numerical values for the transition rates in the Markov chain models of the HERIC, H5, and the IFTPVI, shown in Figure 9 and Figure 10, are provided in

Table 8. Numerical Values for the Transition Rates in Markov Chain Models of HERIC, H5, and IFTPVI.

Chain	Numerical Value (Failure/${10}^6 \mathbf{h})$
$\alpha$ (HERIC)	12.7518
$\beta$ (H5)	22.2416
${\lambda }_{12}$	8.3284
${\lambda }_{13}$	4.1642
${\lambda }_{14}$	0.2593
${\lambda }_{24}$	12.8557
${\lambda }_{34}$	22.6233

. The values in the aforementioned table are obtained using Equations (1), (2) and (8)–(12), and the circuit components failure rates given in Table 7.

5.2. Comparison

In order to do a comprehensive evaluation, the IFTPVI is compared with the HERIC and H5 inverters.

Table 9. Comparison of Fault-Tolerant Techniques.

Topology	IFTPVI	HERIC	H5
Reliability	$81.5744e^{-12.7518t}$ $-80.1526e^{-12.8557t}$ $-0.4218e^{-22.6233t}$	$e^{-12.7518t}$	$e^{-22.2416t}$
MTTF	$0.1437\times {10}^6 \mathrm{h}$	$0.0784\times {10}^6 \mathrm{h}$	$0.0450\times {10}^6 \mathrm{h}$

provides a comparison of the reliabilities and MTTFs among the aforementioned topologies. The reliabilities in this table are calculated by inserting the transition rates values obtained in Table 8 and inserting them into Equations (6), (7) and (15)–(18). Moreover, insertion of transition rates in Table 8 in Equations (25)–(28) yields the MTTFs for the conventional HERIC, conventional H5, and IFTPVI, all of which are provided in Table 9.

As it is seen in Table 9, the IFTPVI has the highest reliability and the longest MTTF. It should be noted that time t in the reliability expressions in the table has a unit of ${10}^6$ h. A graphic study of the reliabilities for the IFTPVI, HERIC and H5 inverters is provided in Figure 12 to achieve a more in-depth and further detailed comparison.

6. Simulation and Experimental Results

6.1. Simulation Results

The performance of the ITFPVI is first investigated by the simulation studies in Matlab/Simulink^TM under the grid-tied condition. In the simulation model, the input voltage is a dc voltage of 350 V, and the RMS value and the frequency of the grid are 220 V and 50 Hz, respectively. Two inductor filters with 4.2 and 4 mH are used to interface the inverter to the grid since the filter inductors rarely have exactly the same inductances in practical applications. The switches are assumed to be IRFP450, and the switching frequency and parasitic capacitor are assumed to be 25 kHz and 300 nF, respectively.

In order to investigate the performance under different faulty conditions, three scenarios are considered. In the first scenario, the performance of the IFTPVI is evaluated under the healthy operation mode. In the second scenario, the fault occurs in one of the legs. In the last scenario, the reconfiguration of the inverter from HERIC to H5 is scrutinized when the fault occurs in the bidirectional switch (S_b).

In order to investigate the performance of the inverter, 2 kW active and 1.1 kVar reactive powers are injected into the grid. The output voltage and injected current under the mentioned conditions are displayed in Figure 13a. Furthermore, the leakage current (common mode current) under the mentioned condition is shown in Figure 13b. The root mean square (RMS) value of the common mode current is about 20 mA, which is below the rated value. It is to be mentioned that according to VDE-AR-N-4105 standard the rated value should be below 300 mA [40,41,42].

Since the configuration of the inverter after the fault in the first or second leg is the same, only the fault in the first leg is investigated. The output voltage of the inverter before and after the fault is shown in Figure 14a. As it can be seen in this figure, during the reconfiguration process that takes about 10 ms, the output voltage becomes zero, and the output current is interrupted. However, after the reconfiguration, the control unit resumes the normal operation of the inverter. The leakage current under this condition is shown in Figure 14b. As shown in the figure, during the reconfiguration the leakage current reaches 2 A. Since this reconfiguration takes place once in the life span of the inverter, this value of the current is not important as long as it does not exceed the maximum current value. Figure 14c shows the switches and relay signal before and after fault.

The other case is that the fault occurs in the bidirectional switch. Under this condition, the inverter should be reconfigured from the HERIC to H5. Since the HERIC inverter offers slightly higher efficiency compared to the H5, the efficiency will slightly decrease after the fault occurred in the bidirectional switch. The output voltage and current before and after the fault in the bidirectional switch are shown in Figure 15a. It is worth mentioning that the metal contacts of the electromechanical relays have almost zero resistance, and the relays will not affect efficiency. The leakage current before and after the reconfiguration is shown in Figure 15b. Comparing Figure 15b with Figure 14b shows that the H5 configuration causes a higher leakage current. Nevertheless, the common-mode current in both configurations is below the required threshold value. Figure 15c shows the switches and relay signal before and after fault.

In order to investigate the effect of the value of the load current on the leakage current, a load change is applied at the 0.2 s. The output voltage, injected current, and output voltage of the converter are shown in Figure 16a. The switching signals and relay command are shown in Figure 16b. Further, the leakage current under the mentioned condition is shown is Figure 16c. As seen in this figure, the value of the load current has no effect of the common-mode current (leakage current). This is because the leakage current depends on the capacitance of the parasitic capacitor, topology of utilized inverter, turn-on and turn-off speed, and voltage oscillation across the parasitic capacitor.

6.2. Experimental Results

In order to further prove the feasibility and viability of the proposed inverter topology, a laboratory-scaled prototype has been developed. The prototype is displayed in Figure 17, and its components’ characteristics are listed in

Table 10. Characteristics of the Prototype.

Switches	IRFP450
Gate-Driver	TLP 250
Relay	Omron
Processor	DSP F28335
Electrometrical Relays	Finder
Input Dc Voltage	350 V
Load	1.6 kW with PF = 0.87
Switching Frequency	5 kHz
Output Frequency	50 Hz

.

Since the results of the fault in the first and second legs are the same, only the fault in the first leg is given here. In this test, a fault is exerted on one of the switches in the first leg. In order to remove the faulty part, the corresponding relay turns on. The result of this test is shown in Figure 18a. As it is shown in this figure, the relay has successfully removed the faulty section and replaced it with the reserve leg. This action takes about 4 ms, which is a very short interval and can be neglected as it happens once in the inverter lifespan. Additionally, the voltages across the reserve switches before and after fault are shown in Figure 18b. As it is shown in Figure 18b, the voltage across the reserve switches is zero as they are in the floating state during the reserve mode. As the fault takes place and the switches join the active part, the input voltage appears across them. It is worthy to mention that since the reserve switches experience no voltage stress during the reserve time they are assumed to be healthy before becoming active.

Moreover, in order to investigate the reaction of the IFTPVI in the presence of a fault in the bidirectional switch, a fault is applied to the switch. As it was explained previously, under this condition, the IFTPVI should maintain the pre-fault operation characteristics by reconfiguring from the HERIC to H5 configuration. To do so, the corresponding relay R₁ should remove the bidirectional switch and add the upper switch of the reserve leg into the circuit. The output voltage and load current under the mentioned condition are shown in Figure 19a. As shown in the figure, the reconfiguration process takes almost 13 ms, which is short enough to be neglected. Furthermore, the voltages of the reserve switches are shown in Figure 19b. It is observed that the voltage stress of the unused reserve switch in this scenario remains the same. Since the mentioned switch is used as the fifth switch of the H5, it experiences one third of the input voltage as shown in Figure 19b. It is to be noted that the lower reserve switch experiences no voltage stress, as seen in Figure 19b.

7. Conclusions

In this paper, a fault-tolerant PV inverter has been proposed by effectively integrating a HERIC inverter, an H5 inverter, a reserve switch leg (half-bridge), and three electromechanical relays. The proposed inverter operates as a HERIC inverter under the normal condition. In the case when a fault occurs in any of the main legs, the corresponding relay removes the faulty leg and connects the reserve leg into the circuit so that the inverter keeps operating like the pre-fault configuration. If the fault occurs in the bidirectional switch, the corresponding relay reconfigures the inverter from HERIC to H5. In addition, a fault diagnosis method has been developed to identify and locate faults. The reliability analysis has been carried out to theoretically prove the reliability enhancement of the proposed topology. Furthermore, the simulation and experimental results have further verified the effectiveness and performance of the proposed PV inverter topology and successful reconfigurations of the inverter under different conditions.