Understanding the Origin of Metal Gate Work Function Shift and Its Impact on Erase Performance in 3D NAND Flash Memories

Abstract

We studied the metal gate work function of different metal electrode and high-k dielectric combinations by monitoring the flat band voltage shift with dielectric thicknesses using capacitance–voltage measurements. We investigated the impact of different thermal treatments on the work function and linked any shift in the work function, leading to an effective work function, to the dipole formation at the metal/high-k and/or high-k/SiO₂ interface. We corroborated the findings with the erase performance of metal/high-k/ONO/Si (MHONOS) capacitors that are identical to the gate stack in three-dimensional (3D) NAND flash. We demonstrate that though the work function extraction is convoluted by the dipole formation, the erase performance is not significantly affected by it.

1. Introduction

When it comes to low-cost and large density non-volatile memory, three-dimensional (3D) NAND flash memory technology is the industry standard [1,2]. The memory stack used in 3D NAND is inspired by a typical SONOS memory cell, which allows easy vertical integration and is addressed by horizontal word lines (WL). To improve the bit density, the number of cells in the vertical 3D NAND string is increased. This requires the stacking of many WLs, which need to be as thin as possible to limit the total height and mechanical stress of the structure [3]. Tungsten (W) metal-based WL is currently being used by the industry. However, novel materials with lower resistivity are being considered as future candidates to reduce the high resistive-capacitive (RC) delay that results as a consequence of WL thinning and continued stacking of the WLs (i.e., downscaling the metal thickness) in the vertical direction.

Moreover, the WL metal can act as an enabler to improve the 3D NAND erase operation. It was shown that high work function metals, such as TiN and Ru, can delay the electron injection from the gate (i.e., electrons tunneling from the gate into the charge-trap layer), thereby improving the erase window [4]. It has also been demonstrated [5] that when a metal gate is used in combination with a thin high-k liner, such as Al₂O₃, HfO₂, or ZrO₂ (i.e., a Metal/High-k/ONO/Si (MHONOS) structure), the erase performance can be further improved. Figure 1 plots the erase saturation levels (lowest possible threshold voltage, V_TH, shift achievable) for different scenarios, with and without a high-k liner, as simulated using our in-house developed 1D simulator [6]. The high-k liner helps to lower the injecting field for the electrons at the gate, and even proves to have a larger impact than the metal work function (WF). The erase is found to be penalized when the MHONOS stack is treated with a high thermal budget [3]. To thoroughly investigate the WL metal and high-k liner combination, and its effect on erase operation, metal work function extraction experiments have been proposed and studied in this work.

WF analysis of metal gate electrodes on high-k dielectrics, by monitoring flat-band voltage, V_FB (or threshold voltage, V_TH), have been demonstrated in the literature [7,8,9,10,11,12]. The studies report an undesirable shift in the V_FB (or V_TH) of metal-oxide-semiconductor (MOS) devices. The origins are unclear, leading to an effective work function (eWF) for the metal, different from the bulk values. Some reports in the literature attribute this shift to Fermi level pinning (FLP) caused either by metal-induced gap states [13,14,15] or charged defects/oxygen transfers, at the metal/high-k interface [12,16,17]. Dipole formation at the high-k/SiO₂ interface due to oxygen vacancies [18,19], and/or the energy offsets between the high-k and SiO₂ [20], have also been suggested in the literature as possible root causes for an eWF. Though, these studies suggest a notable dependence of eWF on the choice of high-k used, other process parameters such as gate electrode deposition and annealing conditions have been found to affect the eWF in a significant way as well [21].

In this paper, we investigate the change in WF (i.e., eWF) of metal electrodes deposited on high-k dielectrics. Based on the process conditions used, we evidence it to either the interfacial reactions at the WL-to-high-k contact or between the high-k and the oxide. The aim of this work is to understand the origins and consequences of WF shifts based on process conditions within the context of 3D NAND flash memory devices. Therefore, we also analyze various MHONOS stacks containing Al₂O₃, ZrO₂, HfO₂ high-k liners and TiN, Ru, Mo as gate metal, and corroborate the eWF with the erase performance of these stacks.

2. Materials and Methods

Capacitors with and without the charge trap layer were fabricated on 300 mm p-doped Si (100) wafers for erase analysis and WF extraction, respectively.

2.1. Work Function Extraction Methodology

The WF of a metal on high-k is determined by extracting V_FB from capacitance–voltage (CV) measurements on a metal-insulator-semiconductor (MIS) structure [22]. The schematic in Figure 2 shows the energy band diagram of an MIS structure. From this, we note that the metal work function can be expressed as follows

$${\Phi }_M=V_{FB}+{\chi }_{Si}+\left[E_C-E_F\right],$$

(1)

where Φ_M is metal work function, V_FB is flat-band voltage computed from CV measurements, χ_Si is electron affinity of Si substrate, E_C and E_F are the conduction band minima and fermi level.

However, the charges present in the bulk and at the interfaces of the oxides [23] can affect the V_FB as follows

$$\Delta V_{FB}={\int }_0^{t_{ox}}\frac{\rho \left(z\right)\left(t_{ox}-z\right)}{\epsilon \left(z\right){\epsilon }_0}dz,$$

(2)

From the above equation, it is clear that the effect of these oxide charges can be cancelled out by extracting the V_FB at zero oxide thickness. This calls for variations in SiO₂ and high-k thicknesses. With the help of a slant etch technique, the thickness of SiO₂ was varied across the wafer as shown in schematic in Figure 3. For each electrode, a set of 3 wafers with different high-k thicknesses (typically 3 nm, 5 nm, 7 nm) was used to provide enough variation and extract the WF conveniently. Typical CV measurements and V_FB extraction procedure are discussed in Appendix A.

The impact of oxide charges on V_FB can be mathematically expressed in terms of equivalent oxide thickness (EOT) and the corresponding charge densities as follows [24]

$$V_{FB}={\Phi }_{MS}+q·{\rho }_{HK}·{\epsilon }_{HK}·\frac{EO{T}_{HK}^2}{2·{\epsilon }_{ox}^2·{\epsilon }_o}+q·{\sigma }_{HK}·\frac{EO{T}_{HK}}{{\epsilon }_{ox}·{\epsilon }_o}+q·{\rho }_{Si{O}_2}·\frac{0.5·T_{Si{O}_2}^2+\left(\frac{{\epsilon }_{HK}}{{\epsilon }_{ox}}\right)·T_{Si{O}_2}·EO{T}_{HK}}{{\epsilon }_{ox}·{\epsilon }_o}+q·{\sigma }_{Si{O}_2}·\frac{EO{T}_{total}}{{\epsilon }_{ox}·{\epsilon }_o},$$

(3)

where q is the electron charge, ρ_HK and σ_HK are the bulk and interface charge densities of high-k dielectric, respectively. The terms ρ_SIO2 and σ_SIO2 are the corresponding bulk and interface charge densities of SiO₂, respectively. EOT_HK, T_SiO2, and EOT_total are the equivalent oxide thickness of high-k, thickness of SiO₂, and both combined, respectively. The EOT_total is in fact the measured EOT computed from the CV measurement of the MIS capacitors. The terms ε_HK, ε_ox, ε_o are the relative permittivity of high-k, SiO₂ and permittivity of free space, respectively. The Φ_MS in the above equation, from which the metal WF is extracted, is later computed by extrapolating V_FB at EOT (both high-k and SiO₂) = 0.

First, a 30 nm thick layer of high quality SiO₂ was thermally grown at 900 °C. This was then etched back with a slant profile (as shown in Figure 3) by slowly immersing (at a constant rate) the wafer in a 1.9% hydrofluoric acid (HF) solution. The desired thickness range of SiO₂ is obtained across the wafer by modifying the rate of immersion accordingly. A nominal thickness range of 3–12 nm was used in this work. Then, after the slant etch, a 3 nm plasma enhanced atomic layer deposition (PEALD) SiO₂ was uniformly deposited at 300 °C, to mimic the blocking oxide in a 3D NAND device. Little wafer-to-wafer variations were observed in the oxide thickness, as measured by ellipsometry (see Figure 4a). The total EOT measured from CV will vary across the wafer due to the slant etch of thermal oxide, as shown in Figure 4b (bubble size represents magnitude of EOT).

After this, high-k liners, such as Al₂O₃, ZrO₂, and HfO₂, were deposited at 300 °C to their desired thicknesses, using atomic layer deposition (ALD). Finally, 20 nm ALD Ru or ALD TiN or PVD Mo were then deposited as the gate electrode. In order to isolate the impact of thermal treatment on individual layers, a high temperature anneal (T_anneal) was performed at different stages of the stack formation (as shown in Figure 5). For instance, some of the capacitors were subjected to a post metallization anneal (PMA) for 20 min at 750 °C in N₂ ambient. A few others were subjected to a post high-k deposition anneal (PDA), where the entire stack sans the metal electrode received a thermal treatment for 1 min at 1050 °C for Al₂O₃-based stacks and 1 min at 750 °C for the rest, all in N₂ ambient. All wafers received a final sintering anneal in 5 atm H₂ ambient at 450 °C for 30 min.

CV measurements were performed on 70 × 70 μm² capacitors at a frequency of 100 kHz. The parameters needed for the WF extraction, namely, V_FB, the substrate doping concentration and the total EOT, EOT_total, are estimated (see Appendix A) with the help of NCSU’s CVC model fitting software [25]. Based on the expression for V_FB from Equation (3), we can express V_FB as a second order polynomial equation in terms of the EOT, as the one below

$$V_{FB}={\Phi }_{MS}+a·EO{T}_{HK}^2+b·EO{T}_{HK}+p·T_{Si{O}_2}^2+q·T_{Si{O}_2},$$

(4)

where a, b, p, and q contain the charge densities of high-k and SiO₂.

From the above equation, we can first eliminate the effect of charges in SiO₂ with a second order polynomial fit of the V_FB with the thickness of SiO₂, T_SiO2. A sample fit is shown in Figure 6. The intercept from the first fit contains the polynomial equation with high-k EOT, EOT_HK and hence is used to eliminate the charges from high-k in a second fit.

As mentioned earlier, we have the EOT_total of the stack as measured from CV. In order to get the T_SiO2 to be used in the first fit, we make use of the ellipsometry data that was measured at preset locations across the wafer, after the slant etch and PEALD deposition. This data is then compared with corresponding dies for which the CV was measured. The difference between the measured EOT_total and this ellipsometry data will give an estimate of the EOT_HK.

The three curves shown in Figure 6 represent the three wafers with three different high-k thicknesses needed for sufficient variation to eliminate the charges affecting the V_FB. The corresponding intercept from the 2nd order fit of the above curves is then used in a second fit, as shown in Figure 7 below.

The intercepts vs. the EOT_HK will now help to eliminate the charges in high-k. The intercept from this second fit is the Φ_MS from which the WF is computed using the formula

$$WF=4.05+{\Phi }_{MS}+E_C-E_F,$$

(5)

where $E_C-E_F\left(in eV\right)=1.12-0.0257\ast \ln \left(\frac{1.83E19}{median doping concentration in the substrate}\right).$

2.2. NAND Flash Erase Analysis

Incremental Step Pulse Erase (ISPE) characteristics were studied by monitoring the shift in V_TH of MHONOS capacitors from their fresh state. The erase operation is divided into a number of steps with increasing amplitude (for a duration of 1 ms) in applied voltage and at the end of each of them a verify operation is applied to check the V_TH. The amplitude and rate of change in V_TH is considered as a measure of erase performance.

Large MHONOS capacitors (50 × 50 μm²) were fabricated on 300 mm p-doped Si (100) wafers, as shown in Figure 8b. N⁺-doped rings were processed, surrounding the active area of the capacitors, to provide minority carriers for program operation. In a study reported elsewhere [3], we have demonstrated a 3D NAND test structure with 5 layers and showed that the memory characteristics of the stack (see Figure 8a) are qualitatively similar to that of the planar test structures that we typically use (see Figure 8b). Moreover, the gate stack deposited in this work mimics the one of 3D NAND in production [3,26] in terms of annealing processes and high-k/metal gate depositions performed. Therefore, we could fairly say that the results obtained from the planar capacitors in this work are relevant for 3D NAND flash memory devices.

The MHONO stack, as seen from the TEM image in Figure 9a, consists of a 6 nm SiON (with 20% N-to-O ratio) tunnel layer deposited using CVD at 780 °C, 6 nm LPCVD Si₃N₄ charge trap layer deposited at 690 °C, 7 nm PEALD SiO₂ blocking oxide deposited at 300 °C, and 2 nm ALD Al₂O₃ or ZrO₂ or HfO₂ high-k liner deposited at 300 °C. A total of 20 nm ALD Ru or ALD TiN or PVD Mo were then deposited as the gate electrode (WL, wordline). Similar to the study of WF extraction, a post metallization anneal, PMA for 20 min at 750 °C in N₂ ambient, and a post deposition anneal, PDA for 2 min at 1050 °C for Al₂O₃ based stacks and 1 min at 750 °C for the rest, all in N₂ ambient, were performed for some of the capacitors (see Figure 9b). All wafers were subject to a final sintering anneal either in forming gas at 420 °C for 20 min or in 5 atm H₂ ambient at 450 °C for 30 min. We may note that the sintering anneal has little influence on the final erase saturation levels.

3. Results and Discussion

The metal WF extracted in this work are listed as a histogram plot in Figure 10 for a few metal/high-k combinations. No high temperature anneals were performed for these splits. W Ref represents the CVD W/thin (3 nm) ALD TiN/Al₂O₃ liner stack similar to the one used currently in 3D NAND production. We could note that the WF of TiN in combination with Al₂O₃ is estimated to be about 4.53 eV and is in close agreement with the actual TiN WF reported in the literature [27,28]. What is surprising is the WF of Ru in combination with Al₂O₃, which is about 200–300 meV less than those reported in the literature for Ru metal [29,30]. It has been demonstrated, using internal photoemission experiments [31], that subtle changes in the chemical bonding at the metal/high-k interface can cause a significant impact on the barrier height (Φ_b, as shown in Figure 2) at this interface. Such chemical modifications could occur from various processing, such as conditions of deposition, thermal budget, and ambient of annealing process. As a consequence, this could lead to a shift in the WF of the metal. However, it is possible to avert this interfacial reaction by using appropriate interfacial layer (IL), as can be seen from Figure 10. The WF of Ru improves to 4.8 eV by adding a thin (3 nm) TiN liner between Ru and Al₂O₃.

In order to verify whether these shifts, measured in WF of Ru, reflect the actual change in metal WF, we compared the erase performance of these stacks. Figure 11 shows the ISPE curves for MHONOS stacks containing the metal/high-k combinations from Figure 10. The erase saturation (lowest VT shift achieved in ISPE) for TiN and Ru on Al₂O₃ (WF ~4.6 eV) is comparable after accounting for the differences in the starting V_TH, while that of W Ref (WF ~4.9 eV) is better, corroborating the WF difference between these stacks. With the addition of TiN liner, the WF of Ru improves, and so does the erase saturation.

We may note that the WF extracted from the Ru/TiN/Al₂O₃ stack is slightly less than that of W Ref, i.e., W/TiN/Al₂O₃ stack, yet the erase is better with Ru. Before addressing this, let us look at Figure 12a,b, which display the WF extracted for Ru, Mo, and TiN in combination with HfO₂, ZrO₂, and Al₂O₃ after different annealing conditions, as described in Figure 5. From Figure 12a, we could note a significant reduction (>500 meV) in the WF of Ru after the thermal treatment, irrespective of whether the metal electrode received the anneal (PMA) or not (PDA). The ISPE curves for these stacks are shown in Figure 13a. The stack that received the PDA does not change in erase while the one that received a PMA degrades both in erase slope and saturation level. We can also note from Figure 12b and Figure 13b that without any high temperature anneals, both Ru and Mo show similar WF and erase saturation levels in combination with ZrO₂. Though after a thermal treatment (PMA or PDA), the WF reduces irrespective of the metal or high-k used, the erase saturation depends on the type of anneal applied. These observations (made from Figure 10, Figure 12, Figure 13) hint that (a) the WF alone is not the reason for erase functionality, and (b) an extra factor, unaccounted in the extraction, is affecting the WF, resulting in an effective work function, eWF, being measured from the experiments.

It is important to note that in the case of TiN with Al₂O₃ (PDA performed at 2min 1050 °C), the degradation in erase saturation is much worse, which is unlike the observations made for HfO₂- and ZrO₂-based stacks, and definitely not reflected in the WF reduction in TiN. A closer study on the high-k material properties reported elsewhere [32], investigated by trap spectroscopy, revealed that worse erase saturation levels at increased thermal budgets could be due to an increase in defect density in the high-k rather than a reduction in the metal WF itself. Higher defect density could increase trap-assisted tunneling [33], thereby increasing the leakage current during the erase operation (a typical band diagram during erase can be seen in Figure 14).

As discussed before, Fermi level pinning (FLP) at the metal/high-k interface, dipole formation at the high-k/SiO₂ interface, and/or the energy offsets between the high-k and SiO₂ have been suggested in the literature as possible root causes for an eWF. If the metal fermi level is pinned, then the Φ_b at the interface should be different, which reflects in the erase saturation levels. Based on the observations made from Figure 11 for Ru with TiN liner and Figure 13 for Ru stacks after PDA, this effect can be ruled out. A common opinion in the literature [21,34,35,36] is that a dipole formed at the high-k/SiO₂ interface is the dominant factor causing appreciable shifts in V_FB, and hence, the WF extracted from it. Many physical models exist to explain this dipole formation, attributing it to dielectric contact induced gap states [37] or dictated by the electronegativity and ionic radii of the cations (from the high-k) [38], However, the most acceptable explanation seems to be oxygen vacancies driven by structural stabilization at the high-k/SiO₂ interface [18,19,20,21,34,39,40]. Moreover, the dipole formation at the high-k/SiO₂ interface should not affect the erase performance of flash memory, which is determined by the electron injection dynamics at the gate contact.

To further clarify the impact of dipole formation on erase performance of flash memory, dipole-forming interlayers (DIL) [36,41,42], namely, Al₂O₃ and La₂O₃ (0.6 nm each), were studied as part of the MHONOS stack (shown in Figure 15). The DIL were deposited between metal and high-k or high-k and SiO₂, with TiN/HfO₂ being used as the control gate electrode and high-k dielectric. All the stacks received a PDA for 1.5 s at 1050 °C in N₂ ambient. The corresponding shifts in V_FB caused by the interlayers were extracted from CV measurements using CVC fitting (as can be seen in Figure 16).

We could note from Figure 16a that with the addition of Al₂O₃ DIL between HfO₂ and SiO₂, the V_FB positively increases by about 120 meV, while it remains unchanged when Al₂O₃ is inserted between the metal and high-k. Though much higher V_FB shifts are theoretically reported for Al₂O₃ [18], the processing conditions and thickness of the DIL play a major role in determining the magnitude of the V_FB shifts [21,42,43]. Furthermore, if we add 0.6 nm La₂O₃ DIL between HfO₂ and SiO₂ while keeping the Al₂O₃ between TiN and HfO₂, we notice a negative drop of about 140 meV in the V_FB, which is in line with trends reported in the literature [44,45]. It is worth to note that the trend in V_FB remains unchanged after a PMA for 20 min at 750 °C in N₂ ambient (see Figure 16b).

The ISPE curves for these stacks without PMA are shown in Figure 17a. We could note, despite the differences in V_FB, that there is no difference in the erase performance of these stacks. On the contrary, when the stacks were subjected to PMA, the erase depends on the material present in the stack, as can be seen in Figure 17b. The control sample with only TiN and HfO₂ shows slight degradation after PMA. However, the stacks with DIL show higher reduction in erase, even worse when the Al₂O₃ is present next to the blocking oxide, though it shows a positive V_FB shift (indicating a higher eWF). It is well known that Al₂O₃ dielectric suffers from a wider band of defect profile [46]. Recalling the discussion from before on the possible impact of defect density in the high-k on erase (see Figure 14), we could fairly say that the above results corroborate this hypothesis.

4. Conclusions

We have extracted and studied the shifts in metal work function (i.e., effective work function, eWF), in response to different processing parameters, such as gate electrode and high-k dielectric materials, and variations in annealing conditions. By studying the work function in combination with the erase performance of NAND flash memory, we were able to narrow down the origin of eWF to dipole formation due to (a) interfacial reactions at the metal/high-k interface and/or (b) possible oxygen vacancies driven by structural stabilization at the high-k/SiO₂ interface. It must be noted that based on the above studies, we did not observe fermi level pinning at the metal/high-k interface.

We also verified and validated the negligible impact of dipole on erase performance by studying different dipole forming interlayers in the memory cell. It is clear that the metal WF extraction is convoluted by dipole formation, while the erase performance of a flash memory cell is affected more by the trap profile in the high-k liner than any other factors that cause shift in flat band voltage.