Analyzing Transfer Characteristics of Disordered Polymer Field-Effect Transistors for Intrinsic Device Parameter Extraction

Abstract

In this study, we present an intrinsic device parameter method based on a single device for disordered polymer field-effect transistors (PFETs). Charges in disordered polymer semiconductors transport through localized states via thermally activated hopping, of which field-effect mobility and contact resistance are gate-bias-dependent. By considering the parameters expressed as gate bias-dependent power laws, dividing drain current with transconductance (I_ds/g_m method) leads to the current–voltage relation decoupled from the contact effect. Following this derived relationship, the intrinsic field-effect mobility and the contact resistance of the PFETs are extracted and found to be consistent with those using the four-probe method. Thus, we can state that the proposed method offers practical benefits for extracting the intrinsic device parameters of disordered PFETs in terms of using a single transfer characteristic of the devices.

1. Introduction

In recent decades, solution-processable polymer field-effect transistors (PFETs) have received considerable attention due to their massive potential for applications in flexible displays, logic circuits, and wearable devices [1,2,3,4]. Especially, donor–acceptor (D–A)-type semiconducting copolymers containing donor or acceptor moieties such as diketopyrrolopyrrole (DPP), isoindigo, naphthalenediimides (NDI), benzothiadiazole, and indacenodithiophene (IDT), exhibit remarkable field-effect mobilities exceeding 10 cm² V⁻¹ s⁻¹ [5,6,7,8,9]. However, the inevitable contact resistance in transistors generally results in under or overestimating field-effect mobility [10,11,12]. Thus, the device parameters should be carefully determined. To extract device parameters decoupled from the contact effects, several approaches have been suggested, such as measuring potential distribution in the channel by placing the voltage probes (i.e., four-probe method) [13], extracting the channel conductance by varying the channel length (i.e., transmission line measurement or transfer length measurement) [14], and eliminating contact effects using the drain current and transconductance (i.e., Y-function method) [15]. While there is progress, they often require specific channel geometries, rendering their general application to PFETs. In the case of the differential method [16,17], TFTs that have different channel lengths should be used for the extraction. However, if we use multiple devices for the parameter extraction, the deduced results can be erroneous due to uniformity issues. In addition, the Y-function method could be used for the extraction using a single device, but the results could be carefully examined for disordered semiconductors [18]. The Y-function method is established for Si-based transistors, of which the parameters are considered to be gate-bias independent. However, due to the localized states, the parameters of the disordered semiconductor-based PFETs are gate-bias dependent [19,20]. For these reasons, we regard simple and reliable intrinsic parameter extraction methods using a single device are required for disordered semiconductor-based PFETs.

Here, we explore an intrinsic device parameter method for disordered polymer field-effect transistors (PFETs). By considering the field-effect mobility and contact resistance as the gate bias-dependent power-laws [21,22], the current-voltage relation decoupled from the contact effect is derived by dividing the drain current with transconductance (I_ds/g_m method). With this relation, the contact resistance and intrinsic mobility are successfully extracted using a single device, and the parameters are found to be consistent with those by the four-probe method. Hence, we regard our proposed method as a simple and reliable extraction method using a single device for disordered PFETs.

2. Materials and Methods

Bottom-gate, top-contact (BGTC) polymer field-effect transistors (PFETs) were fabricated, as shown in Figure 1a. A chemically cleaned 300 nm-thick p⁺-Si/SiO₂ wafer was used as the substrate, and hexamethyldisilazane (HMDS) was spin-casted and thermally annealed at 150 °C for 60 min in a nitrogen atmosphere to minimize the interface traps [23]. Poly [2,5-(2-octyldodecyl)-3,6-diketopyrrolopyrrole-alt-5,5-(2,5-di(thien-2-yl) thieno [3,2-b]thiophene)], (DPP-DTT, Mw (~75,000) with a PDI of 2.5), and poly(2,5-bis(3-tetradecylthiophen-2-yl)thieno [3,2-b]thiophene) (PBTTT, Mw (~50,000) with a PDI of 3.0) were purchased from 1-Material, Inc and Sigma-Aldrich, respectively. Then, polymer semiconducting materials were dissolved in chloroform at concentrations of 10 mg/mL, spin-casted, and subsequently thermally annealed at 150 °C for 60 min in nitrogen. Next, 50 nm thick Au source and drain electrodes were deposited by thermal evaporation and patterned using a shadow mask. For a passivation layer, poly (methyl methacrylate) PMMA was dissolved in n-butyl acetate at a concentration of 80 mg/mL, spin-casted, and cured at 80 °C for 60 min. Finally, the layers were patterned by reactive etching with Ar gas to mitigate the side-current effects on the devices [24]. The channel width and length of PFETs were 1000 and 360 μm, respectively. The surface morphologies of the films were scanned with an atomic force microscope (XE100, Park Systems, Suwon, Korea). The geometric capacitance of the dielectric was measured to be 10.9 nF cm⁻² at 1 kHz using an LCR meter (HP4284A, Agilent Technologies, Santa Clara, CA, USA). The current-voltage (I–V) characteristics of the transistors were investigated with a semiconductor parameter analyzer (Model HP4155C, Agilent Technologies). The extrinsic field-effect mobility of the PFETs in the linear regime was extracted using Equation (1).

$${\mu }_{lin}=\frac{1}{C_i{V}_{ds}}\frac{L}{W}\frac{\mathit{\partial }{I}_{ds}}{\mathit{\partial }{V}_{gs}}$$

(1)

where I_ds is the drain current, V_gs is the gate voltage, C_i is the geometric dielectric capacitance, V_ds is the drain voltage, and L and W are the channel length and width, respectively. In addition, by measuring the potentials in the channel with the voltage probes (V₁ and V₂), the intrinsic field-effect mobility (μ_int) and contact resistance (R_c) were estimated, which are given by Equations (2) and (3) [13,18]:

$$V_{ch}=\frac{\left(V_2-V_1\right)}{\left(L_2-L_1\right)}\left(L\right){,V}_c=V_{ds}-V_{ch}$$

(2)

$${\mu }_{int}=\frac{1}{C_i{V}_{ch}}\frac{L}{W}\frac{\mathit{\partial }{I}_{ds}}{\mathit{\partial }{V}_{gs}},R_c=\frac{V_c}{I_{ds}}$$

(3)

where V_ds, V_1, and V₂ are the drain voltage and measured voltages with potential probes, and L₁, L₂, and L are the distance from the source electrode to the first, second, and drain electrodes, respectively. In this study, the voltage probing electrodes (V₁ and V₂) were placed at 120 and 240 μm in the channel.

3. Results

Figure 1b displays the representative transfer characteristics (I_ds vs. V_gs) of the PBTTT-based PFETs; it exhibits p-type characteristics, of which the field-effect mobility (μ_ext) from the transconductance was estimated to be ~0.009 cm² V⁻¹ s⁻¹ along with a high on/off ratio (>10³). The gate leakage current level was maintained as low as 10⁻¹⁰ A. Figure 1c presents the corresponding output characteristics (I_ds vs. V_ds) of the PFETs. Then, for extracting the intrinsic referential parameters of the PFETs, we investigated the transfer characteristics with the four-probe method. Please see the material and methods section for more information on the four-probe method. Figure 2a shows the measured channel and contact potentials as a function of the gate bias at the drain bias of –1, −3, and −5 V. As seen in Figure 2b,c, regardless of the applied drain bias, the contact resistance (R_c) was gradually decreased to be ~8.9 × 10⁵ Ω cm at V_gs= −40 V, and the intrinsic field-effect mobility (μ_int) was estimated to be ~0.010 cm² V⁻¹. Thus, it is highly believed that the gate-bias-dependent intrinsic device parameters are precisely extracted by the four-probe method. However, placing the voltage–probing electrodes in specifically designed electrode geometries, such as interdigitated or circle-type source-drain electrodes, can be challenging. In addition, to our best knowledge, device parameter extraction methods using a single device for disordered semiconductors are scarcely reported [16]. Hence, we have tried to establish reliable extracting methods for disordered semiconductor-based thin-film transistors using a single transfer characteristic.

As reported elsewhere, charges in disordered semiconductors transport through localized states via thermally activated hopping, of which the intrinsic field-effect mobility (μ_int) and the contact resistance (R_c) can be expressed as gate bias-dependent power laws in Equation (4) [25,26,27,28]. In addition, as depicted in Figure 2a, the voltage drop (I_dsR_c) is considered almost independent of the gate bias, which leads to the condition α + β + 1 = 0. Hence, the drain current (I_ds) and transconductance (g_m) can be expressed as gate bias-dependent power laws as in Equations (5) and (6):

$${\mu }_{int}={\mu }_{int,0}{\left(V_{gs}-V_{th}\right)}^{\alpha },R_c=R_0{\left(V_{gs}-V_{th}\right)}^{-\left(\beta \right)}$$

(4)

$$I_{ds}=\frac{{\mu }_{int,0}{C}_i\frac{W}{L}{\left(V_{gs}-V_{th}\right)}^{\alpha +1}{V}_{ds}}{1+{\mu }_{int,0}{R_{0}C}_i\frac{W}{L}}$$

(5)

$$g_m=\frac{{\mathit{\partial }I}_{ds}}{\mathit{\partial }{V}_{gs}}=\frac{\left(\alpha +1\right){\mu }_{int,0}{C}_i\frac{W}{L}{\left(V_{gs}-V_{th}\right)}^{\alpha }{V}_{ds}}{1+{\mu }_{int,0}{R_{0}C}_i\frac{W}{L}}$$

(6)

where μ_int,0, R₀, and α are the coefficients and the exponents of the power law of the intrinsic field-effect mobility and the contact resistance, respectively. Then, the coefficient of α and the threshold voltage (V_th) can be estimated by dividing the drain current with the transconductance (I_ds/g_m) as in Equation (7),

$$\frac{I_{ds}}{g_m}=\frac{\left(V_{gs}-V_{th}\right)}{\left(\alpha +1\right)}$$

(7)

Moreover, the coefficient of contact resistance (R₀) can be given by Equations (8) and (9), of which the drain current (I_ds) can be described in terms of extrinsic and intrinsic mobility.

$$I_{ds}=\frac{{\mu }_{int,0}{C}_i\frac{W}{L}{\left(V_{gs}-V_{th}\right)}^{\alpha +1}{V}_d}{1+{\mu }_{int,0}{R_{0}C}_i\frac{W}{L}}={\mu }_{ext}{C}_i\frac{W}{L}\left(V_{gs}-V_{th}\right)V_{ds}$$

(8)

$$\begin{gathered} R_0=\left(\frac{\left(1+\alpha \right)}{{\mu }_{ext,0}}-\frac{1}{{\mu }_{int,0}}\right)\frac{L}{C_{i}W}for{V}_{gs}-V_{th}=1V \\ \approx \left(\frac{\left(\alpha \right)}{{\mu }_{ext,0}}\right)\frac{L}{C_{i}W}if{\mu }_{int,0}\approx {\mu }_{ext,0} \end{gathered}$$

(9)

where μ_ext,0 is the coefficient of the extrinsic field-effect mobility. After deducing the coefficient contact resistance (R₀), the contact-effect removed drain current (I_ds,int) can be determined by removing the contact resistance from the total resistance, and the resulting intrinsic mobility can be extracted as in Equations (10) and (11), respectively.

$$I_{ds,int}=\frac{V_{ds}}{R_{ch}}=\frac{V_{ds}}{\frac{V_{ds}}{I_{ds}}-R_0{\left(V_{gs}-V_t\right)}^{-\left(\alpha +1\right)}}$$

(10)

$${\mu }_{int}=\frac{1}{C_i{V}_D}\frac{L}{W}\frac{\mathit{\partial }{I}_{ds,int}}{\mathit{\partial }{V}_{gs}}$$

(11)

Figure 3a shows the extraction plot of I_ds/g_m for PBTTT-based PFETs. The coefficient of α and the threshold voltage (V_th) is extracted to be 0.51 and 9.41 V, 0.56 and 11.33 V, and 0.59 and 11.82 V, at the drain biases of −1, −3, and −5 V, respectively. In addition, the coefficient contact resistance (R₀) was extracted to be 0.85, 2.55, and 2.30 × 10⁹ Ω cm at the drain biases, respectively. Then, the contact resistances and intrinsic mobilities were estimated as in Figure 3b, 3c, and 3d, respectively. Although the deduced coefficients of α and the threshold voltages (V_th) are slightly different at the given biases, the consequential contact resistances (R_c) and the intrinsic field-effect mobilities (μ_int) are deduced to be almost the same values; R_c was gradually decreased to be ~3.2 × 10⁶ Ω cm at V_gs= −40 V, and μ_int was extracted to be ~0.015 cm² V⁻¹, which comparable with those obtained by the four-probe method. Please note that when we tried to extract parameters using the Y-function method for the PFETs, as depicted in Figure S1, only gate-bias-independent parameters were estimated, of which the field-effect mobility was slightly overestimated to be 0.017 cm² V⁻¹, and the contact resistance was underestimated to be 2.1 × 10⁶ Ω cm, respectively. As estimated by the 4-probe method and the I_ds/g_m method, the parameters should be gate-dependent. Thus, we strongly believe that the proposed extraction method of the I_ds/g_m method is simple and promising for extracting the intrinsic parameters using a single device. Please note that the intrinsic mobility from the 4-probe method and the extrinsic mobility of the HMDS-treated PBTTT TFTs (at V_gs − V_th = 1 V) was almost the same as extracted to be 0.0012 and 0.0013 cm² V⁻¹ s⁻¹, respectively. Thus, we tried to derive the relations based on the assumption in Equation (9) (μ_int,0 ≈ μ_ext,0). However, it is still unconfirmed whether the proposed extraction method is reliable for other PFETs. Hence, to ensure that the I_ds/g_m method is applicable in more general, we have fabricated PFETs using another organic semiconductor of DPP-DTT, and the device parameters of the PFETs are analyzed in the same manner.

Figure 4a shows the representative transfer characteristics of the DPP-DTT PFETs. It displays p-type characteristics, and the extrinsic field-effect mobility is estimated to be ~0.021 cm² V⁻¹ s⁻¹ with a high on/off ratio (>10⁴). Figure 4c displays the extraction plot of I_ds/g_m for DPP-DTT PFETs, of which the coefficient of α and the threshold voltage (V_th) is extracted to be 0.68 and −5.91 V, respectively. Remarkably, although the DPP-DTT PFETs show Schottky characteristics in output characteristics of Figure 4b, intrinsic mobility, and contact resistance are estimated to be almost the same as ~0.029 cm² V⁻¹ and ~1.5 × 10⁶ Ω cm at V_gs= −40 V with those by the 4-probe method in Figure 4d. This indicates the proposed method can effectively rule out the contact effect from the drain current. Furthermore, to gain insights into the device analyses using the method, we have fabricated octadecyltrichlorosilane (OTS)-treated DPP-DTT PFETs, and the device parameters are compared with those of the HMDS-treated DPP-DTT PFETs. Figure 5a shows the representative transfer characteristics of the PFETs. Figure 5b,c exhibit the estimated intrinsic motilities and contact resistances of the PFETs by the I_ds/g_m method, respectively. Noteworthy, compared to HMDS-treated PFETs, OTS-treated PFETs exhibit enhanced p-type characteristics. The hole current at V_gs = −40 V increases over ten times (from ~10⁻⁷ to ~10⁻⁶ A), and the threshold voltage of the PFETs clearly shifts from −5.91 to 1.35 V. As a result; the field-effect mobility massively improves up to 0.351 cm² V⁻¹ s⁻¹. In addition, the mobility of the OTS-treated PFETs increases in the given applied bias regime, which can be expressed with the power law. However, the field-effect mobility of the HMDS-treated PFETs increases up to the gate bias of −15 V, but slightly decreases beyond the voltage, probably due to charge scattering in the channel [29,30,31]. We posit that these enhancements of the PFETs would be mainly attributed to the improved coplanarity and interchain connectivity of the donor–acceptor (D–A)-type conjugated copolymers by the surface treatment with OTS. As seen in Figure 5c,d, nano-fibril microstructures with large grains can definitely be found in OTS-treated DPP-DTT films. The root mean square (RMS) surface roughness of OTS-treated DPP-DTT films was measured to be 0.87 nm, while that of HMDS-treated DPP-DTT films was 0.62 nm. Hydrophobic characteristics of the OTS, as in Figure S2, would allow the conjugated copolymers to interact and aggregate strongly with each other, leading to enhanced intermolecular interactions. As a result, the charge scattering is minimized in the PFETs, enhancing the field-effect mobility. Moreover, the contact resistance of the OTS-treated PFETs was also significantly decreased to ~10⁵ Ω cm, which compared to that of the HMDS-treated PFETs of ~10⁶ Ω cm. The enhanced ordering of the polymers leads to improved charge carrier injection from the source electrode to the π-electron orbitals of the polymers, decreasing the contact resistance of the PFETs [32,33]. The extraction plot and the output characteristics (I_ds vs. V_ds) of the OTS-treated DPP-DTT PFETs are depicted in Figure S3. The observed device performances of the PFETs appear primitive, and parameter estimations using other polymer semiconductors, such as n-type or ambipolar semiconducting polymers, would be required to prove the method is applicable in more general. In addition, probably due to the charge scattering, the deduced contact resistance and mobility by the I_ds/g_m method are slightly under and overestimated than those by the 4-probe method. As the gate bias increases, the discrepancy between the observed mobility and the power-law modeled field-effect mobility (μ_int = μ_int,0(V_gs − V_th)^α) would increase and result in the underestimation of the coefficient of α. As a result, the deduced contact resistance and mobility could be slightly under and overestimated than those by the 4-probe method. For PBTTT PFETs, the channel scattering effect could be greater than those in D–A type semiconducting copolymers of DPP-DTT, resulting in more deviated parameters. However, the estimated contact resistances by both methods are in order, and the differences in the mobilities are in the suborder of 10⁻³ cm² V⁻¹ s⁻¹. Thus, we regard the parameter extraction method of the I_ds/g_m method as reliable. The extracted device parameters, such as field-effect mobility and contact resistance of the devices, are summarized in

Table 1. Summary of device parameters for the PFETs used in this study.

Semiconductors	Extraction Methods	μ (cm2 V−1)	Power Law Exponent	Rc at −40 V (Ω cm)
HMDS-treated PBTTT	Trans. method	0.009	Not available	Not available
	Four-probe method	0.010	Not available	8.9 × 105
	Ids/gm method	0.015	0.59	3.2 × 106
	Y-function method	0.017	Not available	2.1 × 106
HMDS-treated DPP-DTT	Trans. method	0.023	Not available	Not available
	Four-probe method	0.029	Not available	1.6 × 106
	Ids/gm method	0.028	0. 68	1.2 × 106
OTS-treated DPP-DTT	Ids/gm method	0.351	0.18	4.8 × 104

.

4. Conclusions

In this study, we investigate an intrinsic device parameter extraction method for disordered polymer field-effect transistors (PFETs). Due to the localized states of the disordered polymer semiconductors, the field-effect mobility and contact resistance are strongly dependent on the gate bias. In addition, because of the inevitable contact and uniformity issues of the PFETs, extraction methods based on multiple devices should be carefully applied for the extraction. However, by considering the parameters as gate bias-dependent power laws and dividing the drain current with transconductance (I_ds/g_m method), current-voltage relations decoupled from the contact effect can be derived using a single transfer characteristic of the PFETs. Furthermore, the gate-dependent parameters, which are consistent with those obtained by the four-probe method, are successfully extracted using the relations. Moreover, using the proposed method, we can figure out that the enhanced device performances of the OTS-treated DPP-DTT PFETs are attributed to the minimized scattering and reduced contact resistance. Thus, we strongly believe that our proposed parameter extraction method based on a single device is a simple and reliable method for an in-depth study of device performance.