Journal of Low Power Electronics and Applications

14 pages, 2025 KiB

Open AccessFeature PaperArticle

Efficacy of Topology Scaling for Temperature and Latency Constrained Embedded ConvNets

by Valentino Peluso, Roberto Giorgio Rizzo and Andrea Calimera

J. Low Power Electron. Appl. 2020, 10(1), 10; https://doi.org/10.3390/jlpea10010010 - 13 Mar 2020

Cited by 4 | Viewed by 4333

Embedded Convolutional Neural Networks (ConvNets) are driving the evolution of ubiquitous systems that can sense and understand the environment autonomously. Due to their high complexity, aggressive compression is needed to meet the specifications of portable end-nodes. A variety of algorithmic optimizations are available [...] Read more.

Embedded Convolutional Neural Networks (ConvNets) are driving the evolution of ubiquitous systems that can sense and understand the environment autonomously. Due to their high complexity, aggressive compression is needed to meet the specifications of portable end-nodes. A variety of algorithmic optimizations are available today, from custom quantization and filter pruning to modular topology scaling, which enable fine-tuning of the hyperparameters and the right balance between quality, performance and resource usage. Nonetheless, the implementation of systems capable of sustaining continuous inference over a long period is still a primary source of concern since the limited thermal design power of general-purpose embedded CPUs prevents execution at maximum speed. Neglecting this aspect may result in substantial mismatches and the violation of the design constraints. The objective of this work was to assess topology scaling as a design knob to control the performance and the thermal stability of inference engines for image classification. To this aim, we built a characterization framework to inspect both the functional (accuracy) and non-functional (latency and temperature) metrics of two ConvNet models, MobileNet and MnasNet, ported onto a commercial low-power CPU, the ARM Cortex-A15. Our investigation reveals that different latency constraints can be met even under continuous inference, yet with a severe accuracy penalty forced by thermal constraints. Moreover, we empirically demonstrate that thermal behavior does not benefit from topology scaling as the on-chip temperature still reaches critical values affecting reliability and user satisfaction. Full article

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15 pages, 1995 KiB

Open AccessArticle

AxCEM: Designing Approximate Comparator-Enabled Multipliers

by Samar Ghabraei, Morteza Rezaalipour, Masoud Dehyadegari and Mahdi Nazm Bojnordi

J. Low Power Electron. Appl. 2020, 10(1), 9; https://doi.org/10.3390/jlpea10010009 - 1 Mar 2020

Cited by 2 | Viewed by 5637

Abstract

Floating-point multipliers have been the key component of nearly all forms of modern computing systems. Most data-intensive applications, such as deep neural networks (DNNs), expend the majority of their resources and energy budget for floating-point multiplication. The error-resilient nature of these applications often [...] Read more.

Floating-point multipliers have been the key component of nearly all forms of modern computing systems. Most data-intensive applications, such as deep neural networks (DNNs), expend the majority of their resources and energy budget for floating-point multiplication. The error-resilient nature of these applications often suggests employing approximate computing to improve the energy-efficiency, performance, and area of floating-point multipliers. Prior work has shown that employing hardware-oriented approximation for computing the mantissa product may result in significant system energy reduction at the cost of an acceptable computational error. This article examines the design of an approximate comparator used for preforming mantissa products in the floating-point multipliers. First, we illustrate the use of exact comparators for enhancing power, area, and delay of floating-point multipliers. Then, we explore the design space of approximate comparators for designing efficient approximate comparator-enabled multipliers (AxCEM). Our simulation results indicate that the proposed architecture can achieve a 66% reduction in power dissipation, another 66% reduction in die-area, and a 71% decrease in delay. As compared with the state-of-the-art approximate floating-point multipliers, the accuracy loss in DNN applications due to the proposed AxCEM is less than 0.06%. Full article

(This article belongs to the Special Issue CMOS Low Power Design Vol. 2)

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18 pages, 1823 KiB

Open AccessArticle

Body Bias Optimization for Real-Time Systems

by Carlos C. Cortes Torres, Ryota Yasudo and Hideharu Amano

J. Low Power Electron. Appl. 2020, 10(1), 8; https://doi.org/10.3390/jlpea10010008 - 22 Feb 2020

Cited by 1 | Viewed by 4845

Abstract

The energy of real-time systems for embedded usage needs to be efficient without affecting the system’s ability to meet task deadlines. Dynamic body bias (BB) scaling is a promising approach to managing leakage energy and operational speed, especially for system-on-insulator devices. However, traditional [...] Read more.

The energy of real-time systems for embedded usage needs to be efficient without affecting the system’s ability to meet task deadlines. Dynamic body bias (BB) scaling is a promising approach to managing leakage energy and operational speed, especially for system-on-insulator devices. However, traditional energy models cannot deal with the overhead of adjusting the BB voltage; thus, the models are not accurate. This paper presents a more accurate model for calculating energy overhead using an analytical double exponential expression for dynamic BB scaling and an optimization method based on nonlinear programming with consideration of the real-chip parameter constraints. The use of the proposed model resulted in an energy reduction of about 32% at lower frequencies in comparison with the conventional model. Moreover, the energy overhead was reduced to approximately 14% of the total energy consumption. This methodology provides a framework and design guidelines for real-time systems and computer-aided design. Full article

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34 pages, 1898 KiB

Open AccessFeature PaperArticle

Logic-in-Memory Computation: Is It Worth It? A Binary Neural Network Case Study

by Andrea Coluccio, Marco Vacca and Giovanna Turvani

J. Low Power Electron. Appl. 2020, 10(1), 7; https://doi.org/10.3390/jlpea10010007 - 22 Feb 2020

Cited by 8 | Viewed by 7864

Abstract

Recently, the Logic-in-Memory (LiM) concept has been widely studied in the literature. This paradigm represents one of the most efficient ways to solve the limitations of a Von Neumann’s architecture: by placing simple logic circuits inside or near a memory element, it is [...] Read more.

Recently, the Logic-in-Memory (LiM) concept has been widely studied in the literature. This paradigm represents one of the most efficient ways to solve the limitations of a Von Neumann’s architecture: by placing simple logic circuits inside or near a memory element, it is possible to obtain a local computation without the need to fetch data from the main memory. Although this concept introduces a lot of advantages from a theoretical point of view, its implementation could introduce an increasing complexity overhead of the memory itself, leading to a more sophisticated design flow. As a case study, Binary Neural Networks (BNNs) have been chosen. BNNs binarize both weights and inputs, transforming multiply-and-accumulate into a simpler bitwise logical operation while maintaining high accuracy, making them well-suited for a LiM implementation. In this paper, we present two circuits implementing a BNN model in CMOS technology. The first one, called Out-Of-Memory (OOM) architecture, is implemented following a standard Von Neumann structure. The same architecture was redesigned to adapt the critical part of the algorithm for a modified memory, which is also capable of executing logic calculations. By comparing both OOM and LiM architectures we aim to evaluate if Logic-in-Memory paradigm is worth it. The results highlight that LiM architectures have a clear advantage over Von Neumann architectures, allowing a reduction in energy consumption while increasing the overall speed of the circuit. Full article

(This article belongs to the Special Issue Low Power Memory/Memristor Devices and Systems)

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22 pages, 3039 KiB

Open AccessFeature PaperArticle

An Acoustic Vehicle Detector and Classifier Using a Reconfigurable Analog/Mixed-Signal Platform

by Swagat Bhattacharyya, Steven Andryzcik and David W. Graham

J. Low Power Electron. Appl. 2020, 10(1), 6; https://doi.org/10.3390/jlpea10010006 - 20 Feb 2020

Cited by 9 | Viewed by 5102

Abstract

The wireless sensor nodes used in a growing number of remote sensing applications are deployed in inaccessible locations or are subjected to severe energy constraints. Audio-based sensing offers flexibility in node placement and is popular in low-power schemes. Thus, in this paper, a [...] Read more.

The wireless sensor nodes used in a growing number of remote sensing applications are deployed in inaccessible locations or are subjected to severe energy constraints. Audio-based sensing offers flexibility in node placement and is popular in low-power schemes. Thus, in this paper, a node architecture with low power consumption and in-the-field reconfigurability is evaluated in the context of an acoustic vehicle detection and classification (hereafter “AVDC”) scenario. The proposed architecture utilizes an always-on field-programmable analog array (FPAA) as a low-power event detector to selectively wake a microcontroller unit (MCU) when a significant event is detected. When awoken, the MCU verifies the vehicle class asserted by the FPAA and transmits the relevant information. The AVDC system is trained by solving a classification problem using a lexicographic, nonlinear programming algorithm. On a testing dataset comprising of data from ten cars, ten trucks, and 40 s of wind noise, the AVDC system has a detection accuracy of 100%, a classification accuracy of 95%, and no false alarms. The mean power draw of the FPAA is 43

μ

W and the mean power consumption of the MCU and radio during its validation and wireless transmission process is 40.9 mW. Overall, this paper demonstrates that the utilization of an FPAA-based signal preprocessor can greatly improve the flexibility and power consumption of wireless sensor nodes. Full article

(This article belongs to the Special Issue CMOS Low Power Design Vol. 2)

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11 pages, 3202 KiB

Open AccessFeature PaperArticle

High-Efficiency Switched-Capacitor DC-DC Converter with Three Decades of Load Current Range Using Adaptively-Biased PFM

by Anurag Veerabathini and Paul M. Furth

J. Low Power Electron. Appl. 2020, 10(1), 5; https://doi.org/10.3390/jlpea10010005 - 20 Feb 2020

Cited by 9 | Viewed by 5797

Abstract

A fully-integrated switched-capacitor (SC) DC-DC converter that steps down 2.0 V to 0.9 V with a peak efficiency of 80% is implemented in a 0.18

μ

m CMOS process. An ultra-low-power voltage-controlled oscillator that generates a wide range of switching frequencies is proposed [...] Read more.

A fully-integrated switched-capacitor (SC) DC-DC converter that steps down 2.0 V to 0.9 V with a peak efficiency of 80% is implemented in a 0.18

μ

m CMOS process. An ultra-low-power voltage-controlled oscillator that generates a wide range of switching frequencies is proposed to extend battery runtime. An efficiency >70% for load currents in the range of 12

μ

A to 17.8 mA is achieved by implementing a novel adaptively-biased pulse frequency modulation (ABPFM) technique in the controller. A symmetric charge-discharge topology with two-phase time interleaving is used as a power stage to reduce the output voltage ripple to <72 mV over the entire load current range. Full article

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3 pages, 226 KiB

Open AccessEditorial

Acknowledgement to Reviewers of Journal of Low Power Electronics and Applications in 2019

by Journal Of Low Power Electronics And Applications Editorial Office

J. Low Power Electron. Appl. 2020, 10(1), 4; https://doi.org/10.3390/jlpea10010004 - 23 Jan 2020

Viewed by 3665

Abstract

The editorial team greatly appreciates the reviewers who have dedicated their considerable time and expertise to the journal’s rigorous editorial process over the past 12 months, regardless of whether the papers are finally published or not [...] Full article

10 pages, 3337 KiB

Open AccessArticle

Threshold Voltage Degradation for n-Channel 4H-SiC Power MOSFETs

by Esteban Guevara, Victor Herrera-Pérez, Cristian Rocha and Katherine Guerrero

J. Low Power Electron. Appl. 2020, 10(1), 3; https://doi.org/10.3390/jlpea10010003 - 8 Jan 2020

Cited by 5 | Viewed by 6888

Abstract

In this study, threshold voltage instability on commercial silicon carbide (SiC) power metal oxide semiconductor field electric transistor MOSFETs was evaluated using devices manufactured from two different manufacturers. The characterization process included PBTI (positive bias temperature instability) and pulsed IV measurements of devices [...] Read more.

In this study, threshold voltage instability on commercial silicon carbide (SiC) power metal oxide semiconductor field electric transistor MOSFETs was evaluated using devices manufactured from two different manufacturers. The characterization process included PBTI (positive bias temperature instability) and pulsed IV measurements of devices to determine electrical parameters’ degradations. This work proposes an experimental procedure to characterize silicon carbide (SiC) power MOSFETs following two characterization methods: (1) Using the one spot drop down (OSDD) measurement technique to assess the threshold voltage explains temperature dependence when used on devices while they are subjected to high temperatures and different gate voltage stresses. (2) Measurement data processing to obtain hysteresis characteristics variation and the damage effect over threshold voltage. Finally, based on the results, it was concluded that trapping charge does not cause damage on commercial devices due to reduced value of recovery voltage, when a negative small voltage is applied over a long stress time. The motivation of this research was to estimate the impact and importance of the bias temperature instability for the application fields of SiC power n-MOSFETs. The importance of this study lies in the identification of the aforementioned behavior where SiC power n-MOSFETs work together with complementary MOS (CMOS) circuits. Full article

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16 pages, 5588 KiB

Open AccessArticle

Temperature Compensation Circuit for ISFET Sensor

by Ahmed Gaddour, Wael Dghais, Belgacem Hamdi and Mounir Ben Ali

J. Low Power Electron. Appl. 2020, 10(1), 2; https://doi.org/10.3390/jlpea10010002 - 4 Jan 2020

Cited by 20 | Viewed by 7838

Abstract

PH measurements are widely used in agriculture, biomedical engineering, the food industry, environmental studies, etc. Several healthcare and biomedical research studies have reported that all aqueous samples have their pH tested at some point in their lifecycle for evaluation of the diagnosis of [...] Read more.

PH measurements are widely used in agriculture, biomedical engineering, the food industry, environmental studies, etc. Several healthcare and biomedical research studies have reported that all aqueous samples have their pH tested at some point in their lifecycle for evaluation of the diagnosis of diseases or susceptibility, wound healing, cellular internalization, etc. The ion-sensitive field effect transistor (ISFET) is capable of pH measurements. Such use of the ISFET has become popular, as it allows sensing, preprocessing, and computational circuitry to be encapsulated on a single chip, enabling miniaturization and portability. However, the extracted data from the sensor have been affected by the variation of the temperature. This paper presents a new integrated circuit that can enhance the immunity of ion-sensitive field effect transistors (ISFET) against the temperature. To achieve this purpose, the considered ISFET macro model is analyzed and validated with experimental data. Moreover, we investigate the temperature dependency on the voltage-current (I-V). Accordingly, an improved conditioning circuit is designed in order to reduce the temperature sensitivity on the measured pH values of the ISFET sensor. The numerical validation results show that the developed solution accurately compensates the temperature variation on the measured pH values at low power consumption. Full article

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17 pages, 5543 KiB

Open AccessArticle

Energy-Efficient Architecture for CNNs Inference on Heterogeneous FPGA

by Fanny Spagnolo, Stefania Perri, Fabio Frustaci and Pasquale Corsonello

J. Low Power Electron. Appl. 2020, 10(1), 1; https://doi.org/10.3390/jlpea10010001 - 24 Dec 2019

Cited by 17 | Viewed by 5958

Abstract

Due to the huge requirements in terms of both computational and memory capabilities, implementing energy-efficient and high-performance Convolutional Neural Networks (CNNs) by exploiting embedded systems still represents a major challenge for hardware designers. This paper presents the complete design of a heterogeneous embedded [...] Read more.

Due to the huge requirements in terms of both computational and memory capabilities, implementing energy-efficient and high-performance Convolutional Neural Networks (CNNs) by exploiting embedded systems still represents a major challenge for hardware designers. This paper presents the complete design of a heterogeneous embedded system realized by using a Field-Programmable Gate Array Systems-on-Chip (SoC) and suitable to accelerate the inference of Convolutional Neural Networks in power-constrained environments, such as those related to IoT applications. The proposed architecture is validated through its exploitation in large-scale CNNs on low-cost devices. The prototype realized on a Zynq XC7Z045 device achieves a power efficiency up to 135 Gops/W. When the VGG-16 model is inferred, a frame rate up to 11.8 fps is reached. Full article

(This article belongs to the Special Issue Low-Power FPGA Designs for Next-Generation Artificial Intelligence Applications)

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J. Low Power Electron. Appl., Volume 10, Issue 1 (March 2020) – 10 articles

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