Journal of Low Power Electronics and Applications

16 pages, 3082 KiB

Open AccessArticle

Surrogate Assisted Optimization for Low-Voltage Low-Power Circuit Design

by Amel Garbaya, Mouna Kotti, Mourad Fakhfakh and Esteban Tlelo-Cuautle

J. Low Power Electron. Appl. 2020, 10(2), 20; https://doi.org/10.3390/jlpea10020020 - 16 Jun 2020

Cited by 8 | Viewed by 3725

Low-voltage low-power (LVLP) circuit design and optimization is a hard and time-consuming task. In this study, we are interested in the application of the newly proposed meta-modelling technique to alleviate such burdens. Kriging-based surrogate models of circuits’ performances were constructed and then used [...] Read more.

Low-voltage low-power (LVLP) circuit design and optimization is a hard and time-consuming task. In this study, we are interested in the application of the newly proposed meta-modelling technique to alleviate such burdens. Kriging-based surrogate models of circuits’ performances were constructed and then used within a metaheuristic-based optimization kernel in order to maximize the circuits’ sizing. The JAYA algorithm was used for this purpose. Three topologies of CMOS current conveyors (CCII) were considered to showcase the proposed approach. The achieved performances were compared to those obtained using conventional LVLP circuit sizing techniques, and we show that our approach offers interesting results. Full article

(This article belongs to the Special Issue Low-Power CMOS Analog and Digital Circuits and Filters)

► Show Figures

Figure 1

8 pages, 667 KiB

Open AccessFeature PaperArticle

Idleness-Aware Dynamic Power Mode Selection on the i.MX 7ULP IoT Edge Processor

by Alfio Di Mauro, Hamed Fatemi, Jose Pineda de Gyvez and Luca Benini

J. Low Power Electron. Appl. 2020, 10(2), 19; https://doi.org/10.3390/jlpea10020019 - 5 Jun 2020

Cited by 3 | Viewed by 3913

Abstract

Power management is a crucial concern in micro-controller platforms for the Internet of Things (IoT) edge. Many applications present a variable and difficult to predict workload profile, usually driven by external inputs. The dynamic tuning of power consumption to the application requirements is [...] Read more.

Power management is a crucial concern in micro-controller platforms for the Internet of Things (IoT) edge. Many applications present a variable and difficult to predict workload profile, usually driven by external inputs. The dynamic tuning of power consumption to the application requirements is indeed a viable approach to save energy. In this paper, we propose the implementation of a power management strategy for a novel low-cost low-power heterogeneous dual-core SoC for IoT edge fabricated in 28 nm FD-SOI technology. Ss with more complex power management policies implemented on high-end application processors, we propose a power management strategy where the power mode is dynamically selected to ensure user-specified target idleness. We demonstrate that the dynamic power mode selection introduced by our power manager allows achieving more than 43% power consumption reduction with respect to static worst-case power mode selection, without any significant penalty in the performance of a running application. Full article

(This article belongs to the Special Issue Circuits and Systems Advances in Near Threshold Computing)

► Show Figures

Figure 1

15 pages, 6149 KiB

Open AccessArticle

Implementation of a Fractional-Order Electronically Reconfigurable Lung Impedance Emulator of the Human Respiratory Tree

by Elpida Kaskouta, Stavroula Kapoulea, Costas Psychalinos and Ahmed S. Elwakil

J. Low Power Electron. Appl. 2020, 10(2), 18; https://doi.org/10.3390/jlpea10020018 - 16 May 2020

Cited by 7 | Viewed by 4180

Abstract

The fractional-order lung impedance model of the human respiratory tree is implemented in this paper, using Operational Transconductance Amplifiers. The employment of such active element offers electronic adjustment of the impedance characteristics in terms of both elements values and orders. As the MOS [...] Read more.

The fractional-order lung impedance model of the human respiratory tree is implemented in this paper, using Operational Transconductance Amplifiers. The employment of such active element offers electronic adjustment of the impedance characteristics in terms of both elements values and orders. As the MOS transistors in OTAs are biased in the weak inversion region, the power dissipation and the dc bias voltage of operation are also minimized. In addition, the partial fraction expansion tool has been utilized, in order to achieve reduction of the spread of the required time-constants and scaling factors. The performance of the proposed scheme has been evaluated, at post-layout level, using MOS transistors models provided by the 0.35

μ

m Austria Mikro Systeme technology CMOS process, and the Cadence IC design suite. Full article

(This article belongs to the Special Issue Low-Power CMOS Analog and Digital Circuits and Filters)

► Show Figures

Figure 1

8 pages, 1464 KiB

Open AccessBrief Report

Evidence of Limitations of the Transconductance-to-Drain-Current Method (g_m/I_d) for Transistor Sizing in 28 nm UTBB FD-SOI Transistors

by Leonardo Barboni

J. Low Power Electron. Appl. 2020, 10(2), 17; https://doi.org/10.3390/jlpea10020017 - 15 May 2020

Cited by 4 | Viewed by 4167

Abstract

The transconductance-to-drain-current method is a transistor sizing methodology that is commonly used in CMOS technology. In this study, we explored by means of simulations, a case of study and three figures of merit used for the method, and we conclude for the first [...] Read more.

The transconductance-to-drain-current method is a transistor sizing methodology that is commonly used in CMOS technology. In this study, we explored by means of simulations, a case of study and three figures of merit used for the method, and we conclude for the first time that the method should be reformulated. The study has been performed on Ultra-Thin Body and Buried Fully Depleted Silicon-On-Insulator 28 nm low-voltage-threshold NFET commercial technology (UTBB FD-SOI), and the simulations were performed via Spectre Circuit Simulator, by using the device model-card. To our knowledge, no previous attempts have been made to assess the method capability, and we collected very important results that infer that the method should be reformulated or considered incomplete for use with this technology, which has an impact and ramifications on the field of process modeling, simulation and circuit design. Full article

► Show Figures

Figure 1

23 pages, 12524 KiB

Open AccessFeature PaperReview

Near-Threshold Voltage Design Techniques for Heterogenous Manycore System-on-Chips

by Sriram Vangal, Somnath Paul, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, James Tschanz and Vivek De

J. Low Power Electron. Appl. 2020, 10(2), 16; https://doi.org/10.3390/jlpea10020016 - 14 May 2020

Cited by 5 | Viewed by 5712

Abstract

Aggressive power supply scaling into the near-threshold voltage (NTV) region holds great potential for applications with strict energy budgets, since the energy efficiency peaks as the supply voltage approaches the threshold voltage (V_T) of the CMOS transistors. The improved silicon energy [...] Read more.

Aggressive power supply scaling into the near-threshold voltage (NTV) region holds great potential for applications with strict energy budgets, since the energy efficiency peaks as the supply voltage approaches the threshold voltage (V_T) of the CMOS transistors. The improved silicon energy efficiency promises to fit more cores in a given power envelope. As a result, many-core Near-threshold computing (NTC) has emerged as an attractive paradigm. Realizing energy-efficient heterogenous system on chips (SoCs) necessitates key NTV-optimized ingredients, recipes and IP blocks; including CPUs, graphic vector engines, interconnect fabrics and mm-scale microcontroller (MCU) designs. We discuss application of NTV design techniques, necessary for reliable operation over a wide supply voltage range—from nominal down to the NTV regime, and for a variety of IPs. Evaluation results spanning Intel’s 32-, 22- and 14-nm CMOS technologies across four test chips are presented, confirming substantial energy benefits that scale well with Moore’s law. Full article

(This article belongs to the Special Issue Circuits and Systems Advances in Near Threshold Computing)

► Show Figures

Figure 1

15 pages, 4480 KiB

Open AccessArticle

An Autonomous Low-Power LoRa-Based Flood-Monitoring System

by Mattia Ragnoli, Gianluca Barile, Alfiero Leoni, Giuseppe Ferri and Vincenzo Stornelli

J. Low Power Electron. Appl. 2020, 10(2), 15; https://doi.org/10.3390/jlpea10020015 - 10 May 2020

Cited by 33 | Viewed by 8850

Abstract

The development of Internet of Things (IoT) systems is a rapidly evolving scenario, thanks also to newly available low-power wide area network (LPWAN) technologies that are utilized for environmental monitoring purposes and to prevent potentially dangerous situations with smaller and less expensive physical [...] Read more.

The development of Internet of Things (IoT) systems is a rapidly evolving scenario, thanks also to newly available low-power wide area network (LPWAN) technologies that are utilized for environmental monitoring purposes and to prevent potentially dangerous situations with smaller and less expensive physical structures. This paper presents the design, implementation and test results of a flood-monitoring system based on LoRa technology, tested in a real-world scenario. The entire system is designed in a modular perspective, in order to have the capability to interface different types of sensors without the need for making significant hardware changes to the proposed node architecture. The information is stored through a device equipped with sensors and a microcontroller, connected to a LoRa wireless module for sending data, which are then processed and stored through a web structure where the alarm function is implemented in case of flooding. Full article

► Show Figures

Figure 1

16 pages, 9874 KiB

Open AccessArticle

Low-Power Embedded System for Gait Classification Using Neural Networks

by Francisco Luna-Perejón, Manuel Domínguez-Morales, Daniel Gutiérrez-Galán and Antón Civit-Balcells

J. Low Power Electron. Appl. 2020, 10(2), 14; https://doi.org/10.3390/jlpea10020014 - 1 May 2020

Cited by 15 | Viewed by 4899

Abstract

Abnormal foot postures can be measured during the march by plantar pressures in both dynamic and static conditions. These detections may prevent possible injuries to the lower limbs like fractures, ankle sprain or plantar fasciitis. This information can be obtained by an embedded [...] Read more.

Abnormal foot postures can be measured during the march by plantar pressures in both dynamic and static conditions. These detections may prevent possible injuries to the lower limbs like fractures, ankle sprain or plantar fasciitis. This information can be obtained by an embedded instrumented insole with pressure sensors and a low-power microcontroller. However, these sensors are placed in sparse locations inside the insole, so it is not easy to correlate manually its values with the gait type; that is why a machine learning system is needed. In this work, we analyse the feasibility of integrating a machine learning classifier inside a low-power embedded system in order to obtain information from the user’s gait in real-time and prevent future injuries. Moreover, we analyse the execution times, the power consumption and the model effectiveness. The machine learning classifier is trained using an acquired dataset of 3000+ steps from 6 different users. Results prove that this system provides an accuracy over 99% and the power consumption tests obtains a battery autonomy over 25 days. Full article

(This article belongs to the Special Issue Circuits and Systems Advances in Near Threshold Computing)

► Show Figures

Graphical abstract

13 pages, 3858 KiB

Open AccessArticle

A Chopper Stabilization Audio Instrumentation Amplifier for IoT Applications

by Jamel Nebhen, Pietro M. Ferreira and Sofiene Mansouri

J. Low Power Electron. Appl. 2020, 10(2), 13; https://doi.org/10.3390/jlpea10020013 - 16 Apr 2020

Cited by 9 | Viewed by 5443

Abstract

A low-noise instrumentation amplifier dedicated to a nano- and micro-electro-mechanical system (M&NEMS) microphone for the use in Internet of Things (IoT) applications is presented. The piezoresistive sensor and the electronic interface are respectively, silicon nanowires and an instrumentation amplifier. To design an instrumentation [...] Read more.

A low-noise instrumentation amplifier dedicated to a nano- and micro-electro-mechanical system (M&NEMS) microphone for the use in Internet of Things (IoT) applications is presented. The piezoresistive sensor and the electronic interface are respectively, silicon nanowires and an instrumentation amplifier. To design an instrumentation amplifier for IoT applications, different trade-offs are discussed like power consumption, gain, noise and sensitivity. Because the most critical noisy block is the amplifier, a delay-time chopper stabilization (CHS) technique is implemented around it to eliminate its offset and 1/f noise. The low-noise instrumentation amplifier is implemented in a 65-nm CMOS (Complementary metal–oxide–semiconductor) technology. The supply voltage is 2.5 V while the power consumption is 0.4 mW and the core area is 1 mm². The circuit of the M&NEMS microphone and the amplifier was fabricated and measured. From measurement results over a signal bandwidth of 20 kHz, it achieves a signal-to-noise ratio (SNR) of 77 dB. Full article

► Show Figures

Figure 1

16 pages, 4144 KiB

Open AccessArticle

Electronic Tuning Square-Wave Generators with Improved Linearity Using Operational Transresistance Amplifier

by Pittala Chandra Shaker and Avireni Srinivasulu

J. Low Power Electron. Appl. 2020, 10(2), 12; https://doi.org/10.3390/jlpea10020012 - 14 Apr 2020

Cited by 1 | Viewed by 5535

Abstract

Two new electronic tuning current-mode square-wave generators are introduced in the ensuing paper. In the first proposed square-wave generator circuit, one Operational Trans-resistance Amplifier (OTRA) and two passive components are involved, along with two NMOS depletion mode transistors. This circuit generates a square-wave [...] Read more.

Two new electronic tuning current-mode square-wave generators are introduced in the ensuing paper. In the first proposed square-wave generator circuit, one Operational Trans-resistance Amplifier (OTRA) and two passive components are involved, along with two NMOS depletion mode transistors. This circuit generates a square-wave with almost equal and fixed duty cycles. The second proposed circuit is able to control both on-duty and off-duty cycles independently with the help of two passive components, two NMOS depletion mode transistors, and two diodes connected to the circuit. The frequency of the proposed circuits can be adjusted with the passive components connected to the circuit. Moreover, electronic tuning can also be achieved with the proposed circuits. The measured results that are included in the paper show the linear variation of a time period as compared with existing OTRA based square waveform generator. The performance of the proposed circuits is examined while using SPICE models. These circuits are built on a laboratory breadboard using commercially available Current Feedback Operational Amplifier (AD844 AN) and passive components are connected externally and tested for square waveform generation. The obtained results demonstrate good agreement with the theoretical values. Full article

(This article belongs to the Special Issue Advanced Researches in Wireless Communication and Wireless Power Transfer)

► Show Figures

Figure 1

11 pages, 2817 KiB

Open AccessArticle

Rectifiers’ Design and Optimization for a Dual-Channel RF Energy Harvester

by Davide Colaiuda, Iolanda Ulisse and Giuseppe Ferri

J. Low Power Electron. Appl. 2020, 10(2), 11; https://doi.org/10.3390/jlpea10020011 - 4 Apr 2020

Cited by 18 | Viewed by 6162

Abstract

This paper presents the design and implementation of two front-ends for RF (Radio Frequency) energy harvesting, comparing them with the commercial one—P2110 by Powercast Co. (Pittsburgh, PA, USA) Both devices are implemented on a discrete element board with microstrip lines combined with lumped [...] Read more.

This paper presents the design and implementation of two front-ends for RF (Radio Frequency) energy harvesting, comparing them with the commercial one—P2110 by Powercast Co. (Pittsburgh, PA, USA) Both devices are implemented on a discrete element board with microstrip lines combined with lumped elements and are optimized for two different input power levels (−10 dBm and 10 dBm, respectively), at the GSM900 frequencies. The load has been fixed at 5kΩ, after a load-pull analysis on systems. The rectifiers stages implement two different Schottky diodes in two different topologies: a single diode and a 2-stage Dickson’s charge pump. The second one is compared with the P2110 by generating RF fields at 915 MHz with the Powercast Powerspot. The main aim of this work is to design simple and efficient low-cost devices, which can be used as a power supply for low-power autonomous sensors, with better performances than the current solutions of state-of-the-art equipment, providing an acceptable voltage level on the load. Measurements have been conducted for input power range −20 dBm up to 10 dBm; the best power conversion efficiency (PCE) is obtained with the second design, which reaches a value of 70% at 915 MHz. In particular, the proposed device exhibited better performance compared to the P2110 commercial device, allowing a maximum distance of operation of up to 22 meters from the dedicated RF power source, making it suitable even for IoT (Internet of Things) applications. Full article

(This article belongs to the Special Issue Low-Power RF Energy Harvesting for IoT Devices)

► Show Figures

Figure 1

Journal Menu

Journal Browser

J. Low Power Electron. Appl., Volume 10, Issue 2 (June 2020) – 10 articles

Further Information

Guidelines

MDPI Initiatives

Follow MDPI