A High-Gain CNTFET-Based LNA Developed Using a Compact Design-Oriented Device Model

Abstract

Recently, carbon nanotube field-effect transistors (CNTFETs) have attracted wide attention as promising candidates for components in the next generation of electronic devices. In particular CNTFET-based RF devices and circuits show superior performance to those built with silicon FETs since they are able to obtain higher power-gain and cut-off frequency at lower power dissipation. The aim of this paper is to present a compact, design-oriented model of CNTFETs that is able to ease the development of a complete amplifier. As a case study, the detailed design of a high-gain CNTFET-based broadband inductorless LNA is presented.

1. Introduction

Carbon nanotube field-effect transistors (CNTFETs) have demonstrated the ability to be suitable for mixed-signal and RF application, with respect to both conventional bulk semiconductors and 2-D materials, such as graphene [1,2,3,4,5,6]. This is due to the fact that the 1-D transport in carbon nanotubes (CNTs) leads not only to a low scattering rate and high current-carrying capability but also to a linear $I_D$ vs. $V_{GS}$ transcharacteristic under some conditions [7,8,9]. This I–V behavior could be considered an advantage in future mobile communication systems where increasingly complex modulation techniques are expected to be used [10].

In particular, RF systems performance mainly depends on their frontend circuit components, such as the low-noise amplifier (LNA), high power amplifier (HPA), single-pole-double-throw (SPDT) switch, oscillator, and mixer. The design of these building blocks is usually implemented through circuit simulators that use compact models representing the actual devices of a given technology. Thus, the need for compact models is of paramount importance for analog RF design where the requirements are quite stringent since the models must accurately describe typically nonlinear devices over a wide range of frequencies, biases, and temperatures.

On the one hand, the device model should be sophisticated enough to take into account the device behavior in different working regions. In particular, the design of RF frontends, including LNAs and HPAs, requires the accurate prediction of (i) the small-signal behavior (that must also include noise) for which the first derivative of the currents and charges with respect to terminal voltages must be correctly modeled, and (ii) large-signal time-domain behavior (along with phase noise) and nonlinear distortion for which an accurate modeling of currents and charges up to at least the fifth-order derivatives is needed.

On the other hand, the device model should be compact and simple enough in order to allow reasonable circuit simulation times. As a consequence, the physical relationships describing the device behavior must be as simple as possible, e.g., distributed regions of the device have to be represented by lumped elements, and complicated physical effects have to be expressed through simple and explicit analytical solutions [11,12].

Several models have been proposed in the literature that try to approximate the real behavior of the CNTFET device, maintaining their mathematical and computational complexity as low as possible [13,14,15,16,17,18,19,20,21].

The goal of this paper is to develop a compact and design-oriented device model that is able to describe the device behavior with sufficient details so as to ease the implementation of the main RF building blocks, such as LNA, HPA, and SPDT switch.

Nowadays, the increasing demand for wireless communication systems for broadband, multi-band, and multi-standard receivers makes the bandwidth a critical issue in the design of LNAs [22,23,24,25,26,27,28]. Large bandwidth systems exhibit desirable advantages, such as large transmission channel capacity, less multipath fading effect, and easier material penetration. As the first stage of a receiver system, the LNA should have very low noise and provide reasonable voltage gain over the wide band of interest so that the total noise of the receiving chain can be suppressed. In addition, wideband input matching and high linearity also need to be guaranteed. Furthermore, low power consumption and small die area can increase the battery life and decrease the chip cost [29].

Usually, voltage-mode LNAs have many drawbacks, such as limited bandwidth, the need for a high supply and the requirement of a current-to-voltage conversion stage due to the existence of high-impedance nodes. Current-mode LNAs have many intrinsic advantages over voltage-mode counterparts, including low supply voltage requirements, wide bandwidth, tunable input impedances, and high slew rates. In recent years, several articles about current-mode wideband LNAs in standard CMOS technology have been reported [28,30,31,32,33,34,35,36].

According to the input matching and noise characteristics of the circuit, LNA has two typical architectures, common source (CS) and common gate (CG) topology. The wideband input matching is provided by the CG topology, but it has a high noise figure (NF) [28]. In the CG LNA topology, most input and/or output matching is achieved by employing inductors and capacitors to achieve broadband matching, which greatly increases the chip area and cost. The advantage of CS topology can get higher gain, but compromises need to be made between gain and broadband input matching. In order to reduce the contradiction between the gain of CS topology and the input matching bandwidth, a resistive feedback technique is usually used to obtain considerable gain and wideband input matching.

With these considerations in mind, we chose to apply our previously developed compact CNTFET model [37] to the design of a cascode LNA. The model was derived from electromagnetic and quantistic simulations that are supposed to mimic the actual technology that will be used for circuit manufacturing, and although it has not yet been validated experimentally, it should be a good starting point to estimate the performance this technology could achieve. The cascode architecture was chosen because it combines the high gain and low NF of a CS topology with the higher operating frequencies of the CG topology and is thus of interest in RF applications.

This paper is organized as follows. In Section 2, the extrinsic CNTFET model comprising noise sources is presented. In Section 3, the simplified DC CNTFET model is described. In Section 4, the proposed device model was applied to the design flow of an LNA. Section 5 reports some simulation results and comparisons. Finally, Section 6 concludes this work.

2. CNTFET Extrinsic Noise Model

As a first step to designing a low-noise amplifier, a suitable model of the noise sources within the employed active devices is necessary. We assume that noise can be modeled by adding stochastic current sources in parallel to the main small-signal elements of the standard FET equivalent circuit and to the contact resistances [25], as shown in Figure 1, which is valid in the saturation region of the transistor.

Here, $g_{\mathrm{m}}$ and $g_{\mathrm{o}}$ are the intrinsic FET transconductance and output conductance, respectively, $R_{\mathrm{d}}$ and $R_{\mathrm{s}}$ represent the channel resistance at the drain and source terminals, respectively, while $C_{\mathrm{gs}}$ and $C_{\mathrm{gd}}$ model the capacitive effects of the gate.

The noise sources $\overline{i_{\mathrm{n},x}^2}$, where x can denote the noise associated with the source (Rs), drain (Rd) or the intrinsic device (int), can be assumed to have a power spectral density proportional to the transistor drain current $I_{\mathrm{D}}$:

$$\overline{i_{\mathrm{n},x}^2}=2q{I}_{\mathrm{D}}{F}_x$$

(1)

where q is the elementary charge and $F_x$ is the appropriate Fano factor. According to [25], it is common to assume $F_{\mathrm{Rs}}=F_{\mathrm{Rd}}=0.3$ if the contact resistances are mostly due to the doped nanotube extensions, while $F_{\mathrm{int}}$ might depend both on technological details of the nanotubes and transistor bias. However, from [38], $F_{\mathrm{int}}$ can be assumed to be almost constant and smaller than 0.1 for a wide range of typical bias currents. For simplicity, we will conservatively assume $F_{\mathrm{int}}=0.1$ in our simulations.

From that, we aim to derive a simplified extrinsic model composed of just the transconductance element, the output conductance, and a single noise current source, all in parallel. From a rapid inspection of the equivalent circuit reported in Figure 1, the extrinsic transconductance $g_{\mathrm{m}}^{*}$ can be expressed as:

$$g_{\mathrm{m}}^{*}=\frac{g_{\mathrm{m}}}{1+g_{\mathrm{m}}·R_{\mathrm{s}}}$$

(2)

and the extrinsic output conductance $g_{\mathrm{o}}^{*}$ can also be expressed as:

$$g_{\mathrm{o}}^{*}=\frac{g_{\mathrm{o}}}{1+g_{\mathrm{m}}·R_{\mathrm{s}}+g_{\mathrm{o}}·(R_{\mathrm{s}}+R_{\mathrm{d}})}$$

(3)

where obviously both of them can be approximated by $g_{\mathrm{m}}$ and $g_{\mathrm{o}}$, respectively, when the contact resistances $R_{\mathrm{s}}$ and $R_{\mathrm{d}}$ are vanishing.

The total noise density $\overline{i_{\mathrm{n},\mathrm{TOT}}^2}$ in the saturation region can be calculated as below:

$$\begin{array}{c}\hfill \overline{i_{\mathrm{n},\mathrm{TOT}}^2}={\left[{\displaystyle \frac{(g_{\mathrm{m}}+g_{\mathrm{o}})·R_{\mathrm{s}}}{1+g_{\mathrm{m}}·R_{\mathrm{s}}+g_{\mathrm{o}}·(R_{\mathrm{s}}+R_{\mathrm{d}})}}\right]}^2·\overline{i_{\mathrm{n},\mathrm{Rs}}^2}+{\left[{\displaystyle \frac{1}{1+g_{\mathrm{m}}·R_{\mathrm{s}}+g_{\mathrm{o}}·(R_{\mathrm{s}}+R_{\mathrm{d}})}}\right]}^2·\overline{i_{\mathrm{n},\mathrm{int}}^2}\\ \hfill +{\left[{\displaystyle \frac{g_{\mathrm{o}}·R_{\mathrm{d}}}{1+g_{\mathrm{m}}·R_{\mathrm{s}}+g_{\mathrm{o}}·(R_{\mathrm{s}}+R_{\mathrm{d}})}}\right]}^2·\overline{i_{\mathrm{n},\mathrm{Rd}}^2}\end{array}$$

(4)

which is in parallel to the equivalent output conductance $g_{\mathrm{o}}^{*}$.

For completeness, the CNTFET simplified extrinsic model with noise sources in the triode region can be derived similarly. The small-signal equivalent circuit is reported in Figure 2, and the total noise in the triode region can be calculated as below:

$$\overline{i_{\mathrm{n},\mathrm{TOT}}^2}={\left[\frac{R_{\mathrm{s}}}{R_{\mathrm{s}}+R_{\mathrm{ds}}+R_{\mathrm{d}}}\right]}^2·\overline{i_{\mathrm{n},\mathrm{Rs}}^2}+{\left[\frac{R_{\mathrm{ds}}}{R_{\mathrm{s}}+R_{\mathrm{ds}}+R_{\mathrm{d}}}\right]}^2·\overline{i_{\mathrm{n},\mathrm{int}}^2}+{\left[\frac{R_{\mathrm{d}}}{R_{\mathrm{s}}+R_{\mathrm{ds}}+R_{\mathrm{d}}}\right]}^2·\overline{i_{\mathrm{n},\mathrm{Rd}}^2}$$

(5)

where $R_{\mathrm{ds}}$ is the on-state resistance of the transistor in the triode region.

Having derived this simplified extrinsic model, in the following, we will always refer to the extrinsic parameters when talking about $g_{\mathrm{m}}$ and $g_{\mathrm{o}}$, without encumbering the notation with the asterisk ($g^{*}$) symbol.

3. DC CNTFET Simplified Model

In order to simplify the design process of the amplifier, a compact, designer-friendly model of the behavior of the drain current in a CNTFET that is suitable for estimating operating points can also be useful.

To develop such a model, it is important to understand the differences in behavior between a conventional MOSFET and a CNTFET of the type analyzed in [37], which, unlike many other studied structures, exhibits a drain current relationship with respect to biasing voltages that is almost exactly a separable function of the gate and drain voltages. This can be seen in Figure 3, which shows the input and output characteristics on a normalized vertical axis (i.e., individual current curves had been divided by their mean value).

For what regards the input characteristics, it can be seen that the drain current is almost linearly dependent on the gate overdrive voltage above the threshold voltage and that the curve shape does not depend at all on drain voltage. On the other hand, for what concerns the CNTFET output characteristics, there is a very weak, and negligible, dependence of their shape on the gate voltage, but unlike conventional MOSFETs, the saturation region, where the characteristic becomes almost linear, can be assumed to start from a fixed voltage that it is not bound to the gate overdrive voltage, thus allowing a great simplification of both the empirical model and of the design procedure.

It is thus reasonable to employ a simple empirical model with separated variables, such as:

$$I_{\mathrm{D}}=g_{\mathrm{m}}{f}_{\mathrm{G}}(V_{\mathrm{GS}}-V_{\mathrm{TH}})f_{\mathrm{D}}(V_{\mathrm{DS}}/V_{\mathrm{p}})(1+\lambda V_{\mathrm{DS}})$$

(6)

where $f_{\mathrm{G}}$ should mimic the shape on the left panel of Figure 3, and $f_{\mathrm{D}}$ that on the right panel.

If maximum simplicity is sought, and the circuit only operates well above threshold, a simple, piecewise linear model for $f_{\mathrm{G}}$ might suffice, such as:

$$f_{\mathrm{G}}\left(v\right)=min(0,v)$$

(7)

otherwise, a slightly more smoothed version can better approximate sub-threshold and near-threshold behavior:

$$f_{\mathrm{G}}\left(v\right)=\left\{\begin{array}{cc}{V}_{\sigma }log\left(1+exp\left(\frac{v}{V_{\sigma }}\right)\right)\hfill & v>0\hfill \\ V_{\sigma }log\left(1+exp\left(\frac{v}{k{V}_{\sigma }}\right)\right)\hfill & v<0\hfill \end{array}\right.$$

(8)

where $V_{\sigma }$ is a parameter that determines the width of the smoothed transition region, and k is a parameter that can be used to adjust the sub-threshold transconductance. It can be noted that Equation (7) is the limit of Equation (8) as $V_{\sigma }\to 0$, and that $\partial f_{\mathrm{G}}{\left(v\right)/\partial v|}_{v\gg 0}=1$ so that $g_{\mathrm{m}}$ retains its normal meaning.

On the other hand, $f_{\mathrm{D}}\left(x\right)$ can be assumed as a saturating power function to describe the dependence on $V_{\mathrm{DS}}$, such as:

$$f_{\mathrm{D}}\left(x\right)=\left\{\begin{array}{cc}(nx-x^n)/(n-1)& 0<x\le 1\\ \\ 1& x>1\end{array}\right.$$

(9)

which satisfies the properties $\forall n\ne 1$, $f_{\mathrm{D}}\left(0\right)=0$, $f_{\mathrm{D}}\left(1\right)=1$, $\partial f_{\mathrm{D}}{\left(x\right)/\partial x|}_{x=1}=0$.

We thus have a total of seven fitting parameters: $g_{\mathrm{m}}$ and $V_{\mathrm{TH}}$ are the slope and threshold voltage of the input characteristics, respectively, while $V_{\sigma }$ controls the near-threshold behavior and k the sub-threshold transconductance. For the output characteristics, $V_{\mathrm{p}}$ is the equivalent of the “pinch-off” voltage that denotes the starting of the saturation region, $\lambda$ defines the output resistance ($g_{\mathrm{o}}\simeq \lambda I_{\mathrm{D}}$), and the exponent n controls the “steepness” of the transition between the triode and saturation regions.

These parameters can be fitted to match the simplified model to the full-fledged simulation, as shown in Figure 4 for a $W=1$ μm CNTFET (100 nanotubes).

4. LNA Design

The above model was applied to the design of an LNA. The architecture we chose is based on the widely-adopted cascode configuration since it can provide a good noise figure, modified by replacing the common-gate stage with a gm-boosting architecture. The schematic is shown in Figure 5.

The gm-boosting effect is provided by the secondary amplifier composed of $M_2$ and $M_3$. Together, they actively provide the gate voltage to the common-gate stage $M_1$ so that its source is kept at a nearly constant voltage. This architecture indeed provides a much lower input impedance than a simple transistor, and that essentially cancels the Miller effect on the drain-gate capacitance of $M_5$, enlarging the operational frequency of the amplifier.

By simple circuit inspection, it is possible to compute that the resistance seen from the drain of $M_5$ is indeed (neglecting the output conductance of $M_1$):

$$R_{\mathrm{GB}}\simeq \frac{1}{g_{\mathrm{m}1}}\frac{1}{1+|A_{\mathrm{v}2}|}$$

(10)

where $A_{\mathrm{v}2}$ is the gain of the secondary amplifier.

$$A_{\mathrm{v}2}=\frac{-g_{\mathrm{m}2}}{g_{\mathrm{o}2}+g_{\mathrm{o}3}}\simeq \frac{-1}{2\lambda (V_{\mathrm{G}2}-V_{\mathrm{TH}})}$$

(11)

so that the voltage gain of the first stage ($M_5$) is very low:

$$A_{\mathrm{v}1}=-g_{\mathrm{m}5}{R}_{\mathrm{GB}}\simeq -\frac{g_{\mathrm{m}5}}{g_{\mathrm{m}1}}\frac{1}{1+|A_{\mathrm{v}2}|}$$

(12)

and $|A_{\mathrm{v}1}|\ll 1$ provided that $g_{\mathrm{m}5}$ and $g_{\mathrm{m}1}$ are comparable (as they should be) being the two transistors $M_5$ and $M_1$ biased with the same current. This way, the input capacitance of the amplifier reduces to:

$$C_{\mathrm{in}}=C_{\mathsf{g}\mathsf{s}5}+C_{\mathsf{g}\mathsf{d}5}(1-A_{\mathrm{v}1})\simeq C_{\mathsf{g}\mathsf{s}5}+C_{\mathsf{g}\mathsf{d}5}$$

(13)

instead of $C_{\mathsf{g}\mathsf{s}5}+C_{\mathsf{g}\mathsf{d}5}(1+g_{\mathrm{m}5}/g_{\mathrm{m}1})$ we would have had without the gm-boosting stage.

Back to the complete amplifier, its gain can be computed with reference to its small-signal equivalent circuit shown in Figure 6. There, for notational simplicity, we imply that $g_{\mathrm{o}4}$ also includes the output load conductance (and so will be much higher than the output conductances of the other transistors).

The overall voltage gain is then:

$$A_{\mathrm{v}}=-\frac{g_{\mathrm{m}5}·\left[g_{\mathrm{o}1}(g_{\mathrm{o}2}+g_{\mathrm{o}3})+g_{\mathrm{m}1}(g_{\mathrm{m}2}+g_{\mathrm{o}2}+g_{\mathrm{o}3})\right]}{(g_{\mathrm{o}1}·g_{\mathrm{o}5}+g_{\mathrm{o}4}·g_{\mathrm{o}5}+g_{\mathrm{o}1}·g_{\mathrm{o}4})·(g_{\mathrm{o}2}+g_{\mathrm{o}3})+g_{\mathrm{m}1}·g_{\mathrm{o}4}·(g_{\mathrm{m}2}+g_{\mathrm{o}2}+g_{\mathrm{o}3})}$$

(14)

and, considering the output conductances to be negligible with respect to transconductances, the voltage gain simplifies as follows:

$$A_{\mathrm{v}}\simeq -\frac{g_{\mathrm{m}5}}{g_{\mathrm{o}4}}$$

(15)

4.1. Amplifier Noise Evaluation

Considering all the CNTFET noise contributions, we have the following equations:

$$(g_{\mathrm{o}2}+g_{\mathrm{o}3})·v_{\mathrm{y}}=-g_{\mathrm{m}2}·v_{\mathrm{x}}-i_{\mathrm{n}2}-i_{\mathrm{n}3}$$

(16)

$$g_{\mathrm{o}4}·v_{\mathrm{out}}+i_{\mathrm{n}4}=-g_{\mathrm{m}1}·(v_{\mathrm{y}}-v_{\mathrm{x}})-g_{\mathrm{o}1}·(v_{\mathrm{out}}-v_{\mathrm{x}})-i_{\mathrm{n}1}$$

(17)

$$g_{\mathrm{o}5}·v_{\mathrm{x}}+i_{\mathrm{n}5}=-g_{\mathrm{o}4}·v_{\mathrm{out}}-i_{\mathrm{n}4}$$

(18)

where $v_{\mathrm{x}}$ and $v_{\mathrm{y}}$ are the voltages at the nodes X and Y of the equivalent circuit Figure 6, respectively.

By solving (16)–(18) and considering the output conductances $g_{\mathrm{o}1}$, $g_{\mathrm{o}2}$, $g_{\mathrm{o}3}$, $g_{\mathrm{o}5}$ vanishing with respect to the CNTFET transconductances $g_{\mathrm{m}}$, the five CNTFET noise contributions to the output voltage $v_{\mathrm{out}}$ result in:

$$v_{\mathrm{out}}^{\left(\mathrm{n}\right)}\simeq -\frac{(g_{\mathrm{o}2}+g_{\mathrm{o}3})·g_{\mathrm{o}5}}{g_{\mathrm{m}1}·g_{\mathrm{m}2}·g_{\mathrm{o}4}}·i_{\mathrm{n}1}+\frac{g_{\mathrm{o}5}}{g_{\mathrm{m}2}·g_{\mathrm{o}4}}·i_{\mathrm{n}2}+\frac{g_{\mathrm{o}5}}{g_{\mathrm{m}2}·g_{\mathrm{o}4}}·i_{\mathrm{n}3}-\frac{1}{g_{\mathrm{o}4}}·i_{\mathrm{n}4}-\frac{1}{g_{\mathrm{o}4}}·i_{\mathrm{n}5}$$

(19)

4.2. DC Bias Design Procedure and Optimization

Due to the separability property of the functional dependence of the drain current with respect to the gate and drain voltages, biasing of the circuit is quite straightforward, and the overall small-signal gain only depends on the input transistor and load, as shown in (15).

Nevertheless, the noise performance is indeed influenced by the bias currents and voltages, and so the design can be tailored to optimize such a performance.

In particular, from Equation (19), it is apparent that only $M_4$ and $M_5$ make a significant contribution to the output noise, with their noise currents directly flowing into the output conductance ($g_{\mathrm{o}4}$). Since the equivalent noise current power spectral density $\overline{i_{\mathrm{n}}^2}$ of a single transistor is proportional to its drain current:

$$\overline{i_{\mathrm{n}}^2}\propto I_{\mathrm{D}}$$

(20)

while its transconductance $g_{\mathrm{m}}$ also depends on gate biasing:

$$g_{\mathrm{m}}\simeq \frac{I_{\mathrm{D}}}{V_{\mathrm{GS}}-V_{\mathrm{TH}}}$$

(21)

it is possible to optimize $M_5$ for noise performance by maximizing its $g_{\mathrm{m}}$, while nothing, unfortunately, can be done for the noise added by $M_4$.

The noise factor of the input stage, a CS configuration, can thus be computed as:

$$F=\frac{S_{\mathrm{i}}/N_{\mathrm{i}}}{S_{\mathrm{o}}/N_{\mathrm{o}}}=\frac{\overline{v_{\mathrm{i}}^2}/\overline{v_{\mathrm{n}}^2}}{\overline{g_{\mathrm{m}}^2{v}_{\mathrm{i}}^2}/(\overline{g_{\mathrm{m}}^2{v}_{\mathrm{n}}^2}+\overline{i_{\mathrm{n}}^2})}=1+\frac{\overline{i_{\mathrm{n}}^2}}{g_{\mathrm{m}}^2\overline{v_{\mathrm{n}}^2}}$$

(22)

where $S_{\mathrm{i}}$ and $S_{\mathrm{o}}$ are the power spectral densities of the input voltage signal ($v_{\mathrm{i}}$) and output current signal ($g_{\mathrm{m}}{v}_{\mathrm{i}}$), respectively, and similarly $N_{\mathrm{i}}$ and $N_{\mathrm{o}}$ for the input noise ($v_{\mathrm{n}}$) and added output noise ($i_{\mathrm{n}}$). Due to Equations (20) and (21), the above Equation (22) becomes:

$$F-1\propto \frac{{(V_{\mathrm{GS}}-V_{\mathrm{TH}})}^2}{I_{\mathrm{D}}}$$

(23)

so that it is best to bias the transistor with the lowest possible overdrive voltage, provided that sufficient linearity is retained. Of course, this implies a trade-off with bandwidth, as lower overdrive voltages require larger transistors to sustain the desired drain current.

With these considerations in mind, it is possible to proceed with the design optimization after having defined a few constraints that are needed on the node voltages to ensure all transistors are biased in their saturation region. To aid optimization, normalized node voltages are used, i.e., if a node n must have a voltage $V_n$ constrained so that $V_{\mathrm{L}n}<V_n<V_{\mathrm{H}n}$, then we pose $x_n=(V_n-V_{\mathrm{L}n})/(V_{\mathrm{H}n}-V_{\mathrm{L}n})$, and the optimizer can (theoretically) explore the whole unitary hypercube $0\le x_n\le 1$.

To do so, the currents in the left and right branches, $I_1$ and $I_2$, respectively, must also be fixed, but those are usually determined by system-level considerations on the maximum power dissipation of the device. From a noise perspective, the higher the currents, the better. We thus chose to use $I_1$ = 7 mA and $I_2$ = 2 mA, since the right branch transistors do not contribute much to the total noise of the LNA.

To minimize noise, from Equation (23), $V_{\mathrm{G}5}$ should be as low as possible, which also has the effect of maximizing the transistor $M_5$ transconductance and hence the gain of the whole amplifier. We thus fixed $x_{\mathrm{G}5}=0.1$ to allow for some signal excursion without losing linearity. The other transistors can be designed to keep their total size as small as possible, aiding in the frequency response. Since $g_{\mathrm{m}}\propto W$, transistors widths W can easily be computed from Equation (21) once the currents and voltages are known, and so a numeric optimizer can be employed. Minimization of the total gate area of the amplifier thus leads to the results shown in

Table 1. LNA biasing constraints and optimized values. $V_{\mathrm{L}n}$ is the minimum allowed node voltage, and $V_{\mathrm{H}n}$ is the maximum. The last two columns report the final optimized node voltage as a percentage of the allowed swing ($x_n$) and in volts ($V_n$).

Node n	${\mathit{V}}_{\mathbf{L}\mathit{n}}$	${\mathit{V}}_{\mathbf{DD}}-{\mathit{V}}_{\mathbf{H}\mathit{n}}$	${\mathit{x}}_{\mathit{n}}$ (%)	${\mathit{V}}_{\mathit{n}}$ (V)
D1	$V_{\mathrm{G}2}+V_{\mathrm{p}}$	$V_{\mathrm{p}}$	50	1.3559
G1	$V_{\mathrm{G}2}+V_{\mathrm{TH}}$	$V_{\mathrm{p}}$	90	1.6302
G2	$V_{\mathrm{TH}}$	$V_{\mathrm{p}}+V_{\mathrm{TH}}$	30	0.7118
G3	0	$V_{\mathrm{TH}}$	0	0.0000
G4	0	$V_{\mathrm{TH}}$	0	0.0000
G5	$V_{\mathrm{TH}}$	0	10	0.6716

, where the search for internal node bias has been further constrained to the range between 10% and 90% of the possible swing.

It may be worth noticing that the optimal bias for the gates of $M_3$ and $M_4$ turned out to be ground (due to having minimized their widths), which is very convenient as only one bias generator (for the gate of $M_5$) is needed for best LNA operation. The resulting transistor widths are shown in

Table 2. CNTFET sizes as determined by numerical optimization of the LNA.

FET	W (μm)	${\mathit{I}}_{\mathbf{D}}$ (mA)
$M_1$	250.6	7
$M_2$	150.4	2
$M_3$	19.1	2
$M_4$	67.0	7
$M_5$	669.6	7

.

5. Simulation Results

Extensive simulations have been performed using the complete Verilog-A CNTFET model to ensure that the amplifier, designed with the simplified model, actually performs according to its designed specifications.

As a first test, Figure 7 reports the voltage gain of the amplifier. From the design data reported in Table 2, its nominal value should be around 25.7 dB, and as can be seen, the achieved gain is pretty close, with a $-3$ dB bandwidth of about 2.5 GHz.

The noise factor depends, of course, on the parameters used for the noise model, for which, unfortunately, we could not find enough experimental data to validate the value we used in our model and on the biasing of the input transistor, as discussed earlier. Nevertheless, with the values reported in the main text, the amplifier achieves around 1 dB of noise figure within the amplifier bandwidth, as shown in Figure 8.

Its linearity is also very good, due to the intrinsically linear input characteristics of the above CNTFET threshold, as demonstrated by the input-referred 1 dB compression point shown in Figure 9, which, considering the high gain of the amplifier, is essentially limited only by the swing of the output node.

Finally, the stability of the amplifier was also evaluated by a pole-zero analysis, reported in Figure 10, from which it is clear that the amplifier is indeed stable (all poles have negative real parts). It is also clearly visible that the amplifier bandwidth is limited by the pair of complex conjugate poles at around 2.5 GHz.

A summary of the achieved performance is shown in

Table 3. Performance comparison of the designed LNA with other works.

Reference	[22]	[23]	[24]	[25]	[26]	[29]	[27]	[28]	This Work
Node	180 nm	180 nm	450 nm	32 nm	65 nm	130 nm	65 nm	130 nm	90 nm
Technology	CMOS	CMOS	CNTFET	CNTFET	CMOS	CMOS	CMOS	CMOS	CNTFET
Data	Sim.	Meas.	Meas.	Sim.	Meas.	Meas.	Sim.	Sim.	Sim.
Bandwidth (GHz)	3–6	1.05–3.05	1–1.2	3–38	1–20	0.1–2.7	0.03–3	0.1–5	0.01–2.5
Power Supply (V)	1.8	1.8	2.5	1.0	1.6	1.2	1.2	1.2	2.0
Power (mW)	15.3	12.6	N/A	16	20.3	1.32	5.7	4.4	18
Gain (dB)	20.14–21	16.9	11	13.7–14.7	12.8	20	11.6	20	25.7
NF (dB)	3.5–3.6	2.6–3.1	8	0.4–1.3	3.3–5.3	4.0	2.7–3.32	3.04–3.97	1.0

, together with a comparison with those obtained by similar works, also taking into account some results relative to conventional CMOS LNAs, as there are still not many works that focus on LNAs made with CNTFET.

In particular, with respect to the two CNTFET LNAs reported in the table, our architecture has the highest gain, which could be obtained without sacrificing bandwidth due to the gm-boosting technique adopted. The high gain also helped in achieving a low NF, of the same order as the best CNTFET LNA reported in the table and at a comparable power dissipation level, and much lower than the CMOS alternatives, due to the intrinsic lower noise of the carbon nanotubes versus conventional transistors.

Of course, due to the relatively young stage of the CNT technology we are designing, and to the fact that the model used was fitted to simulated data, we expect that it might not capture all the details of the manufactured transistor. Actual devices might perform slightly differently and also exhibit parameter device variations, such as device mismatch, that might affect circuit biasing and thus the overall RF performance.

6. Conclusions

In this work, a designer-friendly, simplified model of CNTFET was developed and fitted to previously published data. Its simplicity, stemming from the separability property of the functional dependence of the drain current on the gate and drain voltages, allow direct design and optimization of circuit bias points, as was demonstrated by the designing of a CNTFET LNA. That, coupled with a noise model to optimize the overall noise figure of the amplifier, was then simulated using the full-fledged Verilog-A Stanford model augmented with noise sources. The simulation results show good agreement to the predicted performance, proving the correctness and usefulness of the proposed simplifications. A comparison of the circuit performance was also made with reference to several state-of-the-art architectures found in the literature, encompassing both conventional CMOS technologies and CNTFET circuits, confirming the overall validity of the proposed high-gain LNA design.