Suppressing Voltage Spikes of MOSFET in H-Bridge Inverter Circuit

Round 1

Reviewer 1 Report

I want to thanks the authors for their contributions and i accept the paper in this form 

Author Response

Reviewer Responses:

Reviewer 1
#1 Submitted by: Reviewer 1

I want to thanks the authors for their contributions and i accept the paper in this form 

Response: Thank you very much for your time and effort to review our manuscript.

Action:  We have revised the manuscript in accordance with the suggestions provided by the reviewer.

Author Response File: Author Response.pdf

Reviewer 2 Report

The topic is of interest. The paper needs from the following points: 1- Mathematical model: It is suggested to introduce the model. 2- The contribution: It is required to list the contribution clearly 3- The survey: it can be completed. 4- It is suggested to compare with recent methods. The reviewer suggests revisions so that authors can handle the above comments,

Author Response

Reviewer Responses:

Reviewer 2

#1 Submitted by: Reviewer 2

The topic is of interest. The paper needs from the following points:

 

Response: Thank you very much for your time and effort to review our manuscript. We have revised the manuscript in accordance to your useful suggestions accordingly.

• Mathematical model: It is suggested to introduce the model.

 

Response: Concerning the reviewer’s comment, the mathematical model has been added to the manuscript as reproduced here for convenience:

 

Action:  To give the mathematical modelling of the voltage spikes and oscillation conditions, the turn OFF process of the MOSFET has been analysed based on the Figure 8. An ideal MOSFET transistor consists of gate-drain capacitance (Cgd), drain-source capacitance (Cds), gate-source capacitance (Cgs) and internal diode with the parasitic inductance (LD, LS). However, Rg is the gate driver resistance. During turn OFF condition, Cgs capacitance starts discharged via Rg resistance which leads to decrease in the gate-to-source voltage Vgs.

Figure 8:  the equivalent circuit of the MOSFET transistor

 

Therefore, the pseudo-gate-source voltage of the MOSFET, based on [25], can be reproduced as:

                                                                           (1)

 

                                                                          (2)

 

                                                                          (3)

 

Where: Vs is the source voltage,  is the maximum charge value of the Cgs capacitor, and   is the maximum charge value of the Cdg capacitor.

 

                                                                  (4)

 

While the drain current i_d starts falling, the load current moves out to the freewheeling diode (FWD) as illustrated in (5) and (6). Additional to the voltage spikes, the drain current i_d composes oscillation due to the parasitic components of the MOSFET in the power loop at turn-off operation [26].

 

                                                                   (5)

 

                                                                             (6)

 

The equivalent circuit of the proposed scheme in the turn OFF state is as shown in the Figure 11. Therefore, the value of new capacitor CA can be calculated depending on the DC voltage source and t_on of the duty cycle.

Figure 11: the equivalent circuit of the proposed capacitor with the MOSFET parasitic parameters

 

According to the Kirchhoff’s voltage law (KVL) gives:

 

                                                                            (7)

 

                                                                  (8)

 

                                                                      (9)

 

Applying a Laplace transform and solving the differential equation,

 

                                                          (10)

 

                                                             (11)

 

                                                                                  (12)

 

                                                                (13)

 

Where:

t₁ and t₂ is the ON time at the period time of PWM.

 

                                                                                      (7)

 

Where:  fs is the switching frequency.

 

 

 

• The contribution: It is required to list the contribution clearly

 

Response:  Thank you very much for your useful comment, and the contribution of the proposed has been listed to the manuscript as shown below:

 

Action:  The high dv/dt through a fast-switching transient of the MOSFET is associated with the issue of parasitic components generating oscillations and voltage spikes having adverse effects on the operation of complementary switches, affecting thus the safe operation of the power devices.

 

The main contribution of this paper is to improve the capability of the gate driver circuit for suppressing the voltage spikes in the H-Bridge inverter. The proposed design is used to reduce dv/dt at the transition of the power switches and to suppress the voltage spikes from the output voltage signal.

 

• The survey: it can be completed.

Response:  Thank you very much for your comment, the introduction of the manuscript has been improved as shown below:

Action:  With the rapid development of the power transistor industry, the use of fast switching frequency speed has greatly increased. Although higher switching frequency guarantees quality output, it increases switching losses. However, by applying high switching speed, the parasitic parameters such as parasitic capacitance and inductance with the PCB traces become crucial factors which mainly affect the performance of the power transistors. Therefore, it is important to analysis the effect of these parasitic components and calculates the loss of the MOSFET accurately.

 

On the other hand, the parasitic inductance can boost the voltage overshoot which leads to more total harmonic distortion. To improve the performance of the H-bridge converter and mitigate the effect of the total harmonic distortion, it is important to eliminate the parasitic resonance [6]. A root locus technique has been used with RC snubber circuit design in [7] for double pulse circuit of the SiC MOSFET by ignoring the parasitic inductance source.

 

In the turn off state and due to the voltage rising across the MOSFET, charging current stream via its parasitic capacitance which leads to inducing positive voltage spikes at the gate. If the voltage of these spikes overrun gate threshold voltage, the high side of the MOSFET could be falsely triggering. Gate impedance monitoring method has used to decrease the gate voltage spikes in order to provide a low impedance path by added external gate-source capacitance [30,31]

 

• It is suggested to compare with recent methods.

Response:  Thank you very much for your comment. To compare the proposal scheme with the recent methods Table 2 presents the comparison between different techniques.

Action:  7. Comparison of MOSFET Gate Driver Techniques for Suppressing Voltage Spikes

To show the advantage of the proposed scheme, a comparison with different methods which are presented in References [13]-[17]. These techniques can improve the performance in some sides. However, they all have some disadvantages in other aspects. Table 2 illustrates the comparison between different techniques for capability of suppressing voltage spikes. The proposed method in this paper has superior characteristics comparing to other gate drivers in terms of the voltage spikes suppression capability and the simplicity in design.

 

Table 2. Comparison between different gate driver techniques

Reference	Proposed Technique	Suppressing of Positive voltage spike	Suppressing of Negative voltage spike
[9]	A new gate drive based on adjustment of magnetic bead’s	No	Yes
[18]	RCD level-shifter for bridge-leg configuration	Yes	No
[25]	A passive triggered transistor with a series capacitor to suppress the negative voltage spikes	Yes	Yes
[26]	Active Gate Driver for MOSFET to Suppress Turn-Off Spike and Oscillation	No	Yes
The proposed	Improvement of gate driver circuit for MOSFET	Yes	Yes

 

 

 

Author Response File: Author Response.pdf

Reviewer 3 Report

In all text: Dots instead of colons after „Figure” in the Figure Captions.

The line 84: Move the heading to the other page.

In all text: Use references when stating equations.

Author Response

Reviewer Responses:

 

Reviewer 3

#3 Submitted by: Reviewer 3

 

In all text: Dots instead of colons after “Figure” in the Figure Captions.

The line 84: Move the heading to the other page.

In all text: Use references when stating equations.

Response: We appreciate the reviewer’s time in reviewing our manuscript.

Action:  We have revised the manuscript in accordance with the suggestions provided by the reviewer.

Author Response File: Author Response.pdf

Round 2

Reviewer 2 Report

The paper is well revised

 

Author Response

Reviewer 2
#1 Submitted by: Reviewer 2

The paper is well revised

Response:

We thank you for agreeing in this Round 2 with your response to a wide range of changes that you made in the Round 1.

Author Response File: Author Response.pdf

Reviewer 3 Report

It is not a novel design. Figure 10 shows a typical connection for the IR2112. An example of such solution one can be found e.g. at https://www.infineon.com/dgdl/Infineon-IR2112-DS-v01_00-EN.pdf?fileId=5546d462533600a4015355c81cb71685.

In previous review I mentioned it in comments for Editors.

Author Response

Reviewer Responses:

Reviewer 3

#1 Submitted by: Reviewer 3

It is not a novel design. Figure 10 shows a typical connection for the IR2112. An example of such solution one can be found e.g. at https://www.infineon.com/dgdl/Infineon-IR2112-DS-v01_00-EN.pdf?fileId=5546d462533600a4015355c81cb71685.

Response: Thank you so much for your time and expertise in reviewing our manuscript in Round 2, after having responded to the changes you had instituted in Round 1. We regard this new comment very useful, and it is here where we claim the novelty of our work as under:  

• The high dv/dt, as a result of fast transient switching of the MOSFET, is associated with the issue of parasitic components in generating oscillations and voltage spikes. These spikes are having adverse effects on the operation of complementary switches, thus affecting the safe operation of power devices.
• The main contribution of this paper is to improve the ability of the gate drive circuit (IR2112) to suppress voltage spikes in the H-Bridge inverter. The proposed design is used to reduce dv/dt at the transition of power switches and to suppress voltage spikes from the output voltage signal.
• In this paper, the proposed approach is used to improve the high-performance gate drive circuits based on the gate driver IR2112 in order to suppress the voltage spike from the H-bridge inverter output voltage by adding an external capacitor to the gate drive circuit.
• The honorable reviewer has indicated the link of datasheet where capacitors external to the IR2112 (actual circuit schematic in Figure 2 in the datasheet) are used to measure the input/output delay (Figure 3 in the datasheet) in consequence.

However, our contribution is intended:

1. In the use of IR2112 associated with fast switching H-bridge inverter.
2. Showing the generation of spikes
3. Suppressing those spikes through the use of capacitors external to IR2112.
4. Justifying the utility of our contribution through experimental validation

Author Response File: Author Response.pdf

Round 3

Reviewer 3 Report

I would like to thank the authors for their comprehensive response to my comment.

Remarks:

The line 170: incorrect equation numbering.

Remember to explain new symbols that appear in the text.

Author Response

Reviewer 3

#1 Submitted by: Reviewer 3

I would like to thank the authors for their comprehensive response to my comment.

• The line 170: incorrect equation numbering.

Response: Thank you so much for your time and expertise in reviewing our manuscript in Round 3.

The equation number has been corrected in the manuscript as shown below.

                                                   (14)

• Remember to explain new symbols that appear in the text.

Response: Thank you for your comment, all new symbols have been explained as shown below:

• Where:  is the maximum charge value of the capacitor, and  is the maximum charge value of the
• Where: is the drain current;  is the transconductance
• Where:
• t1 and t2 is the ON time at the period time of PWM; LD MOSFET Internal Drain Inductance;
• LS is the Internal Source Inductance; CA is the external capacitor; VS is the voltage at VS

Author Response File: Author Response.pdf