A Novel Switched-Capacitor Inverter with Reduced Capacitance and Balanced Neutral-Point Voltage

Abstract

A novel three-phase switched-capacitor multilevel inverter (SCMLI) with reduced capacitance and balanced neutral-point voltage is proposed in this paper. Applying only one DC source, the three-phase seven-level topology possessing voltage-boosting capability is accomplished without the high-voltage stress of power switches. Owing to the inherent redundant switching states of the proposed topology, two charging approaches that can effectively limit the voltage ripples and path selection for capacitors can be realized. This provides the presented topology with reduced capacitance, balanced neutral-point voltage, good performance in not only the three-phase four-wire system but also the three-phase three-wire system, and low total harmonic distortion (THD) of the output voltage. A comprehensive comparison with previous SCMLIs in various aspects is conducted to validate the merits mentioned above. The simulation results accord with theoretical analyses, confirming the feasibility of the proposed three-phase SCMLI.

1. Introduction

Multilevel inverters are important circuit configurations in modern electrical power systems because of their many advantages, such as low total harmonic distortion (THD) of the output voltage, low voltage stress on power devices, and low electromagnetic interference (EMI). The main applications of these inverters include static compensators, high-voltage DC transmission systems, active power filters, and renewable energy systems that include variable-frequency motor drives [1,2,3,4,5,6]. Neutral-point-clamped (NPC) [7], flying-capacitor [8], and cascaded H-bridge [9] are three well-researched multilevel inverters. These inverters are widely used in practical and commercial applications. However, these inverters have shortcomings such as neutral-point voltage imbalance and the need for excessive isolated DC sources [10]. Owing to the inability to boost the input voltage, the sum of the DC source voltages cannot be less than the amplitude of the output voltage. To overcome the drawbacks mentioned above, many new topologies have been introduced that offer more optimized component utilization, more voltage levels, higher efficiency, and so on [11,12].

Since the input voltage is relatively low compared with the output voltage, boost circuits [13,14] are required in many applications, such as grid-connected photovoltaic modules, distributed generation (DG) systems, and electric vehicles. Inductors or transformers are used in most boost circuits, making the systems bulky and heavy [15]. Therefore, a charge pump is typically adopted as a boost circuit [16]. In the charge pump, the output voltage is equal to the sum of the capacitor voltages and the input voltage. The capacitors in the charge pump are discharged when connected in series and charged when connected in parallel along with the DC source.

Inverters using the same working principle are called switched-capacitor multilevel inverters (SCMLI), which have become a recent research topic of interest [17,18]. Unlike inductors or transformers, capacitors are used to boost the input voltage. Employing fewer isolated DC sources and related components, they can generate voltage levels. To boost the input voltage, capacitors need to be involved in the load current path. In most SCMLIs, all relevant capacitors are discharged at the top voltage level. In addition, the discharging state can last for a long time according to the modulation method. This time is called the longest discharging time (LDT). As a result, capacitors have difficulty maintaining their voltage, thus exceeding the maximum allowable value of the voltage ripples. This is a critical challenge for existing SCMLIs.

Several methods have been used to solve this problem, but the most adopted method is to increase the capacitance. By employing only one DC source in a three-phase topology, a boost seven-level switched-capacitor inverter was proposed in [19]. The voltage stress of all power switches did not exceed the input voltage, and the capacitance used was 4700 μF. This method increased the volume and cost of the system [20,21]. Another method involves increasing the frequency of the output voltage. A family of SCMLI topologies for high-frequency AC applications was proposed in [22]. This approach can generate more voltage levels with an optimal component count. The main applications of this method have been limited to high-frequency AC systems [23,24]. A third method involves decreasing the maximum allowable modulation index. A novel seven-level inverter for medium-voltage high-power applications was presented in [25], and the maximum allowable modulation index was 0.813. This method reduces the boosting ability of SCMLIs [26]. A fourth method involves reducing the load. A boost single-phase switched-capacitor inverter was presented in [27]. With fewer power switches, this SCMLI could generate nine voltage levels under a resistive load condition (200 Ω). However, this method limits the power that SCMLIs can supply when the output voltage is the same [28,29].

Another problem for several SCMLIs that adopt a DC-link converter is the neutral-point voltage imbalance [30,31,32,33]. The self-balancing characteristic of these SCMLIs self-regulates the average neutral-point voltage to a certain value (usually half the DC-link voltage). The self-balancing time is long, and the neutral-point voltage may drift excessively. In addition, a three-phase three-wire system can worsen this problem in most traditional three-phase SCMLIs. Additional hardware or software measures are necessary to solve this problem. Regarding software measures, many studies have been carried out based on NPC topology. However, there is little research on this problem in SCMLIs. Hardware measures, such as adding additional components, increase the volume and cost of the system.

Generally, the abovementioned topologies have various disadvantages. To overcome these shortcomings, a novel three-phase SCMLI is presented in this paper. The main advantages of the proposed topology are as follows:

(1)

Less capacitance (200 μF) is used.

(2)

There is no problem of neutral-point voltage imbalance.

(3)

Good performance is achieved in not only a three-phase four-wire system but also a three-phase three-wire system.

(4)

Only one DC source is used as a three-phase topology.

(5)

All floating capacitors are used to generate the top voltage level.

This paper is organized as follows: the topology of the proposed SCMLI and the operating principle are fully outlined in Section 2. Theoretical analyses of the two charging approaches are provided in Section 3. Control strategies are presented in Section 4. The voltage ripples of the capacitors are carefully analyzed in Section 5. The overall system efficiency is calculated in Section 6. Simulation results and a comprehensive comparison are presented in Section 7. Lastly, a conclusion is drawn in Section 8.

2. Proposed SCMLI and Operating Principle

The proposed three-phase SCMLI topology is shown in Figure 1. Employing one DC source and eight capacitors, it can generate seven voltage levels (0 V, 0.5 V_dc, V_dc, 1.5 V_dc, −0.5 V_dc, −V_dc, −1.5 V_dc) under different kinds of load conditions. The capacitors’ rated voltage is U_N = 0.5 V_dc. Bidirectional switches are used to block positive and negative voltage stress. The floating capacitors C_1,2 are used to generate the top voltage level. They can also balance the voltages of the DC-link capacitors C_dc1,2 when needed. Furthermore, the proposed topology is used in a three-phase four-wire system when O and N are connected and is used in a three-phase three-wire system when O and N are not connected.

All switching states of the proposed three-phase SCMLI are listed in

Table 1. All switching states of the proposed three-phase SCMLI.

STATES	Voltage	Figure Position	Switches
	Level		S1	S2	S3	S4	S5	S6	S7	S8	S9	S10	S11	S12	S13
1	1.5 Vdc	Figure 2	1	0	0	0	0	0	1	0	1	1	0	0	0
2	Vdc	Figure 2	1	0	0	0	0	0	1	0	1	0	1	1	0
3	Vdc	Figure 5	0	0	0	1	1	0	0	0	1	1	0	0	0
4	0.5 Vdc	Figure 4	1	0	0	0	0	1	0	1	1	1	0	0	0
5	0.5 Vdc	Figure 4	0	1	1	0	0	1	0	0	1	1	0	0	0
6	0.5 Vdc	Figure 4	1	1	1	0	0	0	0	1	0	1	0	0	0
7	0.5 Vdc	Figure 5	1	0	0	0	0	0	0	1	0	1	0	0	0
8	0.5 Vdc	Figure 2	0	1	1	0	0	0	0	0	0	1	0	0	0
9	0.5 Vdc	Figure 2	0	0	0	1	1	0	0	0	1	0	1	1	0
10	0 V	Figure 4	1	0	0	0	0	1	0	1	1	0	1	1	0
11	0 V	Figure 4	0	1	1	0	0	1	0	0	1	0	1	1	0
12	0 V	Figure 4	1	1	1	0	0	0	0	1	0	0	1	1	0
13	0 V	Figure 5	1	0	0	0	0	0	0	1	0	0	1	1	0
14	0 V	Figure 5	0	0	0	0	0	1	0	0	1	0	1	1	0
15	0 V	Figure 2	0	1	1	0	0	0	0	0	0	0	1	1	0
16	−0.5 Vdc	Figure 4	1	0	0	0	0	1	0	1	1	0	0	0	1
17	−0.5 Vdc	Figure 4	0	1	1	0	0	1	0	0	1	0	0	0	1
18	−0.5 Vdc	Figure 4	1	1	1	0	0	0	0	1	0	0	0	0	1
19	−0.5 Vdc	Figure 5	0	0	0	0	0	1	0	0	1	0	0	0	1
20	−0.5 Vdc	Figure 2	0	1	1	0	0	0	0	0	0	0	0	0	1
21	−0.5 Vdc	Figure 2	0	0	0	1	1	0	1	1	0	0	1	1	0
22	−Vdc	Figure 2	0	0	0	0	0	1	1	1	0	0	1	1	0
23	−Vdc	Figure 5	0	0	0	1	1	0	1	1	0	0	0	0	1
24	−1.5 Vdc	Figure 2	0	0	0	0	0	1	1	1	0	0	0	0	1

. Main switching states are depicted in Figure 2a–g. Other switching states are fully discussed in Section 3 and Section 4. To generate 0 V, S₂, S₃, S₁₁, and S₁₂ need to be ON, as shown in Figure 2a. In Figure 2b,e, the black and red devices represent two different paths. Both C₁ and C₂ can be used to generate not only 0.5 V_dc but also −0.5 V_dc. Selecting the right path can make u_C1 approach u_C2. In Figure 2c,f, the capacitors C_dc1, C₂ and C_dc2, C₁ are used to generate V_dc and −V_dc, respectively. To generate 1.5 V_dc, S₁, S₇, S₉, and S₁₀ need to be ON, as shown in Figure 2d. Similarly, to generate −1.5 V_dc, S₆, S₇, S₈, and S₁₃ need to be ON, as shown in Figure 2g. For multilevel inverters, there are several modulation strategies. In this paper, the phase opposition disposition PWM is adopted, which is shown in Figure 2h.

3. Capacitor Charging Approaches

Two significant approaches are used in this paper to charge capacitors. Approach I that is first proposed in this paper plays an important role in balancing capacitors voltages and makes it possible for the proposed topology to solve the problem of neutral-point voltage imbalance. Approach II is a widely adopted approach that can charge the capacitors together. The equivalent circuits of approach I and approach II are shown in Figure 3a,b, respectively. R_dc1, R_dc2, R₁, and R₂ are the equivalent resistances of the devices.

3.1. Approach I

All of the DC-link capacitors C_dc1,2 and one of the floating capacitors C_1,2 were used to realize approach I in this paper. The circuit mode with C₁, C_dc1 and C_dc2 in Figure 3a is taken as an example to illustrate approach I. The approximation that C_dc1 = C_dc2 = C₁ = C₀ and R_dc1 = R_dc2 = R₁ = R₀ is introduced to simplify the analysis. The following analysis is based on this approximation. According to the topology, the equivalent capacitance C_eq and the equivalent resistance R_eq can be expressed as follows:

$$\begin{array}{l}{C}_{\mathrm{eq}}=\frac{(C_{\mathrm{dc}1}+C_1)C_{\mathrm{dc}2}}{C_{\mathrm{dc}1}+C_1+C_{\mathrm{dc}2}}=\frac{2}{3}{C}_0\\ R_{\mathrm{eq}}=\frac{R_{\mathrm{dc}1}{R}_1}{R_{\mathrm{dc}1}+R_1}+R_{\mathrm{dc}2}=\frac{3}{2}{R}_0\end{array}.$$

(1)

Therefore, the current that flows through the DC source is given by

$$i_{\mathrm{s}}=\frac{V_{\mathrm{dc}}-u_{\mathrm{eq}}(0)}{R_{\mathrm{eq}}}{e}^{-\frac{t}{R_{\mathrm{eq}}{C}_{\mathrm{eq}}}},$$

(2)

where

$$u_{\mathrm{eq}}(0)=\frac{u_{\mathrm{Cdc}1}\left(0\right)+u_{\mathrm{C}1}\left(0\right)}{2}+u_{\mathrm{Cdc}2}\left(0\right).$$

(3)

The voltage of capacitor C_dc2 can be expressed as

$$u_{\mathrm{Cdc}2}=u_{\mathrm{Cdc}2}\left(0\right)+\frac{1}{C_{\mathrm{dc}2}}{\displaystyle \underset{0}{\overset{t}{\int }}{i}_{\mathrm{s}}dt}=\frac{2}{3}[V_{\mathrm{dc}}-u_{\mathrm{eq}}(0)](1-e^{-\frac{t}{R_0{C}_0}})+u_{\mathrm{Cdc}2}\left(0\right).$$

(4)

The voltage of capacitor C_dc1 satisfies the following differential equation:

$$u_{\mathrm{Cdc}1}+R_{\mathrm{dc}1}{C}_{\mathrm{dc}1}\frac{d{u}_{\mathrm{Cdc}1}}{dt}=V_{\mathrm{dc}}-u_{\mathrm{Cdc}2}-i_{\mathrm{s}}{R}_{\mathrm{dc}2}=\frac{V_{\mathrm{dc}}+u_{\mathrm{Cdc}1}(0)-u_{\mathrm{Cdc}2}(0)+u_{\mathrm{C}1}(0)}{3}.$$

(5)

According to Equation (5), C_dc1 initial voltage is u_Cdc1(0) and final voltage is (V_dc + u_Cdc1(0) − u_Cdc2(0) + u_C1(0))/3. According to the full response theory of the first order circuit, u_Cdc1 can be expressed as

$$u_{\mathrm{Cdc}1}=u_{\mathrm{Cdc}1}(0)e^{-\frac{t}{R_0{C}_0}}+\frac{V_{\mathrm{dc}}+u_{\mathrm{Cdc}1}(0)-u_{\mathrm{Cdc}2}(0)+u_{\mathrm{C}1}(0)}{3}(1-e^{-\frac{t}{R_0{C}_0}}).$$

(6)

Similarly, u_C1 can be expressed as

$$u_{\mathrm{C}1}=u_{\mathrm{C}1}(0)e^{-\frac{t}{R_0{C}_0}}+\frac{V_{\mathrm{dc}}+u_{\mathrm{Cdc}1}(0)-u_{\mathrm{Cdc}2}(0)+u_{\mathrm{C}1}(0)}{3}(1-e^{-\frac{t}{R_0{C}_0}}).$$

(7)

When u_Cdc1(0) > 0.5 V_dc > u_Cdc2(0) and u_C1(0) < 0.5 V_dc, capacitors C₁ and C_dc2 will be charged, and capacitor C_dc1 will be discharged according to Equations (4), (6) and (7). When u_Cdc1(0) < 0.5 V_dc < u_Cdc2(0) and u_C1(0) > 0.5 V_dc, capacitors C₁ and C_dc2 will be discharged, and capacitor C_dc1 will be charged similarly. If approach I is adopted, all relevant capacitor voltages will move toward 0.5 V_dc. Furthermore, these voltages will reach 0.5 V_dc if u_Cdc1(0) − u_Cdc2(0) + u_C1(0) = 0.5 V_dc. As shown in Figure 4a, S₁, S₈, S₂, and S₃ are ON. C₁ and C_dc1 are connected in parallel, and approach I is realized. To generate 0 V at the same time, S₁₁ and S₁₂ should be ON. Moreover, 0.5 V_dc and −0.5 V_dc can be generated when S₁₀ and S₁₃ are ON, respectively. As shown in Figure 4b, S₂, S₃, S₆, and S₉ are ON. C₂ and C_dc2 are connected in parallel, and approach I is realized. Similarly, 0 V, 0.5 V_dc, and −0.5 V_dc can be generated at the same time.

3.2. Approach II

Approach II, which is used to balance the floating capacitor voltages, is shown in Figure 3b. Similarly, it is assumed that C₁ = C₂ = C₀ and R₁ = R₂ = R₀. According to the topology, R_eq = 2R₀ and C_eq = 0.5C₀. Therefore, i_s is given by

$$i_{\mathrm{s}}=\frac{V_{\mathrm{dc}}-u_{\mathrm{eq}}(0)}{R_{\mathrm{eq}}}{e}^{-\frac{t}{R_{\mathrm{eq}}{C}_{\mathrm{eq}}}},$$

(8)

where u_eq(0) = u_C1(0) + u_C2(0). u_C1 can be calculated as follows:

$$u_{\mathrm{C}1}=u_{\mathrm{C}1}\left(0\right)+\frac{1}{C_1}{\displaystyle \underset{0}{\overset{t}{\int }}{i}_{\mathrm{s}}dt}=\frac{1}{2}[V_{\mathrm{dc}}-u_{\mathrm{eq}}(0)](1-e^{-\frac{t}{R_0{C}_0}})+u_{\mathrm{C}1}\left(0\right).$$

(9)

Similarly, u_C2 can be expressed as follows:

$$u_{\mathrm{C}2}=\frac{1}{2}[V_{\mathrm{dc}}-u_{\mathrm{eq}}(0)](1-e^{-\frac{t}{R_0{C}_0}})+u_{\mathrm{C}2}\left(0\right).$$

(10)

After applying approach II, the average u_C1 and u_C2 reach 0.5 V_dc, according to Equations (9) and (10). Moreover, u_C1 and u_C2 will reach 0.5 V_dc if u_C1(0) = u_C2(0). Approach II can be realized when S₁, S₈, S₆, and S₉ are ON, as shown in Figure 4c. Any one of 0 V, 0.5 V_dc, and −0.5 V_dc can be generated at the same time. These two charging approaches can be realized, which is an important feature of the proposed three-phase SCMLI.

4. Control Strategies to Limit Voltage Ripples

To limit voltage ripples, the control strategies of the capacitor voltages are listed in

Table 2. Control strategies of the capacitor voltages.

Capacitors	Control Strategy
C1 and C2	Approach II, path selection
Cdc1 and Cdc2	Approach I, path selection

. For capacitors C₁ and C₂, the control strategies can be divided into two aspects. The first aspect involves using approach II and making the average of u_C1 and u_C2 return to 0.5 V_dc. Approach II is taken when |0.5(u_C1 + u_C2) − 0.5 V_dc| > u_γ. u_γ is an adjustable parameter. The second aspect involves selecting the right path and making u_C1 approach u_C2. The path selection for C_1,2 is used if |0.5(u_C1 + u_C2) − 0.5 V_dc| < u_γ.

Similarly, for capacitors C_dc1 and C_dc2, the control strategies can be divided into two aspects. The first aspect involves using approach I and making u_Cdc1 and u_Cdc2 move toward 0.5 V_dc. Approach I is taken when |u_Cdc1 − u_Cdc2| > u_α. u_α is also an adjustable parameter. The second aspect involves selecting the right path and making u_Cdc1 approach u_Cdc2. As u_Cdc1 + u_Cdc2 = V_dc, u_Cdc1 and u_Cdc2 return to 0.5 V_dc when u_Cdc1 reaches u_Cdc2. The path selection for C_dc1,2 is used if |u_Cdc1 − u_Cdc2| < u_α.

There are more paths for selection in the proposed topology, and the redundant switching states are depicted in Figure 5a–e. With respect to Figure 5a, the black and red devices represent two different paths. S₁, S₈, S₁₁, and S₁₂ are ON, and the capacitors C_dc1 and C₁ are used to generate 0 V. Similarly, S₆, S₉, S₁₁, and S₁₂ are ON, and capacitors C_dc2 and C₂ are used to generate 0 V. Moreover, 0.5 V_dc is generated when S₁, S₈, and S₁₀ are ON, as shown in Figure 5b, whereas −0.5 V_dc is generated when S₆, S₉, and S₁₃ are ON, as shown in Figure 5d. In Figure 5c,e, capacitors C₁ and C₂ can be used to generate not only V_dc but also level −V_dc. For capacitors in the proposed topology, path selection is an important control strategy. As shown in Figure 2 and Figure 5, there are various paths for selection at several voltage levels, and the capacitors used are different, making it easier to balance the capacitor voltages. This is one of the main advantages of the proposed topology.

Usually, there is a conflict between the control strategies of u_C1,2 and the control strategies of u_Cdc1,2. It is important to make a comprehensive decision according to the latest status. In this paper, the top priority is to decide whether to take approach II. |0.5(u_C1 + u_C2) − 0.5 V_dc| > u_γ, and this is the criterion that u_C1 and u_C2 have to meet if approach II is to be taken. After that, approach I is taken when |u_Cdc1 − u_Cdc2| > u_α. This will make u_Cdc1 and u_Cdc2 move toward 0.5 V_dc. Then, the path selection for C_dc1,2 is used if |u_Cdc1 − u_Cdc2| > u_β. u_α is larger than u_β. Lastly, the path selection for C_1,2 is used.

The reasons for there being no problem of neutral-point voltage imbalance for the proposed three-phase SCMLI can be divided into two aspects. On the one hand, approach I is adopted in this paper. This approach is an effective measure to balance the capacitor voltages. On the other hand, there are various paths for selection at several voltage levels. These two aspects complement each other, giving the proposed topology the ability to solve the problem of neutral-point voltage imbalance.

5. Capacitance Determination

Approach II can be used at 0 V, 0.5 V_dc, and −0.5 V_dc. Thus, capacitors C₁ and C₂ are discharged when u_ref > V_dc and i_bus > 0 in the positive half cycle. To address this problem, an important change to the original modulation method is made in this paper, and the new modulation wave in the positive half cycle is shown in Figure 6.

According to the original modulation method, there are two choices in a switching period when u_ref > V_dc. These choices are u_bus = V_dc and u_bus = 1.5 V_dc. In this paper, this condition is expressed as u_bus ϵ {V_dc, 1.5 V_dc}. u_bus ϵ {0.5 V_dc, 1.5 V_dc} is added when t₁ ≤ t ≤ t₄ because the abovementioned control strategies can be realized at 0.5 V_dc. Specifically, u_bus ϵ {0.5 V_dc, 1.5 V_dc} is used in half of the switching periods when t₁ ≤ t ≤ t₂ or t₃ ≤ t ≤ t₄. u_bus ϵ {0.5 V_dc, 1.5 V_dc} is used in all the switching periods when t₂ ≤ t ≤ t₃.

The longest discharging time of floating capacitors is an important SCMLI parameter because the required capacitance can be calculated according to it. The longest discharging time t_ldt of floating capacitors in the proposed three-phase SCMLI can be expressed as

$$t_{\mathrm{ldt}}=2T_{\mathrm{s}}-t_{\mathrm{c}},$$

(11)

where T_s is the switching period, and t_c is the minimum duration of 0.5 V_dc when t₁ ≤ t ≤ t₂ or t₃ ≤ t ≤ t₄. According to Equation (11), the longest discharging time of floating capacitors in the proposed topology is smaller than 2T_s, which is much shorter than that in other traditional SCMLIs. During the longest discharging time, the current that flows through floating capacitors is i_bus. The voltage variation of floating capacitors that comes from i_bus can be calculated as follows:

$$\frac{{\displaystyle \underset{t_{\mathrm{start}}}{\overset{t_{\mathrm{end}}}{\int }}{i}_{\mathrm{bus}}dt}}{C_{1,2}}\approx \frac{2T_{\mathrm{s}}-t_{\mathrm{c}}}{C_{1,2}}{i_{\mathrm{bus}}|}_{t=t_{\mathrm{start}}}<\frac{2T_{\mathrm{s}}}{C_{1,2}}\frac{m{A}_{\mathrm{boost}}{V}_{\mathrm{dc}}}{\left|Z_{\mathrm{MN}}\right|},$$

(12)

where m is the modulation index, and A_boost is the voltage gain. t_start and t_end are the start time and end time of the longest discharging time, respectively. Z_MN is the total impedance between point M and point N. Considering that approach I is adopted, Equation (12) needs to satisfy

$$\frac{2T_{\mathrm{s}}}{C_{1,2}}\frac{m{A}_{\mathrm{boost}}{V}_{\mathrm{dc}}}{\left|Z_{\mathrm{MN}}\right|}<0.5u_{\mathsf{\alpha }}.$$

(13)

According to Equation (13), the required capacitance of floating capacitors can be calculated as follows:

$$C_{1,2}>\frac{4T_{\mathrm{s}}}{u_{\mathsf{\alpha }}}\frac{m{A}_{\mathrm{boost}}{V}_{\mathrm{dc}}}{\left|Z_{\mathrm{MN}}\right|}.$$

(14)

According to Equations (11)–(14), reducing the longest discharging time of the floating capacitors can effectively reduce the capacitance of the floating capacitors.

Approach I, which can make u_Cdc1 and u_Cdc2 move toward 0.5 V_dc, is taken if |u_Cdc1 − u_Cdc2| > u_α. Thus, u_Cdc1 and u_Cdc2 can be limited to 0.5 V_dc ± 0.5 u_α with less DC-link capacitance. Similarly, the voltage variation of the DC-link capacitors between t_begin (the end time of the first approach I) and t_finish (the start time of the second approach I) can be calculated as follows:

$$\frac{{\displaystyle \underset{t_{\mathrm{begin}}}{\overset{t_{\mathrm{finish}}}{\int }}{i}_{\mathrm{Cdc}1}dt}}{C_{\mathrm{dc}1,2}}\approx \frac{k{T}_{\mathrm{s}}}{C_{\mathrm{dc}1,2}}{i_{\mathrm{Cdc}1}|}_{t=t_{\mathrm{begin}}}<\frac{k{T}_{\mathrm{s}}}{2C_{\mathrm{dc}1,2}}\frac{m{A}_{\mathrm{boost}}{V}_{\mathrm{dc}}}{\left|Z_{\mathrm{MN}}\right|},$$

(15)

where kT_s = t_finish − t_begin. To coincide with approach I, Equation (15) needs to satisfy

$$\frac{k{T}_{\mathrm{s}}}{2C_{\mathrm{dc}1,2}}\frac{m{A}_{\mathrm{boost}}{V}_{\mathrm{dc}}}{\left|Z_{\mathrm{MN}}\right|}<0.5u_{\mathsf{\alpha }}.$$

(16)

According to Equation (16), the required capacitance of the DC-link capacitors can be calculated as follows:

$$C_{\mathrm{d}c1,2}>\frac{k{T}_{\mathrm{s}}}{u_{\mathsf{\alpha }}}\frac{m{A}_{\mathrm{boost}}{V}_{\mathrm{dc}}}{\left|Z_{\mathrm{MN}}\right|}.$$

(17)

According to Equations (14) and (17), the required capacitance of the floating capacitors is similar to that of the DC-link capacitors. Therefore, C_1,2 = C_dc12 in this paper.

6. Efficiency Calculation

In this section, the overall efficiency of the proposed three-phase SCMLI is calculated. First, the conduction loss of the power switches P_con1 can be expressed as

$$P_{\mathrm{con}1}=f_{\mathrm{o}}{\displaystyle \sum _{i=1}^{N_{\mathrm{swi}}}{\displaystyle \underset{0}{\overset{T_{\mathrm{o}}}{\int }}(i_{\mathrm{si}}^2{r}_{\mathrm{si}}+i_{\mathrm{si}}{V}_{\mathrm{si}})dt}},$$

(18)

where i_si, r_si, and V_si are the current, internal resistance, and voltage drop of the i-th switch, respectively. N_swi is the number of power switches. T_o and f_o are the period and frequency of the output voltage, respectively. The conduction loss P_con2 that comes from the DC-link capacitors and the floating capacitors can be calculated as follows:

$$P_{\mathrm{con}2}=f_{\mathrm{o}}{\displaystyle \sum _{i=1}^{N_{\mathrm{ca}}}{\displaystyle \underset{0}{\overset{T_{\mathrm{o}}}{\int }}{i}_{\mathrm{Ci}}^2{r}_{\mathrm{Ci}}dt}},$$

(19)

where i_Ci and r_Ci are the current and the internal resistance of the i-th capacitor, respectively. N_ca is the number of capacitors. The conduction loss of the output filters P_con3 can be calculated as follows:

$$P_{\mathrm{con}3}=f_{\mathrm{o}}{\displaystyle \sum _{i=1}^{N_{\mathrm{fil}}}{\displaystyle \underset{0}{\overset{T_{\mathrm{o}}}{\int }}(i_{\mathrm{Lfi}}^2{r}_{\mathrm{Lfi}}+i_{\mathrm{Cfi}}^2{r}_{\mathrm{Cfi}})dt}},$$

(20)

where i_Lfi and r_Lfi are the current and the internal resistance of the i-th filter inductor, respectively. i_Cfi and r_Cfi are the current and the internal resistance of the i-th filter capacitor, respectively. N_fil is the number of filters.

To simplify the analysis, the voltage and the current of the power switches are considered to have a linear relation with time during the switching process. Therefore, the switching loss P_off(i,j) that is caused by the j-th turning OFF process of the i-th switch is given by

$$P_{\mathrm{off}(\mathrm{i},\mathrm{j})}=f_{\mathrm{o}}{\displaystyle {\int }_0^{t_{\mathrm{off}}}v(t)i(t)dt}=f_{\mathrm{o}}{\displaystyle {\int }_0^{t_{\mathrm{off}}}\frac{V_{\mathrm{off}(\mathrm{i},\mathrm{j})}}{t_{\mathrm{off}}}t[-\frac{I_{\mathrm{off}(\mathrm{i},\mathrm{j})}}{t_{\mathrm{off}}}(t-t_{\mathrm{off}})]dt}=\frac{1}{6}{V}_{\mathrm{off}(\mathrm{i},\mathrm{j})}{I}_{\mathrm{off}(\mathrm{i},\mathrm{j})}{t}_{\mathrm{off}}{f}_{\mathrm{o}},$$

(21)

where V_off(i,j) and I_off(i,j) are the voltage after the turning OFF process and the current before the turning OFF process, respectively. Similarly, switching loss P_on(i,j) that is caused by the j-th turning ON process of the i-th switch is given by

$$P_{\mathrm{on}(\mathrm{i},\mathrm{j})}=\frac{1}{6}{V}_{\mathrm{on}(\mathrm{i},\mathrm{j})}{I}_{\mathrm{on}(\mathrm{i},\mathrm{j})}{t}_{\mathrm{on}}{f}_{\mathrm{o}},$$

(22)

where V_on(i,j) and I_on(i,j) are the voltage before the turning ON process and the current after the turning ON process, respectively. According to Equations (21) and (22), the total switching loss P_sw can be calculated by

$$P_{\mathrm{sw}}={\displaystyle \sum _{i=1}^{N_{\mathrm{swi}}}({\displaystyle \sum _{j=1}^{N_{\mathrm{on}\left(\mathrm{i}\right)}}{P}_{\mathrm{on}(\mathrm{i},\mathrm{j})}}+{\displaystyle \sum _{j=1}^{N_{\mathrm{off}\left(\mathrm{i}\right)}}{P}_{\mathrm{off}(\mathrm{i},\mathrm{j})}})}=\frac{1}{6}{f}_{\mathrm{o}}{\displaystyle \sum _{i=1}^{N_{\mathrm{swi}}}(t_{\mathrm{on}}{\displaystyle \sum _{j=1}^{N_{\mathrm{on}\left(\mathrm{i}\right)}}{V}_{\mathrm{on}(\mathrm{i},\mathrm{j})}{I}_{\mathrm{on}(\mathrm{i},\mathrm{j})}}+t_{\mathrm{off}}{\displaystyle \sum _{j=1}^{N_{\mathrm{off}\left(\mathrm{i}\right)}}{V}_{\mathrm{off}(\mathrm{i},\mathrm{j})}{I}_{\mathrm{off}(\mathrm{i},\mathrm{j})}})},$$

(23)

where N_on(i) and N_off(i) are the number of i-th switch turning ON processes and turning OFF processes, respectively.

According to Equations (18)–(20), and (23), the overall efficiency of the proposed topology is given by

$$\eta =\frac{P_{\mathrm{o}}}{P_{\mathrm{o}}+P_{\mathrm{con}1}+P_{\mathrm{con}2}+P_{\mathrm{con}3}+P_{\mathrm{sw}}}.$$

(24)

7. Simulation Results and Comparison

7.1. Simulation Results

MATLAB/Simulink was chosen as the simulation software. The parameters of the proposed three-phase SCMLI are listed in

Table 3. Parameters of the proposed three-phase SCMLI.

Parameters	Value
Vdc	200 V
Capacitor rated voltage	100 V
Modulation ratio	0.95
Output voltage	285 V
C1, C2, Cdc1, and Cdc2	200 μF
Output power	1884 W
Resistive–inductive load Z1	40 Ω, 100 mH
uα	8 V
Filter capacitor	80 μF
Filter inductor	4 mH
Switching frequency	20 kHz
Output frequency	50 Hz

. The input voltage was set as 200 V, which resembles many other SCMLIs. Thus, the rated voltage of the capacitors was 100 V. The modulation ratio was 0.95, and the output voltage was 285 (300 × 0.95) V. The capacitance used was 200 μF, which meets the requirement of Equation (15). The output power was 1884 W, and the resistive–inductive load Z₁ was 40 Ω, 100 mH. u_α was 8 V since the maximum allowable voltage ripple of capacitors was 10 V (10% of the rated voltage). The filter capacitor was 80 μF, and the filter inductor was 4 mH. The switching frequency was 20 kHz. This frequency can reduce the requirement of capacitance according to Equation (15). The output frequency was 50 Hz.

7.1.1. Performance in Three-Phase Four-Wire System

To assess the performance of the proposed three-phase SCMLI in the three-phase four-wire system, Z_o = Z₁ is given. Figure 7a shows the observed A-phase bus voltage. The top voltage level was 300 V, and the proposed three-phase SCMLI could boost the input voltage. Because u_α was equal to 8 V, the voltages of the DC-link capacitors in the A-phase were limited to 96–104 V, as shown in Figure 7b. Approach I could move the voltage of DC-link capacitors toward 100 V when they were larger than 104 V or smaller than 96 V. Figure 7c shows the floating capacitor voltages in the A-phase, which were approximately 96–103 V. It can be seen in this figure that the longest discharging time of floating capacitors was shorter than 2T_s. These waveforms meet the voltage ripple requirement, which should be less than 10% of the rated voltage.

The output voltage of each phase under the resistive–inductive load condition is shown in Figure 8a, and the fast Fourier transform (FFT) result of the A-phase output voltage is shown in Figure 8b. According to the result, THD = 1.87%, and the amplitude of the fundamental component was 285.1 V. This amplitude agrees with the modulation ratio because the desired amplitude of the output voltage was 285 V. Similarly, the output current of each phase under the resistive–inductive load condition is shown in Figure 9a, and the FFT result of the A-phase output current is shown in Figure 9b. THD = 0.83%, and the amplitude of the fundamental component was 5.605 A. The quality of all the waveforms was high, which is attributable to the low-voltage ripples of the capacitors.

To further test the performance of the proposed three-phase SCMLI, a resistive–inductive load transient is given. The time when the load changed from Z_o = 2Z₁ to Z_o = Z₁ was 0.12 s. The bus voltage of the A-phase is shown in Figure 10a. The difference between the waveform before 0.12 s and the waveform after 0.12 s was not notable. Figure 10b shows the A-phase DC-link capacitor voltages. The voltage ripple of these capacitors was 8 V during the entire process (u_α = 8 V). Figure 10c shows the A-phase floating capacitor voltages. The transient process only lasted for a short period of time (approximately 0.01 s). After that, the floating capacitor voltages quickly returned to the steady state. These waveforms also meet the voltage ripple requirements and are in good agreement with the abovementioned theoretical analysis.

The output voltage of each phase during a resistive–inductive load transient is shown in Figure 11a, and the FFT result of the A-phase output voltage is shown in Figure 11b. THD = 1.96%, and the start time was 0.12 s. There was no significant change in the output voltage of each phase after 0.12 s. The output current of each phase under the same resistive–inductive load transient is shown in Figure 12. Similarly, the transient process only lasted for a short period of time. The output current of each phase quickly changed from the initial steady state to a new steady state. Thus, there is no need to worry about the overvoltage problem or the overcurrent problem.

To test the presented three-phase SCMLI more rigorously, a special load with a temporary three-phase unbalanced disturbance is given. For each phase, Z_o = 2Z₁. A disturbance load R_d = 100 Ω was only added to the A-phase when 0.8 s < t < 0.85 s. Under this condition, Figure 13a shows the A-phase bus voltage, and there was no obvious change in the waveform when 0.8 s < t < 0.85 s or t > 0.85 s. Figure 13b shows the A-phase DC-link capacitor voltages. Similarly, the transient process only lasted for a short period of time (approximately 0.01 s). During this transient process, u_Cdc2 was momentarily larger than 104 V, and u_Cdc1 was momentarily smaller than 96 V. After that, the DC-link capacitor voltages were limited to 96–104 V, as before. Figure 13c shows the A-phase floating capacitor voltages. During the same transient process, u_C2 was momentarily larger than 105 V. After that, the floating capacitor voltages quickly returned to the steady state.

When the disturbance load was added to the A-phase, the output voltage of each phase was as shown in Figure 14a, and the FFT result of the A-phase output voltage was as shown in Figure 14b. THD = 3.28%, and the start time was 0.08 s. The change in the output voltage of each phase during the transient process was small.

When the disturbance load was added to the A-phase, the output current of each phase was as shown in Figure 15. The amplitude of the A-phase output current i_oA increased because of the disturbance load when 0.8 s < t < 0.85 s. After that (t > 0.85 s), the A-phase output current i_oA quickly returned to the steady state. As for i_oB and i_oC, the disturbance load had no effect because it was only added to the A-phase.

All these observed waveforms in the three-phase four-wire system are in good agreement with the theoretical analyses, confirming the feasibility of the proposed three-phase SCMLI in the three-phase four-wire system.

The recorded efficiency of different topologies is shown in Figure 16. The efficiency decreased with increasing output power. Compared with [27,30], the proposed topology has greater efficiency. The efficiency of the proposed topology is similar to that of [31]. As shown in Figure 17, the share of total conduction loss was larger than that of switching loss. This is because the switching frequency was at a normal level. Furthermore, the share of switching loss increased with decreasing output power. Therefore, decreasing the switching frequency can be adopted to improve the efficiency of the proposed topology when the output power is lower than 800 W.

7.1.2. Performance in Three-Phase Three-Wire System

To test the performance of the proposed three-phase SCMLI in a three-phase three-wire system, the same resistive–inductive load transient is given. The A-phase bus voltage is shown in Figure 18a. Because u_NO was not always equal to 0, the bus voltage had more voltage levels. The resistive–inductive load transient had no effect on the bus voltage. Figure 18b shows the DC-link capacitor voltages of the A-phase. The voltage ripple of these capacitors was 10 V. Figure 18c shows the floating capacitor voltages of the A-phase. They changed from 98–101 V to 96–104 V. All these waveforms met the voltage ripple requirements during the entire process.

The output voltage of each phase during a resistive–inductive load transient is shown in Figure 19a, and the FFT result of the A-phase output voltage is shown in Figure 19b. THD = 0.90%, and the start time was 0.12 s. Even in the first period after 0.12 s, the waveform quality of each phase output voltage satisfied the requirement. The output current of each phase under the same resistive–inductive load transient is shown in Figure 20. The transient process only lasted for a short period of time. The output current of each phase quickly changed from the initial steady state to a new steady state.

The problem of neutral-point voltage imbalance became more serious for traditional SCMLIs in the three-phase three-wire system. In contrast, these observed waveforms were in line with expectations, confirming that the proposed three-phase SCMLI achieves good performance in a three-phase three-wire system and there is no problem of neutral-point voltage imbalance.

7.2. Comparison

To better illustrate the advantages of the proposed topology, a comprehensive comparison with other up-to-date SCMLIs in various aspects is shown in

Table 4. Comparison of different topology results.

	[19]	[20]	[26]	[27]	[30]	[31]	[32]	[33]	Proposed Topology
CDC-link	4700 4700	-	-	-	-	-	1000 1000	4700 4700	200 200
Cfloating	4700 4700	6800 6800 3300	4330 4320 2190	1000 1000	2200 2200 2200	2200 /2200	1000	4700	200 200
Nca_3p	8	9	9	6	9	6	5	5	8
TRVca_3p	4	15	15	3	6	3	4	4	4
εca	100%	100%	80%	100%	50%	100%	100%	100%	100%
NDC_3p	1	3	3	3	3	3	1	1	1
Load condition	40 Ω 100 mH	50 Ω 30 mH	42.2 Ω 79 mH	200 Ω	30 Ω 30 mH	10 Ω 100 mH	160 Ω	40 Ω 100 mH	40 Ω 100 mH
m	1.0	0.9	0.91	1.0	1.0	1.0	1.0	1.0	0.95
Suffering from imbalance	yes	no	no	yes	yes	yes	yes	yes	no
Aboost	1.5	6	4	2	2	2	1.5	1.5	1.5
Nlevel	7	13	9	9	9	9	7	7	7
Nsd	10	15	12	11	11	10	9	9	13
TSVsw	9	33	24	12	10	11	8	8	11

C_DC-link is the DC-link capacitance (μF). C_floating is the floating capacitance (μF). N_{ca_3p} is the number of capacitors in the three-phase applications. TRV_{ca_3p} is the total rated voltage of capacitors (Vdc) in the three-phase applications. ε_ca is the share of the floating capacitors voltages that are used to generate the top voltage level. N_{DC_3p} is the number of DC sources in the three-phase applications. N_level is the number of voltage levels. N_sd is the number of power switches and diodes in each phase. TSV_sw is the total standing voltage of switches (V_dc) in each phase.

. The main advantages of the proposed topology are as follows:

(1)

Less capacitance (200 μF) is used.

In most SCMLIs, the required capacitance is usually greater than 2000 μF, thus increasing the volume and cost of the system. The capacitance used in [27,32] was 1000 μF, but the load impedance (>150 Ω) was much larger than that of other SCMLIs. The required capacitance increases with decreasing load impedance. The cost of capacitors increases with higher rated voltage, making the advantage of reduced capacitance in the proposed topology more obvious.

(2)

There is no problem of neutral-point voltage imbalance.

The DC-link converter brings the problem of neutral-point voltage imbalance to [19,27,30,31,32,33]. The self-balancing characteristic of these SCMLIs self-regulates the average neutral point voltage to a certain value (usually half the DC-link voltage). However, the self-balancing time is long, and the neutral-point voltage may drift excessively. Additional hardware or software measures need to be taken to solve this problem. Regarding software measures, there is little research about this problem in SCMLIs. Hardware measures, such as adding additional components to the system, increase the volume and cost of the system.

(3)

Good performance is achieved in not only the three-phase four-wire system but also the three-phase three-wire system.

Most traditional three-phase SCMLIs [19,32,33] suffer from the problem of neutral-point voltage imbalance, which becomes more serious in the three-phase three-wire system. Owing to the advantage above, the proposed topology can be adopted in more applications.

(4)

Only one DC source is used as a three-phase topology.

The methods used in [20,26,27,30,31] all represent single-phase topologies. In the three-phase applications, three DC sources are required for such topologies. This advantage of the proposed topology reduces the complexity and cost of the system.

(5)

All floating capacitors are used to generate the top voltage level.

Not all floating capacitors were used to generate the top voltage level in [26,30]. The voltages of these floating capacitors are underused. This advantage of the proposed topology reduces the demand for capacitors.

Furthermore, the proposed topology is simple. Thirteen power switches are used in each phase, and the sum of their voltage stresses is only 11 V_dc, which reaches the average level of other SCMLIs. Two DC-link capacitors and two floating capacitors in each phase are used, and the sum of their rated voltages is 4 V_dc, which is not larger than that of the other three-phase SCMLIs. The proposed topology can generate seven voltage levels under different kinds of load conditions.

8. Conclusions

A novel three-phase SCMLI with reduced capacitance and balanced neutral-point voltage was proposed in this paper. Good performance was achieved in not only the three-phase four-wire system but also the three-phase three-wire system. Only one DC source was used in the three-phase topology. A comprehensive comparison with other recently presented SCMLIs in various aspects was made, and simulation results under different kinds of load conditions were given. All observed waveforms were in good agreement with the theoretical analyses, confirming the feasibility of the proposed three-phase SCMLI.