Novel Three-Phase Nine-Level Inverter and Its Control Strategies

Abstract

In this paper, the authors propose a new three-phase, nine-level inverter with self-balancing of capacitors voltages. The proposed inverter is the result of a serial connection of the SPUC topology and the NPC converter. A single DC source is used, and each phase is made up of nine power switches and three capacitors. Two control techniques are proposed to maintain capacitors voltages at desired values, the first of which is a PWM technique ensures the self-balancing of capacitors voltages in open loop without using any filters or PI regulators, and the second is based on the hysteresis control which offers a nearly sinusoidal waveform of the load current without using any voltage sensors. The authors make use of the Matlab Simulink environment to perform the simulation of the proposed concept. The dynamics of the latter was verified against load change.

1. Introduction

In recent years, multilevel inverters have attracted considerable attention because of their advantages, including low electromagnetic interference (EMI), reduced voltage stress (dv/dt), low total harmonics distortion (THD), and high power conversion.

Many three-phase inverters were proposed over the years. Most of them are based on the three basic topologies, which are the neutral point clamped (NPC) [1], the cascaded H-bridge (CHB) [2], and the flying capacitor (FC) [3]. However, their power quality remains fairly low. The authors propose a solution by optimizing the number of active and passive devices. The proposed converter overcomes the serious drawback of the NPC by permitting a natural self-balancing of capacitors voltages when the number of the desired voltage levels is greater than three.

In this paper, we propose an advanced three-phase, nine-level inverter which is derived from the series connection of the SPUC [4] converter that allows a load voltage with high level number while using an optimized count of active and passive components and NPC topology that has the advantage of joining capacitors together. The proposed inverter uses the benefit of redundant states to perform the self-balancing of capacitors voltages in open loop without using any filters or PI regulators [5,6,7].

Firstly, a PWM technique is applied to the proposed inverter, as a result the system offering nine levels in output voltage without using any closed loop regulation [8,9,10,11,12,13,14,15,16,17,18,19]; because the latter is not suitable for some industrial applications, this allows a low cost of inverter and installation. Secondly, a hysteresis control is used to provide a near sinusoidal without the use of a voltage sensor or PI controllers.

2. Methods

Firstly, the proposed inverter topology, which is based on PUC and NPC converters, is presented in single- and three-phase versions, and then capacitors balancing techniques are detailed, which are PWM techniques and hysteresis controls.

2.1. Presentation the Proposed Three-Phase Inverter Topology and Switching States

The proposed inverter is derived from a series connection of SPUC and NPC converters, and this connection was used between PUC and NPC converters [20]. As a result, it can provide a maximum of levels using a single DC source because a closed loop is used to keep voltage values of the desired capacitors.

The proposed topology has a new advantage, which is the ability to maintain capacitors voltages at desired values in open loop without any PI regulators and with two different methods of control, which are PWM techniques and hysteresis control. The proposed nine-level inverter is constituted from nine power switches and three capacitors per phase. Those capacitors, which are C3, C4, and C5 should be balanced respectively to E/2, E/8, and E/8. However, C1 and C2 should be maintained in the half of the DC source. Figure 1 represents the single phase of the nine-level inverter proposed.

In order to generate a nine level output voltage, we assume that Vc1 = Vc2 = Vc3i = E/2 and Vc4i = Vc5i = E/8 (i = a, b, c).

Table 1. Switching sequence for the three-phase 9-level inverter proposed.

State	Interconnection	Voltage(V)	S1i	S2i	S3i	S4i	S5i	S6i	S7i	S8i	S9i
9	Vc2	400	0	0	0	0	0	1	0	1	0
9′	Vc3i	400	1	0	0	0	1	1	0	0	0
8	Vc3i − Vc5i	300	1	0	0	0	1	0	0	0	1
7	Vc3i − (Vc4i + Vc5i)	200	1	0	1	0	1	0	0	0	0
7′	Vc4i + Vc5i	200	1	1	0	0	0	1	0	0	0
6	Vc4i	100	1	1	0	0	0	0	0	0	1
5	0	0	1	1	1	0	0	0	0	0	0
5′	0	0	0	0	0	1	1	1	0	0	0
4	−Vc5i	−100	0	0	0	1	1	0	0	0	1
3	−Vc4i − Vc5i	−200	0	0	1	1	1	0	0	0	0
3′	(Vc4i + Vc5i) − Vc3i	−200	0	1	0	1	0	1	0	0	0
2	Vc4i − Vc3i	−300	0	1	0	1	0	0	0	0	1
1′	−Vc3i	−400	0	1	1	1	0	0	0	0	0
1	−Vc1	−400	0	0	1	0	0	0	1	0	0

represents the nine required levels with redundant states (1′, 3′, 5′, 7, 9′). Figure 2 represents the three-phase, nine-level inverter proposed.

The nine levels were generated as follows.

In state 9, in which the load voltage is equal to Vc2, switches S6 and S8 are “ON”. Capacitor C2 is discharging since it is connected only to the load.

In state 8, in which the load voltage is equal to Vc3i − Vc5i, switches S1, S5, and S9 are “ON”. Capacitor C5 has a serial connection with capacitor C3, thus Capacitor 5 is charging. However, Capacitor 3 is discharging.

In state 7′, in which the load voltage is equal to Vc4i + Vc5i, switches S1, S2, and S6 are “ON”. Capacitors are connected directly to the load, so they are discharging.

In state 6, in which the load voltage is equal to Vc4i, switches S1, S2, and S9 are “ON”. Capacitor C4 is discharging since it is connected only to the load.

In state 5, in which the load voltage is equal to zero, switches S1, S2, and S3 are “ON”. There is no effect to capacitors since none is connected to the DC source.

In state 4, in which the load voltage is equal to −Vc5i, switches S4, S5, and S9 are “ON”. Capacitor C5 is discharging since it is connected only to the load.

In state 3, in which the load voltage is equal to −Vc4i − Vc5i, switches S3, S4, and S5 are “ON”. Capacitors are connected directly to the load, thus, they are discharging.

In state 2, in which the load voltage is equal to Vc4i − Vc3i, switches S2, S4, and S9 are “ON”. Capacitor C4 has a serial connection with capacitor C3, thus, Capacitor 4 is charging. However, Capacitor 3 is discharging.

In state 1, in which the load voltage is equal to −Vc1, switches S3 and S7 are “ON”. Capacitor C1 is discharging since it is connected only to the load.

The number of voltage levels should be decreased in order to create several redundant states. The ability of choosing among them is one of the major advantages. Indeed, a state can be chosen according to the desired charging or discharging capacitor behavior while keeping the same output voltage value. As shown in Table 1, states (3 and 3′) allow the same output voltage, which is equal to −200 V. One can proceed by the same manner to determine the other redundant states.

2.2. Proposed Nine-Level Inverter Using PWM Technique

In order to generate the gate pulses, one has to design a modulation technique. Consequently, in this paper, the authors propose the following procedure in which a sign function of the reference voltage is used to determine ${\mathrm{S}}_1$.

$$\mathrm{Sign}\left({\mathrm{v}}_{\mathrm{r}}\right)=\left\{\begin{array}{c}{1,\mathrm{v}}_{\mathrm{r}}\ge 0\\ {0,\mathrm{v}}_{\mathrm{r}}<0\end{array}\right.$$

(1)

$${\mathrm{S}}_1=\mathrm{Sign}\left({\mathrm{v}}_{\mathrm{r}}\right)$$

(2)

Eight equal amplitude triangular carriers which are indicated by the letter ${\mathrm{C}}_{\mathrm{ri}}$ (i = 1…8) are compared with the sinusoidal reference, the carriers arrangements for PWM strategy are shown in Figure 3, and each comparison generates a new signal indicated by the letter Zi (i = 1…8).

$${\mathrm{Z}}_1=\left\{\begin{array}{c}{1,\mathrm{C}}_{\mathrm{r}1}\ge {\mathrm{v}}_{\mathrm{r}}\\ {0,\mathrm{C}}_{\mathrm{r}1}{<\mathrm{v}}_{\mathrm{r}}\end{array}\right.$$

(3)

$${\mathrm{Z}}_2=\left\{\begin{array}{c}{1,\mathrm{C}}_{\mathrm{r}2}\ge {\mathrm{v}}_{\mathrm{r}}\\ {0,\mathrm{C}}_{\mathrm{r}2}{<\mathrm{v}}_{\mathrm{r}}\end{array}\right.$$

(4)

$${\mathrm{Z}}_3=\left\{\begin{array}{c}{1,\mathrm{C}}_{\mathrm{r}3}\ge {\mathrm{v}}_{\mathrm{r}}\\ {0,\mathrm{C}}_{\mathrm{r}3}{<\mathrm{v}}_{\mathrm{r}}\end{array}\right.$$

(5)

$${\mathrm{Z}}_4=\left\{\begin{array}{c}{1,\mathrm{C}}_{\mathrm{r}4}\ge {\mathrm{v}}_{\mathrm{r}}\\ {0,\mathrm{C}}_{\mathrm{r}4}{<\mathrm{v}}_{\mathrm{r}}\end{array}\right.$$

(6)

$${\mathrm{Z}}_5=\left\{\begin{array}{c}{1,\mathrm{C}}_{\mathrm{r}5}\ge {\mathrm{v}}_{\mathrm{r}}\\ {0,\mathrm{C}}_{\mathrm{r}5}{<\mathrm{v}}_{\mathrm{r}}\end{array}\right.$$

(7)

$${\mathrm{Z}}_6=\left\{\begin{array}{c}{1,\mathrm{C}}_{\mathrm{r}6}\ge {\mathrm{v}}_{\mathrm{r}}\\ {0,\mathrm{C}}_{\mathrm{r}6}{<\mathrm{v}}_{\mathrm{r}}\end{array}\right.$$

(8)

$${\mathrm{Z}}_7=\left\{\begin{array}{c}{1,\mathrm{C}}_{\mathrm{r}7}\ge {\mathrm{v}}_{\mathrm{r}}\\ {0,\mathrm{C}}_{\mathrm{r}7}{<\mathrm{v}}_{\mathrm{r}}\end{array}\right.$$

(9)

$${\mathrm{Z}}_8=\left\{\begin{array}{c}{1,\mathrm{C}}_{\mathrm{r}8}\ge {\mathrm{v}}_{\mathrm{r}}\\ {0,\mathrm{C}}_{\mathrm{r}8}{<\mathrm{v}}_{\mathrm{r}}\end{array}\right.$$

(10)

A staircase signal which the image of the voltage load can then be generated by summing these equations is as follows.

$${\mathrm{S}=\mathrm{Z}}_1{+\mathrm{Z}}_2{+\mathrm{Z}}_3{+\mathrm{Z}}_4{+\mathrm{Z}}_5{+\mathrm{Z}}_6{+\mathrm{Z}}_7{+\mathrm{Z}}_8$$

(11)

The remaining gate pulses can then be expressed as follows.

$${\mathrm{S}}_2=\overline{{\mathrm{S}}_5}$$

(12)

$${\mathrm{S}}_3=\overline{{\mathrm{Z}}_6}+\overline{{\mathrm{Z}}_8}$$

(13)

$${\mathrm{S}}_4{=1-\mathrm{sign}(\mathrm{v}}_{\mathrm{r}})$$

(14)

$${\mathrm{S}}_5{=(\mathrm{Z}}_1{\mathrm{Z}}_2\oplus {\mathrm{Z}}_3{\mathrm{Z}}_4{)+(\mathrm{Z}}_1{\mathrm{Z}}_2\oplus {\mathrm{Z}}_3{\mathrm{Z}}_4)$$

(15)

$${\mathrm{S}}_6{=\mathrm{Z}}_1{+\mathrm{Z}}_3{+(\mathrm{Z}}_4\oplus {\mathrm{Z}}_5)$$

(16)

$${\mathrm{S}}_7{=(\mathrm{Z}}_1\oplus {\mathrm{Z}}_2{)+(\mathrm{Z}}_3\oplus {\mathrm{Z}}_4{)+(\mathrm{Z}}_5\oplus {\mathrm{Z}}_6{)+(\mathrm{Z}}_7\oplus {\mathrm{Z}}_8)$$

(17)

$${\mathrm{S}}_8{=\mathrm{Z}}_1$$

(18)

$${\mathrm{S}}_9{=\mathrm{Z}}_8$$

(19)

Finally, the proposed control technique is depicted in Figure 4. It permits the self-balancing of capacitors voltages in open loop operation.

2.3. Proposed Nine-Level Inverter Using Hysteresis Control

The proposed control technique is based on the eight band hysteresis approach, when the current error Δi is negative. The positive voltages (sector A in Figure 5) are applied. Inversely, the negative voltages (sector B) are applied when the current error is positive. Δi is the difference between actual load current and its reference.

The nine states and their transition conditions are depicted in Figure 6. Switch pulses are presented in the following order S1i. S2i. S3i. S4i. S5i. S6i. S7i. S8i. S9i (i = a, b, c).

3. Results

Simulation of the proposed SPUC-NPC three-phase, nine-level inverter was carried out in the MATLAB/SIMULINK environment.

3.1. Using PWM Technique

The parameters used for the simulation are presented in

Table 2. Simulation parameters.

Parameter	Value
Switching frequency	1000 Hz
E (DC source voltage)	800 V
Load resistor	30 Ω
Load inductance	15 mH
Auxiliary DC bus capacitor	4000 µF
Amplitude modulation index	m = 0.75

:

As shown in Figure 7, capacitors voltages are respectively well balanced and remain in steady state around the half of the DC source voltage for Vc1 and Vc2. However capacitor voltages of the three phases (a, b, and c) which are Vc3i, Vc4i, and Vc5i (i = a, b, c) are maintained in E/2 for capacitor 3 and the eighth of the DC source for capacitors 4 and 5.

Figure 8a shows the inverter output voltage waveform. The latter is constituted of nine voltage levels, which are {400 V; 300 V; 200 V; 100 V; 0; −100 V; −200 V; −300 V; −400 V}. However, the load current is nearly sinusoidal as is presented in Figure 8c. This waveform is obtained without using any active or reactive filter. Moreover, no sensor or closed loop is used, which permits a low inverter and installation cost.

A very low THD is achieved. The THD level of the proposed three-phase, nine-level inverter is 16.36% for output voltage (Figure 8b) and 4.39% for output current waveform (Figure 8d). Although this value fulfills standards, it can be reduced by increasing the modulating signal frequency or amplitude modulation index, and to prove this, another simulation is done using 2000 Hz as the switching frequency, with the other parameters kept at the same values; Figure 9 shows simulation results.

The proposed concept is verified against a load resistance change. Therefore, at t = 5 s, load resistance changes from 30 Ω to 15 Ω. Other parameters keep the same values, which are 800 V for DC link and 15 mH for load inductance.

Simulation results show that capacitors voltages keep the same values, even after a severe load change. In fact, Vc1 and Vc2 are fixed in the half of the DC source. However, others capacitors remain well maintained around the half of the DC link for Vc3i and the eighth of the DC source for Vc4i and Vc5i (i = a, b, c). Figure 10 shows capacitors voltages against step load change.

The load voltage behavior before and after load change is depicted in Figure 11a. The balancing technique operates very well even during load change. Figure 11b shows load current behavior before and after load change. The current remains nearly sinusoidal even during load change, which reflects the high dynamics of the proposed algorithm.

3.2. Using Hysteresis Control

Simulation was performed using parameters depicted in

Table 3. Simulation parameters.

Parameters	Value
Hysteresis bandwidth	0.25
E (DC source voltage)	600 V
Load resistor	30 Ω
Load inductance	15 mH
Auxiliary DC bus capacitor	4000 µF

.

As shown in Figure 12, the capacitors are seen to have reached their desired voltage values, thus Vc1 and Vc2 are fixed around the half of the DC source. However, Vc3i, Vc4i, and Vc5i (i = a, b, c) are balanced, respectively, to E/2, E/8, and E/8. The same results are obtained for the three phases. No voltage sensor or closed loop is needed.

As shown in Figure 13a, the output voltage consists of nine voltage levels, and 15.19% is the THD level detected as being presented in Figure 13b. However, the load current is nearly sinusoidal as is presented in Figure 13c, with 1.96% as THD level (Figure 13d), the output line-to-line voltage and its THD level are presented in Figure 14.These waveforms are obtained without using any active or reactive filter. Moreover, no voltage sensor or PI regulator is used which permits a low inverter and installation cost. The THD level can be reduced by reducing the hysteresis bandwidth. The nine switching patterns are presented in Figure 15.

In order to verify the high dynamics of the proposed system, a load resistance change is applied at t = 5 s. In fact, resistance is changed from 60 Ω to 30 Ω. Other parameters keep the same values.

Capacitors voltages are well maintained around the desired value, even after a severe load change. In fact Vc1 and Vc2 are fixed in the half of the DC source. However, other capacitors are maintained around the half of the DC link for Vc3i and the eighth of the DC source for Vc4i and Vc5i (i = a, b, c). Figure 16 shows the capacitors voltages against step load change.

As shown in Figure 17, before and after the change, the load voltage is constituted of nine levels with the same step, which is 75 V. By the same way, load current is nearly sinusoidal before and after the change, which reflects the high dynamics of the proposed system.

4. Comparative Study

Table 4. THD level voltage comparison.

Amplitude Modulation Index	Inverters	THD Level %
		1000 Hz	2000 Hz	5000 Hz
m = 1.15	Proposed Inverter	14.05	13.32	13.27
m = 1	Proposed Inverter	14.27	13.51	13.4
	9-Level, Three-Phase Reversing Voltage [21]	N.C	N.C	16.30
	Three-Phase, 9-Level Inverter with Reduced Switching Devices [22]	14.35	N.C	N.C
	Three-Phase, 9-level Cascaded MLI with less switches [23]	N.C	N.C	13.72
m = 0.9	Proposed Inverter	15.12	14.02	13.8
	3-Phase, Nine-Level Diode Clamped Inverter [24]	14.32	14.09	N.C
	Asymmetric Three-Phase Cascading Trinary-DC Source [25]	N.C	16.06	N.C
	Three-Phase, 9-Level Inverter with Reduced Switching Devices	15.27	N.C	N.C
m = 0.85	Proposed Inverter	15.41	14.60	14.22
	Asymmetric Three-Phase Cascading Trinary-DC Source	N.C	17.39	N.C
m = 0.75	Proposed Inverter	16.36	15.73	15.17

N.C = Not calculated.

compares the THD level of output voltage with other topologies by varying the switching frequency and amplitude modulation index, and we observe that the proposed topology has a low THD level without the need of any filters; however,

Table 5. Comparison of switching components.

Inverters	Switches	Clamping Diodes	Capacitors	DC Source
Diode clamped	48	168	NA	8
Flying capacitor	48	NA	84	8
H-Bridge	48	NA	NA	12
PUC	24	NA	6	3
Proposed inverter	27	NA	11	1

presents a comparison of switching components, and the comparison includes basic topologies and the PUC inverter, as can be seen, the SPUC-NPC three-phase, nine-level inverter has a significant advantage other than the use of a limited number of power components, which is the implementation of one DC source, and other capacitors voltages are balanced without the use of any closed loop regulation and with two control methods, which are PWM techniques and hysteresis control.

5. Conclusions

A novel three-phase inverter using only nine power switches and three capacitors per phase has been presented in this paper. The proposed topology is able to generate nine levels at the output voltage while using a single DC source. The self-balancing of capacitors voltages is achieved with two control methods, which are PMM techniques and hysteresis control. No filters or PI regulators are used, which permits a low inverter and installation cost. The high dynamics of the proposed inverter was verified by simulation.