Voltage Multiplier with High Input/Output Voltage Gain from Center-Tap Rectifier-Voltage Tripler and Quadrupler

Abstract

This paper proposes new rectifiers in the center-tap transformer to provide higher input/output (I/O) voltage gain with an equal transformer turns-ratio in the LLC resonant converter: a voltage tripler rectifier and a voltage quadrupler rectifier, which have simple structures with one capacitor and two diodes, and three and four times higher I/O voltage gain than a center-tap rectifier, respectively. Each rectifier is compared in terms of the transformer turns-ratio and the magnetizing offset current, and the voltage and current stresses in the capacitors and diodes. The validity of these proposed rectifiers in the half-bridge (HB) LLC resonant converter is confirmed by the experimental results from a 100 V/200 W output prototype.

1. Introduction

The center-tap rectifier (CTR) without an output inductor is widely used in many switching converters in low output-voltage and high output-current applications, since it has a simple structure, low voltage stresses, and small conduction losses resulting from two diodes in the secondary side. The asymmetric/symmetric half-bridge (HB) and full-bridge (FB) converters with pulse-width modulation (PWM) control and resonant converters with pulse-frequency modulation (PFM) control normally adopt the CTR for the DC/DC power conversion. The CTR has many advantages, such as a simple structure, low component count, and flexibility in designing an asymmetric turns-ratio between the secondary turns. However, it has a limitation in making high input/output (I/O) voltage gain, due to a disadvantageous transformer turns-ratio. For example, if an HB LLC resonant converter, as shown in Figure 1a, operates in a resonant region, the voltage (V_M) on the magnetizing inductor (L_M) of the center-tap transformer is half of the input voltage (V_S/2), and is transferred to the output (V_O) through the transformer turns-ratio (n), i.e., V_O = V_S/(2n), i.e., n = N_P/N_S.

To relieve this drawback, the voltage doubler rectifier (VDR) in Figure 1b is frequently used in many applications requiring a higher transformer turns-ratio (n). For example, if an HB LLC resonant converter with the VDR operates in a resonant region, the voltage (V_M) on the magnetizing inductor (L_M) of the transformer with the VDR is half of the input voltage (V_S/2), and is transferred to the voltage (V_D) on a doubler capacitor (C_D) through the transformer turns-ratio (n), i.e., V_D = V_S/(2n). Since the output voltage (V_O) is the sum of V_D and the voltage (V_NS) across the secondary turn (N_S), i.e., V_NS = V_S/(2n) and V_O = V_D + V_NS, V_O is V_S/n, which means that n can be doubled, compared with the center-tap transformer in Figure 1a.

In addition, there are several approaches to obtain a higher I/O voltage gain [1,2,3,4,5,6,7,8].

Table 1. Comparisons with prior arts.

	[1]	[2]	[3]	[4]	[5]
Semiconductor Devices	Switch: 3EA Diode: 3EA Inductor: 1EA Capacitor: 1EA Total: 8EA	Switch: 3EA Diode: 4EA Inductor: 1EA Capacitor: 1EA Total: 9EA	Switch: 2EA Diode: 2EA Inductor: 1EA Capacitor: 1EA Total: 6EA	Switch: 3EA Diode: 3EA Inductor: 1EA Capacitor: 1EA Total: 8EA	Switch: 3EA Diode: 4EA Inductor: 2EA Capacitor: 2EA Total: 11EA
Transformer Offset-Current	Exist	Exist	Exist	None	None
Additional Control	On/Off Control	PWM Control	PWM Control	On/Off Control	On/Off/PWM Controls
	[6]	[7]	[8]	Proposed Rectifiers
				Tripler	Quadrupler
Semiconductor Devices	Switch: 4EA Diode: 2EA Inductor: 1EA Capacitor: 1EA Total: 8EA	Switch: 3EA Diode: 2EA Inductor: 1EA Capacitor: 2EA Total: 8EA	Switch: 4EA Diode: 2EA Inductor: 1EA Capacitor: 2EA Total: 9EA	Switch: 2EA Diode: 2EA Inductor: 1EA Capacitor: 2EA Total: 7EA	Switch: 2EA Diode: 2EA Inductor: 1EA Capacitor: 2EA Total: 8EA
Transformer Offset-Current	None	None	None	Exist (Small)	None
Additional Control	Phase Control	On/Off Control	PWM Control	None	None

shows comparisons with “prior arts.” In column [1] of Table 1, the HB LLC resonant converter can achieve a higher I/O voltage gain by increasing the transformer secondary turns. However, it utilizes one additional diode and switch, and additional transformer secondary windings, which cause circuit complexity. Moreover, in the mode of increasing I/O voltage gain, the offset current in the transformer occurs due to the primary unbalanced current, which results from only one powering operation in the secondary side. The offset current in the transformer causes the size of the transformer to be increased. In column [2] of Table 1, the HB LLC converter with a boost pulse-width modulation (PWM) control method is proposed. In the mode of increasing I/O voltage gain, the added switch is turned on or off with PWM control. While the added switch is turned on, the energy stored in the resonant capacitor (C_r) is stored in the resonant inductor (L_r) by the resonance between L_r and C_r. Meanwhile, if the added switch is turned off, the energy stored in L_r is transferred to the output through the transformer; thus, a higher I/O voltage gain can be obtained. However, one additional switch is needed, and the additional switch cannot be clamped due to the leakage inductor of the transformer, which has high voltage stress. Moreover, as in column [1] in Table 1, the offset current in the transformer occurs due to the primary unbalanced current, which results from only one powering operation in the secondary side. This increases the transformer size. In column [3] of Table 1, the HB LLC converter with the asymmetric PWM control method is proposed. This paper does not consider additional devices in order to obtain higher I/O voltage gain. However, in a situation of obtaining higher I/O voltage gain, asymmetric PWM control is used. Since it causes “only one powering operation during small duty-cycle” in one switching period, the primary current becomes unbalanced; thus, the offset current in the transformer occurs. The offset current in the transformer causes the size of the transformer to be increased, similar to [1,2].

In column [4] of Table 1, a boost converter, which is utilized as a power factor correction (PFC) stage, is used to obtain higher I/O voltage gain. For higher I/O voltage gain, the boost inductor (L_B) in the PFC stage is replaced with a coupled inductor with secondary winding in the secondary side of the DC/DC stage, and one diode (D_A) and switch (Q_A) are added in the secondary side of the DC/DC stage. In a situation of obtaining higher I/O voltage gain, the HB flyback converter with a single-ended rectifier is operated with a coupled inductor in the PFC stage and one diode and switch in the secondary side, finishing the operation of main HB LLC converter. This does not have offset current in the transformer, but too many components would be additionally required. In column [5] of Table 1, the HB LLC converter is proposed with additional “one primary switch (Q_A)” and “one resonant tank”, including one transformer and a resonant inductor and a capacitor. If higher I/O voltage gain is required, an additional primary switch (Q_A) is always turned on, and Q_P1 and Q_P2 are alternatively switched. In this case, since the input voltage (V_S) is applied to each transformer in two “parallel-connected” resonant tanks, high I/O voltage gain can be obtained. Meanwhile, if Q_P1 and Q_P2 are together turned on or off, alternatively with Q_A, two transformers in two resonant tanks are connected in series. Since half (V_S/2) of the input voltage is applied to each transformer, low I/O voltage gain is achieved. This does not have offset current in the transformer, but too many components would be additionally required. In column [6] of Table 1, the HB LLC converter is proposed by “replacing two diodes with two switches” and “applying phase-shifted control” in the secondary full-bridge rectifier. If higher I/O voltage gain is needed, the phase-shifted control between the primary switches (Q₁ and Q₂) and the secondary switches (SR₁ and SR₂) is applied. Since the energy stored in a resonant inductor (L_r) is further increased, as the free-wheeling period in the secondary side is larger, higher I/O voltage gain can be achieved. However, this cannot be applied in a center-tapped rectifier, but only in a full-bridge rectifier. Moreover, this requires two additional secondary switches. In column [7] in Table 1, the HB LLC converter is proposed by “adding one switch (Q_A) and one resonant capacitor (C_RA)”. If higher I/O voltage gain is required, the additional switch is turned on; thus, the resonant capacitance is increased. Since Q factor is reduced, higher I/O voltage gain can be achieved. However, this requires additional on/off control and additional devices, which cause the complexity of the system. In column [8] of Table 1, the HB LLC converter is proposed by “replacing two diodes with two switches (Q_SR1 and Q_SR2)” and “adding one blocking capacitor (C_B)” in the secondary full-bridge rectifier. In the “normal full-bridge control” in the secondary side, an additional blocking capacitor (C_B) has only a function of current-balancing during the resonant region operation. Meanwhile, if higher I/O voltage gain is needed, low-side switches in the secondary full-bridge legs are both turned on. During this period, an additional blocking capacitor (C_B) stores V_S/(2 × n), where Vs and n, respectively, indicate the input voltage and the transformer turns-ratio. Then, the V_S/(2 × n) stored in the C_B is transferred to the output, with the transformer voltage reflected in the secondary side, i.e., V_S/(2 × n). Thus, the proposed converter in column [8] of Table 1 can obtain higher I/O voltage gain. However, this requires complex secondary gate control and two switches, which cannot be applied in a center-tapped rectifier but only in a full-bridge rectifier.

In this paper, new rectifiers to obtain higher voltage gain are proposed; a voltage tripler rectifier and a voltage quadrupler rectifier, which require one more capacitor in the secondary side compared with the CTR, or no elements compared with the VDR. Moreover, compared with columns [1,2,4,5,6,7,8] in Table 1, the proposed rectifiers can achieve high I/O voltage gain with “smaller number of elements.” In addition, although the proposed voltage tripler has a “transformer offset current,” it has a very small transformer offset current compared with columns [1,2,3] in Table 1, due to the “large transformer turns-ratio” resulting from higher I/O voltage gain. Meanwhile, the proposed voltage quadrupler has no transformer offset current. As a result, the proposed rectifiers can have a small volume, due to the low component count and the small-sized transformer, compared with prior arts. They have a simple structure with one capacitor and two diodes, and three and four times higher voltage gain with the same transformer turns-ratio.

The validity of these proposed rectifiers in the half-bridge (HB) LLC resonant converter is verified by the experimental results from a 100 W/200 V output prototype.

2. Comparison and Analysis

Figure 1 shows the circuit diagram of the conventional and proposed rectifiers. Figure 1a,b show the CTR and VDR, respectively. The CTR in Figure 1a has two secondary turns (N_S1 and N_S2), and two diodes are series-connected to each turn.

Meanwhile, the VDR in Figure 1b has a secondary turn (N_S), and the doubler capacitor (C_D) is series-connected to that. If the secondary current (i_Sec) reflected from the primary flows in the secondary undot direction, the secondary diode (D_S2) is conducted. During this interval, assuming resonant operation, since half of the input voltage (V_S/2) is applied to L_M in the primary undot direction, V_S/(2n) is applied to N_S in the undot direction, and the voltage (V_D) on C_D is V_S/(2n). Since V_O is V_S/n in the VDR in resonant operation, as explained in Section 1, V_D is V_O/2, i.e., V_D = V_S/(2n) = V_O/2. On the other hand, if the secondary current (i_Sec) reflected from the primary flows in the secondary dot direction, the secondary diode (D_S1) is conducted, and the i_sec flows through N_S, D_S1, and C_D. During this interval, assuming resonant operation, since half of the input voltage (V_S/2) is applied to L_M in the primary dot direction, V_S/(2n) is applied to N_S in the dot direction. Since the output voltage (V_O) is the sum of V_D and the voltage (V_NS) across the secondary turn (N_S), i.e., V_NS = V_S/(2n) and V_O = V_D + V_NS, V_O is V_S/n. Thus, two times higher input/output (I/O) voltage gain can be achieved with an equal turns-ratio, compared with the CTR in Figure 1a.

On the other hand, Figure 1c and Figure 1d show the proposed voltage tripler and quadrupler, respectively, and Figure 2 shows their operational modes. To achieve higher I/O voltage gain, the proposed rectifier has new secondary windings from the VDR.

The voltage tripler has a new N_S2, which is series-connected with D_S2. If the secondary current (i_Sec) reflected from the primary flows in the secondary undot direction, the secondary diode (D_S2) is conducted, and the secondary current flows through N_S1, C_D, D_S2, and N_S2, as shown in Figure 2a. During this interval, assuming resonant operation, since half of the input voltage (V_S/2) is applied to L_M in the primary undot direction, V_S/(2n) is applied, respectively, to N_S1 and N_S2 in the undot direction, and the voltage (V_D) on C_D is V_S/n. On the other hand, if the secondary current (i_Sec) reflected from the primary flows in the secondary dot direction, the secondary diode (D_S1) is conducted, the i_sec flows through N_S1, D_S1, and C_D., and D_S2 is blocked, as shown in Figure 2b. During this interval, assuming resonant operation, since half of the input voltage (V_S/2) is applied to L_M in the primary dot direction, V_S/(2n) is applied to N_S1 in the dot direction. Since the output voltage (V_O) is the sum of V_D and the voltage (V_NS1) across the secondary turn (N_S1), i.e., V_NS1 = V_S/(2n) and V_O = V_D + V_NS1, V_O is 3V_S/(2n). That is, since V_D is V_S/n, V_D is equal to 2V_O/3.

The voltage quadrupler is operated similarly to the voltage tripler. It has new windings N_S2 and N_S3, which are series-connected with D_S2 and D_S1, respectively. If the secondary current (i_Sec) reflected from the primary flows in the secondary undot direction, the secondary diode (D_S2) is conducted, and the secondary current flows through N_S1, C_D, D_S2, and N_S2, as shown in Figure 2c. During this interval, assuming resonant operation, since half of the input voltage (V_S/2) is applied to L_M in the primary undot direction, V_S/(2n) is respectively applied to N_S1 and N_S2 in the undot direction, and the voltage (V_D) on C_D is V_S/n. On the other hand, if the secondary current (i_Sec) reflected from the primary flows in the secondary dot direction, the secondary diode (D_S1) is conducted, the i_sec flows through N_S1, N_S3, D_S1, and C_D., and D_S2 is blocked, as shown in Figure 2d. During this interval, assuming resonant operation, since half of the input voltage (V_S/2) is applied to L_M in the primary dot direction, V_S/(2n) is respectively applied to N_S1 and N_S3 in the dot direction. Since the output voltage (V_O) is the sum of V_D and voltages (V_NS1 and V_NS3) across the secondary turns (N_S1 and N_S3), i.e., V_NS1 = V_NS3 = V_S/(2n) and V_O = V_D + V_NS1 + V_NS3, V_O is 2V_S/n. That is, since V_D is V_S/n, V_D is equal to V_O/2.

Consequently, in the proposed voltage tripler and quadrupler, three and four times higher input/output (I/O) voltage gain can be achieved with an equal turns-ratio, compared with the CTR shown in Figure 1a.

Table 2. Comparison of conventional and proposed rectifiers in turns-ratio (n) and secondary capacitor (C_D).

Types of Rectifier	Turns-Ratio	Capacitor (CD)
		Voltage Stress	Current
			Peak	RMS
×1-Rectifier (Center-tap)	n:1:1	-	-	-
×2-Rectifier (Voltage doubler)	n:(1/2)	VO/2	πIO	$\mathsf{\pi }{\mathrm{I}}_{\mathrm{O}}\sqrt{2}$/2
×3-Rectifier (Voltage tripler)	n:(1/3):(1/3)	2VO/3	πIO	$\mathsf{\pi }{\mathrm{I}}_{\mathrm{O}}\sqrt{2}$/2
×4-Rectifier (Voltage quadrupler)	n:(1/4):(1/4)	VO/2	πIO	$\mathsf{\pi }{\mathrm{I}}_{\mathrm{O}}\sqrt{2}$/2

and

Table 3. Comparison of conventional and proposed rectifiers in secondary diodes (D_S1 and D_S2).

Types of Rectifier	Turns-Ratio	Diodes (DS1 and DS2)
		Voltage Stress		Current
		DS1	DS2	Peak	Average
×1-Rectifier (Center-tap)	n:1:1	2VO		πIO/2	IO/2
×2-Rectifier (Voltage doubler)	n:(1/2)	VO		πIO	IO
×3-Rectifier (Voltage tripler)	n:(1/3):(1/3)	2VO/3	4VO/3	πIO	IO
×4-Rectifier (Voltage quadrupler)	n:(1/4):(1/4)	VO		πIO	IO

show the comparison of rectifiers in terms of the transformer turns-ratio, the voltage and RMS current of C_D, and the voltage and current stresses of D_S1 and D_S2. It is assumed that the HB LLC resonant converter operates in a resonant region, the diodes (D_S1 and D_S2) have the same conduction time, N_P is the transformer primary turns, and the rectifiers have equal output voltage (V_O) and output current (I_O).

2.1. Transformer Turns-Ratio and Magnetizing Offset Current

Since the I/O voltage gains of the conventional CTR and VDR and the proposed tripler and quadrupler rectifiers are, respectively, V_S/(2n), V_S/n, 3V_S/(2n), and 2V_S/n, the turns-ratios (n = N_P/N_Sk, k = 1, 2, 3) of the VDR and the tripler and quadrupler rectifiers are 2, 3, and 4, respectively, under n = 1 in the CTR. Thus, a larger turns-ratio (n = N_P/N_S) is required to obtain the same output voltage in the proposed tripler and quadrupler, compared with the CTR and the VDR.

Meanwhile, in the HB LLC resonant converter with the CTR, the secondary resonant current is flowing alternately in the secondary dot or undot direction during half of a switching period (T_S/2), and their average should be the output current (I_O). Thus, each average of the i_Sec flowing in the secondary dot or undot direction should be half of the output current (I_O/2). If the i_sec is reflected in the primary side of the transformer, each average of the reflected primary current (i_Pri,_Rf) is I_O/(2n) or −I_O/(2n) during T_S/2, as shown in Figure 3a. Due to the current-second balance on the primary resonant capacitor, the transformer magnetizing offset current is zero in the CTR. In Figure 3, M₁ and M₂, respectively, indicate operational modes 1 and 2.

Second, in the VDR, the secondary resonant current, which only flows in the secondary dot direction, is transferred to the output through C_D during T_S/2, and its average should be the output current (I_O). Meanwhile, the secondary resonant current, flowing in the secondary undot direction, does not pass through the output, but through C_D and D_S2. Due to the current-second balance on C_D, its average should be −I_O during the undot-direction operation. If the i_sec is reflected in the primary side of the transformer, each average of the reflected primary current (i_Pri,_Rf) is I_O/n or −I_O/n during T_S/2, as shown in Figure 3b. Due to the current-second balance on the primary resonant capacitor, the transformer magnetizing offset current is also zero in the VDR.

Third, in the proposed tripler rectifier, the secondary resonant current (i_Sec = i_DS1), which only flows in the secondary dot direction of N_S1, is transferred to the output through C_D and D_S1 during T_S/2, as shown in Figure 2b, and its average should be the output current (I_O), as shown in Figure 3c. Meanwhile, the secondary resonant current, flowing in the secondary undot direction of N_S1 and N_S2, does not pass through the output, but through C_D and D_S2, as shown in Figure 2a. Due to the current-second balance on C_D, its average should be −I_O during the undot-direction operation. If the i_sec is reflected in the primary side of the transformer, the average of the reflected primary current (i_Pri,_Rf) in the dot direction is I_O/n, and the average of i_Pri,_Rf in the undot direction is −2I_O/n, as shown in Figure 3c. Due to the current-second balance on the primary resonant capacitor, the transformer magnetizing offset current is I_O/n in the proposed tripler rectifier.

Fourth, in the proposed quadrupler rectifier, the secondary resonant current (i_Sec = i_DS1), which only flows in the secondary dot direction of N_S1 and N_S3, is transferred to the output through C_D and D_S1 during T_S/2, as shown in Figure 2d, and its average should be the output current (I_O), as shown in Figure 3d. Meanwhile, the secondary resonant current, flowing in the secondary undot direction of N_S1 and N_S2, does not pass through the output, but through C_D and D_S2, as shown in Figure 2c. Due to the current-second balance on C_D, its average should be −I_O during the undot-direction operation. If the i_sec is reflected in the primary side of the transformer, each average of the reflected primary current (i_Pri,_Rf) is 2I_O/n or −2I_O/n during T_S/2, as shown in Figure 3d. Due to the current-second balance on the primary resonant capacitor, the transformer magnetizing offset current is also zero in the proposed quadrupler rectifier.

2.2. Voltage and Current Stress on C_D

As explained in Section 2, in the VDR, and in the proposed tripler and quadrupler rectifiers, each voltage (V_D) on the secondary capacitor (C_D) is V_O/2, 2V_O/3, and V_O/2, respectively.

Meanwhile, in the VDR and the proposed tripler and quadrupler rectifiers, as explained in Section 2.1, if the secondary resonant current only flows in the secondary dot direction, the secondary resonant current is transferred to the output during T_S/2. Assuming resonant operation, its average should be the output current (I_O), and the peak (i_Sec,_Pk) of the secondary resonant current can be obtained as πI_O from Equation (1), in the VDR and in the proposed tripler and quadrupler rectifiers. Since the secondary resonant current (i_Sec) flows through C_D, the current stress on C_D is πI_O.

$${\mathrm{I}}_{\mathrm{O}}=\frac{1}{2\mathsf{\pi }}{{\displaystyle \int }}_0^{\mathsf{\pi }}{\mathrm{i}}_{\mathrm{Sec},\mathrm{pk}}\sin \left(\mathrm{wt}\right)\mathrm{d}\left(\mathrm{wt}\right)$$

(1)

Moreover, due to the current-second balance on C_D, the secondary resonant current (i_Sec) can be expressed as πI_O×sin(wt) during a period; thus, the rms current on C_D is πI_O/(2)^0.5, in the VDR and in the proposed tripler and quadrupler rectifiers.

2.3. Voltage and Current Stress on D_S1 and D_S2

The voltage stress on a diode is determined when a diode is blocked.

In the CTR, if the secondary current (i_Sec) reflected from the primary flows in the secondary dot direction, D_S1 is conducted and D_S2 is blocked. Thus, the voltage across N_S1 is the output voltage (V_O), and the voltage stress on D_S2 is 2V_O by the secondary turns-ratio of the transformer, assuming N_S1 = N_S2. In the opposite situation, the voltage stress on D_S1 is 2V_O. Moreover, the secondary resonant current is twice transferred to the output during a period. Assuming resonant operation, its average should be the output current (I_O), and the peak (i_Sec,_Pk) of the secondary resonant current can be obtained as πI_O/2 from Equation (2).

$${\mathrm{I}}_{\mathrm{O}}=\frac{1}{\mathsf{\pi }}{{\displaystyle \int }}_0^{\mathsf{\pi }}{\mathrm{i}}_{\mathrm{Sec},\mathrm{pk}}\sin \left(\mathrm{wt}\right)\mathrm{d}\left(\mathrm{wt}\right)$$

(2)

Since the secondary resonant current (i_Sec) flows through D_S1 or D_S2, the current stress on D_S1 and D_S2 is πI_O/2.

In the VDR, if the secondary current (i_Sec) reflected from the primary flows in the secondary dot direction, D_S1 is conducted and D_S2 is blocked. Thus, the voltage stress on D_S2 is V_O. On the other hand, if the secondary current (i_Sec) reflected from the primary flows in the secondary undot direction, D_S2 is conducted and D_S1 is blocked. Thus, the voltage stress on D_S1 is V_O.

In the proposed tripler rectifier, if the secondary current (i_Sec) reflected from the primary flows in the secondary dot direction, D_S1 is conducted and D_S2 is blocked. Since V_D is 2V_O/3, the voltage (V_NS1) across N_S1 is V_O/3. Assuming N_S1 = N_S2, the voltage (V_NS2) across N_S2 is V_O/3 in the dot direction; thus, the voltage stress on D_S2 is 4V_O/3. Meanwhile, if the secondary current (i_Sec) reflected from the primary flows in the secondary undot direction, D_S2 is conducted and D_S1 is blocked. Due to V_D = 2V_O/3, and assuming N_S1 = N_S2, the voltage (V_NS2) across N_S2 is V_O/3 in the undot direction by the secondary turns-ratio of the transformer; thus, the voltage stress on D_S1 is 2V_O/3.

In the proposed quadrupler rectifier, if the secondary current (i_Sec) reflected from the primary flows in the secondary dot direction, D_S1 is conducted and D_S2 is blocked. Since V_D is V_O/2, the voltages (V_NS1, V_NS2, and V_NS3) across N_S1, N_S2, and N_S3 are V_O/4 in the dot direction by the secondary turns-ratio of the transformer, assuming N_S1 = N_S2 = N_S3. As a result, the voltages (V_NS2 and V_NS3) across N_S2 and N_S3 are cancelled, and the voltage stress on D_S2 is V_O. Meanwhile, if the secondary current (i_Sec) reflected from the primary flows in the secondary undot direction, D_S2 is conducted and D_S1 is blocked. Due to V_D =V_O/2, and assuming N_S1 = N_S2 = N_S3, the voltages (V_NS1, V_NS2, and V_NS3) across N_S1, N_S2, and N_S3 are V_O/4 in the undot direction by the secondary turns-ratio of the transformer. As a result, the voltages (V_NS2 and V_NS3) across N_S2 and N_S3 are cancelled, and the voltage stress on D_S1 is V_O.

On the other hand, in the VDR and in the proposed tripler and quadrupler rectifiers, due to once powering in a switching period, as explained in Section 2.2, the average currents on D_S1 and D_S2 are I_O, and they are increased two times compared with that (I_O/2) in the CTR. Moreover, since the secondary resonant current (i_Sec) flows through D_S1 or D_S2, the current stresses on D_S1 or D_S2 are πI_O, which is equal to the current stress on C_D. Consequently, the multipliers have lower voltage stress and higher current stress than the CTR.

3. Design Guideline of Proposed Rectifiers

3.1. Design of Transformer Turns-Ratio

The I/O voltage gain (M = V_O/V_S) of the proposed voltage tripler is 3/(2n) at resonant frequency, as mentioned in Section 2, Comparison and Analysis. Since “the input voltage (V_S) and output voltage (V_O) are, respectively, 400 V and 100 V” and “the highest efficiency is indicated at resonant frequency,” n is 6.

Meanwhile, the I/O voltage gain (M = V_O/V_S) of the proposed voltage quadrupler is 2/n at resonant frequency, as mentioned in Section 2, Comparison and Analysis. Since “the input voltage (V_S) and output voltage (V_O) are, respectively, 400 V and 100 V” and “the highest efficiency is indicated at resonant frequency,” n is 8.

3.2. Design of Resonant Tanks (L_R, C_R, and L_M)

The voltage gain (M = V_O/V_S) of the HB LLC converter can be expressed as follows [7]:

$$\mathrm{M}=\frac{{\mathrm{V}}_{\mathrm{O}}}{{\mathrm{V}}_{\mathrm{S}}}=\frac{1}{ \mathrm{n} \prime \sqrt{{\left\{1+\frac{1}{\mathrm{k}}\left[1-{\left(\frac{{\mathrm{f}}_{\mathrm{R}}}{{\mathrm{f}}_{\mathrm{S}}}\right)}^2\right]\right\}}^2+{\left[\frac{{\mathsf{\pi }}^2\mathrm{Q}}{8{\left(\mathsf{\alpha }\mathrm{n}\right)}^2}\left(\frac{{\mathrm{f}}_{\mathrm{S}}}{{\mathrm{f}}_{\mathrm{R}}}-\frac{{\mathrm{f}}_{\mathrm{R}}}{{\mathrm{f}}_{\mathrm{S}}}\right)\right]}^2}}$$

(3)

where k = L_M/L_R, Q = (L_R/C_R)^0.5/R_O, f_R = 1/[2π(L_RC_R)^0.5], n = N_P/N_S, and f_S is the switching frequency.

Here, n’ indicates, respectively, 3/(2n) and 2/n in the proposed tripler and quadrupler rectifiers. Moreover, α indicates, respectively, 1/3 and 1/4 in the proposed tripler and quadrupler rectifiers. Assuming V_S = 400 V and V_O = 100 V, n should be 6 and 8 at resonant frequency in the proposed tripler and quadrupler rectifiers. In addition, since n′ and α × n are equal to 1/4 and 2 in both rectifiers, both voltage gains are the same.

Figure 4 shows equal voltage gain (M = V_O/V_S) in the proposed tripler and quadrupler rectifiers at full load condition, where I/O voltage gain is the lowest. Since Vs is 400 V and V_O is 100 V, the voltage gain (M) is 0.25. From Figure 4, it is noted that M is 0.25 at resonant frequency (f_R = 80 kHz). By considering “double gain margin” and frequency variation range, L_M and L_R are designed at 500 μH and 62 μH, i.e., k = L_M/L_R ≈ 8. To operate at resonant frequency (f_R = 80 kHz) for high efficiency, C_R is designed at 62nF, i.e., f_R = 1/[2π(L_RC_R)^0.5] ≈ 80 kHz.

3.3. Design of Main Transformer

The core area (A_C) is included in L_M·i_LM,_Max = N_P·B_Max·A_C, where i_LM,_Max is the maximum magnetizing inductor current, N_P is the primary turns of the transformer, and B_Max is the maximum flux density.

In the tripler rectifier, since the voltages (V_D and V_NS1) on C_D and secondary turns (N_S1) are 2V_O/3 and V_O/3 during 0.5 T_S of undot direction operation in Figure 2a, the voltage (V_M) on the magnetizing inductor (L_M) is nV_O/3; thus, the ripple (∆i_LM) of the magnetizing inductor current is nV_O/(6·L_M·F_S). Meanwhile, the tripler rectifier has a transformer magnetizing offset current (i_LM,_Offset), i.e., i_LM,_Offset = I_O/n; thus, i_LM,_Max is the sum of i_LM,_Offset and ∆i_LM/2, i.e., i_LM,_Max = i_LM,_Offset (=I_O/n) + ∆i_LM/2[=nV_O/(12·L_M·F_S)]. Generally, the transformer turns-ratio (n) of the HB LLC resonant converter with the CTR is 2, but with the proposed tripler rectifier, it is is 6. As a result, the proposed tripler rectifier has a much smaller transformer magnetizing offset current, compared with [1,2,3].

In the quadrupler rectifier, since the voltages (V_D and V_NS1) on C_D and secondary turns (N_S1) are V_O/2 and V_O/4 during 0.5 T_S of the undot direction operation, as shown in Figure 2c, the voltage (V_M) on the magnetizing inductor (L_M) is nV_O/4; thus, i_LM,_Max is nV_O/(16·L_M·F_S).

On the other hand, the window area (A_W) indicates the area to wind the primary and secondary windings. A_W can be expressed as (N_P·i_LR,_RMS + N_S1·i_NS1,_RMS + N_S2·i_NS2,_RMS)/(K_U·J) in the tripler rectifier and (N_P·i_LR,_RMS + N_S1·i_NS1,_RMS + N_S2·i_NS2,_RMS + N_S3·i_NS3,_RMS)/(K_U·J) in the quadrupler rectifier, where, respectively, i_LR,_RMS and i_NSn,_RMS mean the RMS current on the primary turns (N_P) and the secondary turns (N_Sn) in the transformer, and K_U and J mean the utilization factor of the window area and the current density of the primary and secondary wires in the transformer.

The turns-ratio (n) of the proposed tripler and quadrupler rectifiers were determined to be 6 and 8 by applying I/O voltage gain at resonant frequency. Moreover, L_M was determined to be 500μH by considering “double gain margin” and frequency variation range. Assuming N_P and A_C are 48 and 170 mm² because of V_O = 100 V and F_S = 80 kHz, the maximum flux density (B_Max) is 0.097 T and 0.077 T, respectively, in the tripler and quadrupler rectifiers, which are within the saturation flux (B_Sat), i.e., B_Sat = 0.3 T. Due to i_LM,_Offset in the tripler rectifier, B_Max in the tripler rectifier is higher. For high efficiency in high switching frequency, the variation (∆B) of the flux density, related to the core loss, is generally designed below 0.15 T. ∆B are equal to 0.153 T, because ∆i_LM in both rectifiers are equal to 2.5 A. By considering ∆B and core volume (V_e), related to the core loss, the primary turns and core of the transformer are chosen at 48 turns and PQ3220 with “A_C = 170 mm² and PL-13 material.”

Meanwhile, in the tripler and quadrupler rectifiers, the peak (i_LR,_PK) of the primary current (i_LR) is πI_in, using a relationship that the average of the input current with i_LR and 0 A in half a cycle is equal to the input current (I_in); thus, the RMS (i_LR,_RMS) of i_LR is πI_in$\sqrt{2}$/2, i.e., i_LR,_RMS = 1.11 A. In the tripler and quadrupler rectifiers, the current (i_NS1) on N_S1 is equal to that on C_D from Figure 2, and its RMS current (i_NS1,_RMS) is πI_O$\sqrt{2}$/2 from Table 2, i.e., i_NS1,_RMS = 4.44 A. Moreover, in both rectifiers, the currents (i_NS2 and i_NS3) on N_S2 and N_S3 are the same as the half-cycle shape of the current on C_D from Figure 2. As a result, their RMS currents (i_NS2,_RMS and i_NS3,_RMS) are all πI_O/2, i.e., i_NS2,_RMS = i_NS3,_RMS = 3.14 A. If K_U is 0.25 and J is 6 A/mm², A_W in the tripler and quadrupler rectifiers are, respectively, 76 mm² and 78.4 mm², which are suitable for PQ3220 with A_W = 80.8 mm².

Consequently, PQ3220 with PL-13 material, A_C = 170 mm², and A_W = 80.8 mm² was selected for the transformer in both rectifiers, by considering reasonable A_C and A_W as following

Table 4. Design parameters for transformer and resonant inductor (L_R).

Components	Proposed Voltage Tripler	Proposed Voltage Quadrupler
Ripple of magnetizing inductor current (∆iLM)	nVO/(6·LM·FS)	nVO/(8·LM·FS)
Magnetizing offset current (iLM,Offset)	IO/n	-
Maximum magnetizing inductor current (iLM,Max)	IO/n + nVO/(12·LM·FS)	nVO/(16·LM·FS)
Core Area (AC)	[LM·IO/n + nVO/(12·FS)]/(NP·BMax)	nVO/(16·FS·NP·BMax)
RMS current (iLR,RMS) on primary turns (NP)	$\mathsf{\pi }{\mathrm{I}}_{\mathrm{in}}\sqrt{2}$/2
RMS current (iNS1,RMS) on secondary turns (NS1)	$\mathsf{\pi }{\mathrm{I}}_{\mathrm{O}}\sqrt{2}$/2
RMS current (iNS2~3,RMS) on secondary turns (NS1, NS2)	πIO/2
Window Area (AW)	(NP·iLR,RMS+NS1·iNS1,RMS+NS2·iNS2,RMS)/(KU·J)	(NP·iLR,RMS+NS1·iNS1,RMS+NS2·iNS2,RMS+NS3·iNS3,RMS)/(KU·J)
Transformer	Proposed Voltage Tripler	Proposed Voltage Quadrupler
LM	500μH
n (NP:NS1:NS2:NS3)	6 (48:8:8)	8 (48:6:6:6)
AC (PQ3220)/BMax/∆B	170 mm2/0.097 T/0.153 T	170 mm2/0.077 T/0.153 T
AW	76 mm2	78.4 mm2

.

4. Experimental Results

To verify the operation and analysis of the proposed rectifiers, the prototype was implemented using the half-bridge (HB) LLC resonant converter with the proposed voltage tripler and quadrupler rectifiers.

Table 5. Specifications and components used in experimental prototype.

Specifications	Proposed Voltage Tripler	Proposed Voltage Quadrupler
Input Voltage (VS)	400 [VDC]
Output Voltage (VO)	100 [VDC]
Output Power (PO)	200 [W] (Rated Load Resistance (RO) = 50 [Ω])
Switching Frequency (FS)	80 [kHz]
Components	Proposed Voltage Tripler	Proposed Voltage Quadrupler
Primary switches (QP1 and QP2)	IPP60R385CP (650 [V]/9 [A]/385 [mΩ])
Transformer	PQ3220(PL-13) • LM: 500 [μH], Llkg: 32 [μH] • Turns-ratio: 48:8:8 (n = 6) • Primary Winding: 0.5[mm] • Secondary Winding: 1 [mm](NS1), 0.8 [mm](NS2)	PQ3220(PL-13) • LM: 500 [μH], Llkg: 38 [μH] • Turns-ratio: 48:6:6:6 (n = 8) • Primary Winding: 0.5[mm] • Secondary Winding: 1 [mm](NS1), 0.8 [mm] (NS2, NS3)
Resonant inductor (LR)	PQ2016(PL-13) • LR: 30 [μH] • Number of Turns: 5 • Winding: 0.5 [mm]	PQ2016(PL-13) • LR: 24 [μH] • Number of Turns: 5 • Winding: 0.5 [mm]
Resonant capacitor (CR)	62 [nF] (KEMET) R76MF2470 (400 [V]/47 [nF]) + R76MF2150 (400 [V]/15 [nF])
Secondary diode (DS1)	V20100C (100 V/20 A/0.58 V)	V20150C (150 V/20 A/0.69 V)
Secondary diode (DS2)	V20200C (200 V/20 A/0.68 V)
Secondary capacitor (CD)	24 [μF] (KEMET) R76IW5120 (250 [V]/12 [μF]) × 2 [EA]
Experimental Stresses	Proposed Voltage Tripler	Proposed Voltage Quadrupler
Secondary diode (DS1)	Steady-State: 67 [V] (= 2VO/3) Maximum: 73[V]	Steady-State: 100 [V] (= VO) Maximum: 140 [V]
Secondary diode (DS2)	Steady-State: 134 [V] (= 4VO/3) Maximum: 157 [V]	Steady-State: 100 [V] (= VO) Maximum: 137 [V]

and Figure 5 show the experimental specifications, components, and circuits with used parameters of each component. The specifications are 400 V input and 100 V/200 W output. The transformer turns-ratios are 48:8:8, and 48:6:6:6 for the voltage tripler and quadrupler, respectively. From Table 2, it is noted that the number of the secondary turns between the voltage tripler and quadrupler is three-fourths different, under the same primary turns.

Figure 6 and Figure 7 show the experimental waveforms based on the realized H/W of the primary current (i_LR), and the voltages (V_DS1 and V_DS2) and currents (i_DS1 and i_DS2) of the secondary diodes in the voltage tripler and quadrupler, respectively.

The voltage tripler has asymmetric waveform in the primary current (i_LR), due to the magnetizing offset current about 0.33A (= I_O/n), as shown in Figure 6a. This results from operations shown in Figure 2a,b. During “undot direction like Figure 2a” and “dot direction like Figure 2b,” −2I_O/n and I_O/n are on average reflected to the primary side, respectively. In addition, “initial resonant currents” in i_LR are different at 1.8 A and −1.2 A, as shown in Figure 6a, due to the magnetizing offset current. This results in “below or above operation” alternatively in a switching period. However, the primary current (i_LR) is symmetrical, due to there being no magnetizing offset current in the voltage quadrupler, as shown in Figure 7a. This results from the operations, as shown in Figure 2c,d. During “undot direction like Figure 2c” and “dot direction like Figure 2d,” −2I_O/n and 2I_O/n are on average reflected to the primary side, respectively. Therefore, i_LR in Figure 6a and Figure 7a has different shapes, due to the magnetizing offset current.

On the other hand, the average and peak values of the diode currents (i_DS1 and i_DS2) are about 2A (= I_O) and 6.3A (= πI_O), which are the same in the two rectifiers, as shown in Figure 6b,c and Figure 7b,c. The voltage stresses (V_DS1 and V_DS2) of D_S1 and D_S2 in the voltage tripler are 73 V (= 2V_O/3 [=67 V] + Ringing [=6 V]) and 157 V (= 4V_O/3 [=134 V] + Ringing [=23 V]), respectively, as shown in Figure 6b,c. Those in the voltage quadrupler are 140 V (= V_O [=100 V] + Ringing [=40 V]) and 137 V (= V_O [=100 V] + Ringing [=37 V]), as shown in Figure 7b,c. The difference in the voltage stresses on the secondary diodes results from the parasitic pattern leakage inductance.

Finally, the efficiencies of the voltage tripler and quadrupler are measured at about 94.1% and 93.7% at full load condition, respectively. Figure 8 shows theoretical loss distribution in both voltage rectifiers. Both rectifiers use equal components “except for the secondary turns of the transformer and secondary diodes,” due to a very small magnetizing offset current (i_LM,_Offset = I_O/n) resulting from a large transformer turns-ratio (n), although the voltage tripler has i_LM,_Offset.

As shown in Figure 8, the voltage tripler has less conduction loss on the secondary diodes (D_S1 and D_S2). This results from the small forward voltage of V20100C with a 100 V rating, compared with V20150C with a 150 V rating in the voltage quadrupler. Moreover, since the voltage tripler has fewer total secondary turns (16T) than those (18T) of the voltage quadrupler, it has slightly less copper loss in the transformer.

Consequently, the voltage tripler has slightly higher efficiency, due to the smaller conduction and copper losses in the secondary side than those of the voltage quadrupler; however, both rectifiers have almost equal efficiency.

5. Conclusions

New rectifiers are proposed in this paper. The proposed voltage tripler and quadrupler rectifiers have a simple structure with one capacitor and two diodes, and higher voltage gain with an equal turns-ratio or the same voltage gain with a larger turns-ratio. The proposed tripler and quadrupler rectifiers have several advantages, such as low component counts, a smaller transformer magnetizing offset current resulting from a larger turns-ratio, and no additional controls, compared with eight previous examples that can obtain additional I/O voltage gains in HB LLC resonant converters.

The rectifiers were compared and analyzed in respect of the transformer turns-ratio, the magnetizing offset current, and the voltage and current stresses of the secondary capacitor and diodes. Moreover, the design details, including the transformer turns-ratio, the resonant tanks, and the main transformer, which are different from those of conventional HB LLC resonant converters, were presented in this paper.

The validity of the basic operation and features was confirmed by the experiment using the half-bridge LLC resonant converter with 400 V input and 100 V/200 W output. Even though the diodes were adopted in the secondary side, the proposed tripler and quadrupler rectifiers achieved 94.1% and 93.7%, respectively. Moreover, the proposed tripler has the same size of transformer as the quadrupler rectifier, due to a much higher transformer turns-ratio, although it has a transformer magnetizing offset current.

This research will be helpful in applications requiring both high efficiency and a high step-up ratio in the half-bridge LLC resonant converter.