A Q-Band CMOS Image-Rejection Receiver Integrated with LO and Frequency Dividers

Abstract

This paper presents a Q-band image-rejection receiver using a 65 nm CMOS technology. For a high image-rejection ratio (IMRR), the Q-band receiver employs the Hartley architecture which consists of a Q-band low-noise amplifier, two down-conversion mixers, a 90° hybrid coupler, and two IF baluns. In addition, a Q-band fundamental voltage-controlled oscillator (VCO) and a frequency divider chain divided by 256 are integrated into the receiver for LO. A charge injection technique is employed in the mixers to reduce the DC power while maintaining a high conversion gain and linearity. The VCO adopts a cross-coupled topology to secure stable oscillation with high output power in the Q-band. The frequency divider chain is composed of an injection-locked frequency divider (ILFD) and a multi-stage current-mode logic (CML) divider to achieve a high division ratio of 256, which facilitates the LO signal locking to an external phase-locked loop. An inductive peaking is employed in the ILFD to widen the locking range. The Q-band image-rejection receiver exhibits a peak conversion gain of 16.4 dB at 43 GHz. The IMRR is no less than 35.6 dBc at the IF frequencies from 1.5 to 5 GHz.

1. Introduction

The development of mobile devices and the need for high-speed communication have resulted in considerable research on receivers operating in the mm-wave frequency bands [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17]. In [2,3,4], the beamforming receivers were implemented by combining four channels [2,3] and eight channels [4], respectively. In [5,6], direct-conversion receivers were presented for low power consumption and small chip area. Although the direct conversion was free from the image problem, the architecture suffered from high DC offset, even-order distortion, and flicker noise [18]. In [13], a high image-rejection ratio (IMRR) over a wide bandwidth was obtained using a single-sideband receiver structure with a high IF. However, such a high IF frequency would require additional down-conversion to the baseband, and the first down-conversion mixer may suffer from compression or self-mixing due to the LO frequency interference. In [14,15], a high IMRR was achieved in the low-IF band by using a Hartley-structured receiver with a quadrature generator that minimized the I-Q mismatch. However, these studies did not include an LO circuit integrated in the receiver, so additional VCO and frequency dividers were required for phase-locked LO generation.

This paper presents a Q-band image-rejection receiver employing the Hartley architecture for a high IMRR [19]. Furthermore, the receiver integrates an on-chip voltage-controlled oscillator (VCO) and frequency divider chain for LO generation. The divider chain is composed of an injection-locked frequency divider (ILFD) and a seven-stage current-mode logic (CML) divider, which fulfill a high division ratio of 256. This facilitates the LO locking to an external phase-locked loop (PLL). This Q-band image-rejection receiver was implemented using a 65 nm bulk CMOS technology, which is relatively cost-effective and easily accessible. The remainder of the paper is organized as follows. In Section 2, the architecture of the Q-band image-rejection receiver is described. The design and measurement of each circuit block of the receiver is presented in Section 3. Section 4 presents the measurement of the Q-band image-rejection receiver. Finally, the conclusions are presented in Section 5.

2. Q-Band Image-Rejection Receiver Architecture

Figure 1 shows the block diagram of the Q-band image-rejection receiver. The image-rejection receiver is composed of a Q-band low-noise amplifier (LNA), two down-conversion mixers, a 90° hybrid coupler, two IF baluns, a Q-band VCO, and a frequency divider chain. The receiver adopts the Hartley image-rejection architecture for a high IMRR. The RF input is amplified and divided with a phase difference of 180 degrees through the single-to-differential Q-band LNA and applied to the two Q-band down mixers. The LO signal generated by the Q-band VCO is divided with a phase difference of 90° through the 90° hybrid coupler and drives two down-conversion mixers, respectively. The differential IF outputs generated by each mixer are added in-phase at the output of the IF balun, and combined through the off-chip IF 90° hybrid coupler. The desired IF signal down-converted through the two down-conversion mixers is added in-phase, and the image signal is canceled out by out-of-phase.

The Q-band VCO operates in the fundamental mode to suppress the spurious spectral components compared to the harmonic-mode VCOs. The following frequency divider chain provides a low-frequency LO signal divided by 256. Thus, the LO signal can be readily locked to an off-chip PLL circuitry.

3. Circuit Blocks of the Q-Band Image-Rejection Receiver

In this section, the design details and measurement results of each individual circuit block of the Q-band image-rejection receiver are described.

3.1. Q-Band LNA

A schematic of the Q-band LNA is depicted in Figure 2a. The first stage of the LNA employs a single-ended structure to eliminate the noise figure (NF) component which would be otherwise contributed by an input balun. The NF is further improved by the source degeneration of a transmission line (TL₁). The input is matched to the optimum NF point through L-section matching, which is composed of parallel and series inductors (L₁ and L₂). All transmission lines are designed in a microstrip structure using the top metal with a 1.2 μm thickness to minimize the loss and chip area, as shown in Figure 3a. The layout of the inductor and transformer are shown in Figure 3b,c, respectively. The inductors were designed in an octagonal shape using the top metal and the inductance was extracted through EM simulation. The transformers were designed using a broadside coupling structure composed of the top two metals (LB and OI).

The second to last stages were designed using a differential common-source structure with the capacitive neutralization technique to improve gain and stability. The interstage matching between the first and second stages was implemented using transmission lines (TL₂–TL₄) and a transformer-based balun (TF₁) connected to a balancing capacitor (C₁). The other interstage and output matching networks are also composed of transmission lines and transformers to reduce the chip area. The output impedance is conjugately matched to the RF input of the following Q-band down-conversion mixer. A chip micrograph of the Q-band LNA is shown in Figure 2b. The chip area is 1.7 × 0.6 mm², which includes the probing pads. The differential output is combined into a single-ended signal using a balun (TF₄) for single-ended measurement purposes. The LNA chip consumes DC power of 30 mW at the drain bias voltage of 1.2 V. The parameter value of each component is presented in

Table 1. Parameter values of the Q-band LNA.

Parameter	Value	Parameter	Value
M1–M7	1 × 10 μm	Cdc, Cbypass	880 fF
L1	380 pH	C1	160 fF
L2	460 pH	CN	8.8 fF

.

The measurement results for the Q-band LNA are shown in Figure 4. The measurement was performed by an on-chip probing method. Figure 4a shows the S-parameters and NF. A peak gain of 18.8 dB was measured at 43.3 GHz with a 3 dB bandwidth of 5.6 GHz (41.7–47.3 GHz). The input matching was measured below 7.2 dB over the entire 3 dB bandwidth while the simulated NF was below 6.9 dB. Figure 4b presents the power measurement of the LNA at 43.5 GHz. The measured input and output 1 dB compression power (IP_1dB and OP_1dB) were −22 dBm and −4.5 dBm, respectively.

3.2. Q-Band Down-Conversion Mixer

The Q-band down-conversion mixer was designed using a Gilbert-cell topology for a high conversion gain and isolation performance [20,21]. A schematic of the mixer is shown in Figure 5a. The charge injection through R₁ and R₂ is adopted at the transconductance stages to reduce DC power consumption while maintaining a high conversion gain. The RF and LO matching networks are composed of transformer-based baluns (TF₅ and TF₆) and series transmission lines (TL₁₅–TL₁₈) for broadband impedance matching and chip area reduction. Series inductors (L_s) are inserted between the transconductance and switching-quad stages to extend the RF bandwidth. A source-follower buffer was added at the output to improve the isolation and IF matching performance. The transistor sizes of the transconductance, switching-quad, and source-follower stages were 2 × 20 μm (M₈ and M₉), 2 × 12 μm (M₁₀–M₁₃), and 2 × 30 μm (M₁₄ and M₁₅), respectively. A chip micrograph of the Q-band down-conversion mixer is shown in Figure 5b, occupying a chip area of 1 × 0.8 mm² including the probing pads. For a single-ended testing purpose, one of the differential output is terminated by a 50-ohm resistor. The Q-band down-conversion mixer consumes DC power of 4.57 mW at the mixer core and 3.89 mW at the source-follower buffer. The parameter value of each component is presented in

Table 2. Parameter values of the Q-band down-conversion mixer.

Parameter	Value	Parameter	Value	Parameter	Value
M8, M9	2 × 20 μm	R3, R4	730 Ω	C3	203 fF
M10–M13	2 × 12 μm	R5, R7	68 Ω	Cbypass	880 fF
M14, M15	2 × 30 μm	R6, R8	92 Ω	CIF	5 pF
RG	5 kΩ	LS	240 pH
R1, R2	340 Ω	C2	139 fF

.

Figure 6 presents the measurement result of the Q-band down-conversion mixer. Figure 6a shows the measured conversion gain versus RF frequency with the LO power of 0 dBm applied at 40 GHz. The conversion gain exhibited a peak value of 0.25 dB at 40.5 GHz and the 3 dB bandwidth was 6.8 GHz (37.3–43.3 GHz). The conversion gain and IF output power at 1.0 GHz versus RF input power at 41.0 GHz are plotted in Figure 6b. The IP_1dB of the mixer was measured to be −6.5 dBm. Since the OP_1dB of the LNA was −4.5 dBm, as given in Section 3.1, the input drive power to the mixer would be −7.5 dBm taking into account a 3 dB difference due to the output balun of the LNA (TF₄ in Figure 2a). Therefore, no gain compression was expected from the mixer.

3.3. Q-Band Voltage-Controlled Oscillator

Generally, there are three oscillator topologies used in the mm-wave frequency band: ring topology [22,23], Colpitts topology [24], and cross-coupled topology [25]. In this work, the cross-coupled topology was adopted as shown in Figure 7a because it provides a sufficient negative resistance, differential operation, and high output power [25]. The total gate width was set to 1.5 × 12 μm considering the trade-off between DC power consumption and output power. The LC tank was implemented using transmission lines (TL₁₉ and TL₂₀) and MOS varactors (C_var). The dimensions were optimized to resonate with the input capacitance of the cross-coupled pair and the buffer transistors (M₁₈ and M₁₉) at 40 GHz. The C_var tuned the capacitance from 51.6 to 146 fF with a Q-factor ranging from 4 to 7.6 at 40 GHz. The oscillation core was followed by two cascaded buffer amplifiers. The first buffer is a source follower that improves isolation and stability. Subsequently, a common-source amplifier (M₂₀ and M₂₁) was followed to boost the output power to the level required for pumping the Q-band down-conversion mixer. A chip micrograph of the Q-band VCO is shown in Figure 7b. For a single-ended testing purpose, the differential output was combined using the output balun (TF₇). The Q-band VCO occupied a chip area of 0.7 × 0.8 mm² including the probing pads. The DC power consumption levels of the oscillation core and buffer stage were 21.1 mW and 31.7 mW, respectively. The parameter value of each component is presented in

Table 3. Parameter values of the Q-band VCO.

Parameter	Value	Parameter	Value
M16, M17	1.5 × 12 μm	L5, L6	250 pH
M18, M19	1.5 × 20 μm	L7, L8	195 pH
M20, M21	3 × 20 μm	Cbypass	880 fF
RG	5 kΩ	Cvar	51.6–146 fF
R9, R10	100 Ω

.

In Figure 8, the measured oscillation frequency and output power of the Q-band VCO are compared with the simulation. As the varactor control voltage (V_C) varied from 0 to 2.4 V, the oscillation frequency was tuned from 35.6 to 45.6 GHz (24.6%). The measured output power ranged from −2.7 to 0.6 dBm, including 2 dB of balun loss, which was added only for a measurement purpose.

3.4. Frequency Divider Chain

Three different topologies are widely used for a frequency divider at the mm-wave frequency: the injection-locked frequency divider (ILFD), Miller divider, and current-mode logic (CML) divider. Generally, the ILFD operates at the highest frequency with a low DC power consumption at the expense of a narrow bandwidth. On the other hand, the CML divider cannot support a high-frequency operation and consumes high DC power. However, it occupies the smallest chip area, particularly at relatively low frequencies [26,27]. Therefore, in this work, the frequency divider chain adopted a ILFD for the first frequency division in the Q-band, which was followed by seven CML dividers.

Figure 9 shows a schematic diagram of a basic Q-band ILFD, which consists of a cross-coupled oscillation core (M₂₂ and M₂₃), a resonator, an injection network (M₂₄), and a source-follower buffer (M₂₅ and M₂₆). The resonator, composed of an inductor (L_res) and parasitic capacitances of M_22–23, M₂₄, and M_25–26, resonates at f₀, a half frequency of the injection signal (LO_in). The LO_in is injected directly into the differential oscillation core through M₂₄. This direct injection enables the extension of the locking range (LR) at a higher operating frequency compared to conventional injection through a tail current source [28]. The LR of the direct ILFD can be expressed as [29]

$$LR\propto \frac{2\pi f_0{I}_{in}}{Q{I}_{osc}}$$

(1)

where I_in and I_osc denote the injection current by LO_in and oscillation current, respectively, flowing through M_inj, and R_ds denotes the drain-to-source resistance of M_inj. Q is defined as follows:

$$Q\approx \frac{R_{ds}}{2\pi f_0{L}_{res}}$$

(2)

According to Equation (1), the LR can be widened by increasing the injection current I_in.

To improve LR of the basic ILFD shown in Figure 9, two variations of ILFD employing a peaking inductor and a varactor, respectively, are presented. In Figure 10a, a peaking inductor (L_peak) is connected in series with M_29j, so that the swing of V_ds and thus I_in of M₂₉ increase. This leads to a wider LR. In Figure 10b, a varactor (C_var) is added to tune the free-running oscillation frequency. Therefore, the LR can be extended by adjusting the oscillation frequency in accordance with the injection frequency. The parameter value of each component is presented in

Table 4. Parameter values of the ILFDs.

Parameter	Value	Parameter	Value
M22, M23, M27, M28, M32, M33	3 × 13 μm	Lres	290 pH
M24, M29, M34	2 × 24 μm	Lpeak	120 pH
M25, M26, M30, M31, M35, M36	3 × 20 μm	Cbypass	1.4 pF
RG	5 kΩ	Cvar	41–167 fF
R11–R16	80 Ω

.

Figure 11 shows the chip micrographs of the basic ILFD, ILFD with a peaking inductor, and ILFD with a varactor. The chip sizes were 0.62 × 0.58 mm², 0.67 × 0.58 mm², and 0.66 × 0.55 mm², respectively, excluding the probing pads. All chips consumed 26.1 mW of DC power.

Figure 12 shows the measurement result of the ILFDs. Figure 12a shows the measured output spectrum in the free-running and injection-locked modes. It was observed that the output signal at 19.6 GHz was clearly locked to the injection signal of P_LO = 0 dBm at 39.2 GHz. Figure 12b presents a comparison of the LR and output power of the three ILFDs at P_LO = 0 dBm. The ILFD with a peaking inductor achieved the widest LR of 35.1% (19.4–26.9 GHz). The output power of the ILFD was no lower than −13.8 dBm over the LR.

To achieve a sufficient frequency division ratio, the output of the ILFD was further divided by the subsequent CML dividers. Seven CML dividers were connected in cascade, so that the whole divider chain fulfilled a division ratio of 256 in the integrated receiver. To experimentally verify the operation of the divider chain, a reduced version of the LO test cut consisting of a Q-band VCO and a 1/16 divider chain shown in Figure 13 was tested. The divider chain was composed of the ILFD with a peaking inductor and three-stage CML divider employing a master-slave structure. One of the differential VCO output signals was monitored to check the oscillation frequency.

Figure 14 shows the measurement results of the Q-band VCO followed by a 1/16 divider chain. The phase noise of the divided signal was −102.37 dBc/Hz at 10 MHz offset as shown in Figure 14a. Figure 14b shows the output frequency of the VCO and the divider versus the VCO control voltage. It was observed that the frequency division by 16 was exactly performed.

4. Measurement of the Q-Band Image-Rejection Receiver

A Q-band image-rejection receiver integrated the circuit blocks described in Section 3 on a single chip, as shown in Figure 15. The chip area was 2.5 × 1.6 mm² including the probing pads.

The measurement result of the image-rejection receiver is shown in Figure 16. The conversion gain was measured versus the IF frequency while the LO frequency was fixed at 40 GHz. As shown in Figure 16a, the receiver exhibited a peak conversion gain of 16.4 dB at 43 GHz and a 3 dB bandwidth of 3.5 GHz (1.5–5 GHz). The noise figure was simulated to be 5.8–7.8 dB over the 3 dB bandwidth. Figure 16b shows the measured IMRR, which ranged from 35.6 to 55.1 dBc over the same bandwidth. The input 1 dB compression power (IP_1dB) was Ȓ28 dBm at the IF frequency of 2.5 GHz.

In

Table 5. Performance summary and comparison.

Ref.	Process	RF Freq. (GHz)	Architecture	CG 1 (dB)	NF 2 (dB)	IP1dB (dBm)	IMRR (dBc)	Pdc (mW)
[6]	65 nm CMOS	22.5–26.1	LNA + Mixer + AMPIF 3 + AMPLO 4 + PPFLO 5	31.5	4.8	−35.2	-	127.44
[9]	0.12 μm SiGe	10–40	LNA + Mixer + VGAIF 6 + ×4 + AMPLO 4	39	6.8	−33	-	130
[10]	0.13 μm SiGe	25–45	LNA + Mixer + ×3 + AMPLO 4	21	5	-	30	-
[11]	45 nm SOI CMOS	24–44	LNA + Mixer + AMPIF 3 + AMPLO 4	35.2	3.2	−25.5	32	60
[13]	22 nm SOI CMOS	20–44	LNA + Mixer + AMPIF 3 + AMPLO 4	28.5	3.3	−25	75	70
[16]	22 nm SOI CMOS	19.5–42	LN-VGA + mixer + LPF + AMPIF 3 + AMPLO 4 + IQGEN 7	25.3	2.7	−23	-	102
[17]	65 nm CMOS	26.5–32.5	LNA + Mixer + BuffIF 8 + AMPLO 4 + PPFLO5	29.5	5.3	−28	-	33
This work	65 nm CMOS	41.5–45	LNA + Mixer + VCO + 1/256 divider	16.4	5.8	−28	35.6	91.9 + 294 (divider chain)

¹ Maximum conversion gain over the bandwidth. ² Lowest NF over the bandwidth. ³ IF amplifier. ⁴ LO amplifier. ⁵ LO poly phase filter. ⁶ IF variable gain amplifier. ⁷ I-Q generator. ⁸ IF buffer.

, the performance of the Q-band image-rejection receiver is summarized and compared with those of previously reported silicon-based receivers in a similar frequency band. Compared with other image-rejection receivers, this work achieved a high IMRR at a reasonably low IF frequency below 5 GHz using the Hartley structure. It should be noted that a high IMRR was achieved in [13] by using a high IF frequency of 16 GHz. In addition, the LO circuit consisting of a VCO and a 1/256 divider chain was integrated in this work, which facilitated locking to a low-frequency LO reference.

5. Conclusions

In this paper, a Q-band image-rejection receiver was developed using a 65 nm bulk CMOS technology, which is relatively cost-effective and easily accessible. The Q-band receiver employing a Hartley architecture for a high IMRR integrates a Q-band LNA, two Q-band down-conversion mixers, a 90° hybrid coupler, two IF baluns, and an LO circuit. The integrated LO consists of a Q-band fundamental VCO followed by a 1/256 divider chain, which fulfills a high division ratio. This facilitates the LO locking to an external phase-locked loop (PLL). The Q-band image-rejection receiver exhibits a peak conversion gain of 16.8 dB and a high IMRR of 35.6 dB with IP_1dB of −28 dBm. This receiver can be employed for future 5G mm-wave communication.