A Fully Integrated 0.6 Gbps Data Communication System for Inductive-Based Digital Isolator with 0.8 ns Propagation Delay and 10⁻¹⁵ BER

Abstract

Digital isolators are implemented to protect low-voltage electronics and ensure human safety during high-voltage surge events. In this work, we present the design of an inductive-based digital isolation system that can sustain up to 1 kV_rms breakdown voltage. The proposed system is designed using the pulse polarity modulation scheme and fabricated in a 0.35 $\mathsf{\mu }$m CMOS. Two identical dies are bounded within the IC package, with one die housing the transmitter (Tx) and the isolation transformer, while the other die contains the receiver (Rx). Two different customized designs between three metal layers are implemented to form the isolation element. The transformer’s secondary coil is constructed in metal-1, while the primary coil is formed in metal-2 and metal-3 for comparing the system functionality, isolation capability, and propagation delay. The functionality has been verified by measurements for an operating frequency of 300 MHz with a 2.6 ns propagation delay and an energy consumption of 8.15 $\times$ 10³ pJ/bit at 1 Mbps. The chip was tested under extreme temperatures and achieved a maximum measured common mode transient immunity (CMTI) of 500 V/$\mathsf{\mu }$s. Jitter has been examined to ensure fast transmission at a bit error rate (BER) of 10⁻¹⁵ with a total jitter (TJ) of 188.18 ps.

1. Introduction

Sensor Interfaces are key elements in industrial applications as they provide dedicated power levels for various actuators, sensors, and read-back links within the system. To ensure reliable circuit operations, power management systems require control levels configuration for their data communication channels in terms of human safety and circuitry protection [1,2]. One main requirement to afford optimum performance is to have an isolation system that enables digital signal transmission while eliminating dangerous effects on low-voltage system electronics caused by the high-voltage domain. Typically, in high-voltage applications, isolation barrier breakdown can not only cause potential hazards to end users but also may cause damage to low-voltage control circuits affecting the system functionality. For example, if the isolation barrier failure mode occurs in the AC motor drive system, either the damage is limited to the die with the isolation capacitor or to the gate driver die [3].

Digital isolation techniques are in the broad area of data communication systems for modern sensor interfaces. They are widely used in different applications, including medical equipment, network interfaces, and automotive industrial systems. The purpose of the isolation barrier is to eliminate voltage spikes and unwanted ground loops that may exist between high-voltage and low-voltage circuit domains [4]. This is achieved by establishing two separate ground references for the transmitter (Tx) and receiver (Rx) circuits, allowing safe communication between different voltage levels. Additionally, it is mandatory in many industrial applications to maintain the required protection level against multiple noise sources, such as lightning strikes, while ensuring the correct functionality at the targeted signal transfer speed.

The coupling methods to perform the digital isolation are based mainly on three types: optocouplers, capacitors, and transformers. Digital isolators based on optocouplers were the very first conventional way in data communication systems that exploit light to transfer data in the near-infrared band. The main advantages of optocouplers are a high isolation breakdown and immunity to electromagnetic interference (EMI). On the other hand, they suffer from high power consumption (30 mA at 40 Mbps) [5], which causes lifetime degradation. Moreover, optocouplers are not compatible with the CMOS process since they are fabricated in gallium arsenide (GaAs), and discrete chips are required for multiple isolation channels [6,7].

Capacitive isolators are implemented in silicon dioxide (SiO₂) technology which has a dielectric strength of up to 500 V/$\mathsf{\mu }$m [8,9]. As a result, an isolation voltage of 1.5 kV_rms can be achieved within a 3 $\mathsf{\mu }$m SiO₂ thickness between metal-1 and metal-6 in a 0.18 $\mathsf{\mu }$m CMOS process [10]. Compared to optocouplers, capacitive isolators can be integrated with the CMOS process and have lower power consumption [11,12,13]. In addition, capacitive techniques are well-suited for high-speed data transfer due to their higher EMI. However, because of the fast ground shift (in hundreds of kV/$\mathsf{\mu }$s) between the two circuit domains, capacitive techniques have lower common mode transient immunity (CMTI) [14,15,16]. This common mode current, which is proportional to the capacitor size, may corrupt data transfer and increase the bit error rate (BER).

To achieve higher data rates, more isolation voltage, and improve the CMTI, the inductive-based isolation method is adopted. Inductive methods use polyimide, with a field strength of 250 V/$\mathsf{\mu }$m before breakdown, as the insulation material between coils to transfer data and power through magnetic coupling. Polyimide outperforms SiO₂ by having a lower parasitic capacitance of the isolation barrier at the expense of added fabrication cost [17,18,19,20,21,22,23,24]. This method supports high data rates of 0.5 Gbps [25], provides an excellent CMTI (650 kV/μs) [26], and offers a great isolation voltage of 7.5 kV_rms [27]. In addition to data transmission [28,29], isolated DC-DC converters use transformers for power transfer because of their high-quality factor compared to capacitive coupling, which usually requires off-chip elements to construct subharmonic resonant peak efficiency [30,31,32,33].

Figure 1 shows the typical block diagram of an inductive-based digital isolation system for industrial sensor interfaces. Transceiver blocks are implemented on the low-voltage and high-voltage sides, each with their respective supply and ground rails: VDD_L/VDD_H/VDD₁/VDD₂/VDD₃ and GND_L/GND₁/GND₂/GND₃. Two differential signals are transmitted from the microcontroller logic unit (MLU) on the low-voltage side to the gate driver on the high-voltage side, while the read-back signal is transmitted from the off-chip load through the analog-to-digital converter (ADC) on the high-voltage side to MLU. To ensure a fully isolated environment, the system incorporates an isolated DC-DC converter that takes the input voltage source from the low-voltage side and generates required voltage levels in the high-voltage domain. A fully integrated digital isolation system attempts to combine the communication links into a single compact die to further minimize power consumption and reduce fabrication costs.

This design utilizes edge-based modulation [34] due to its lower power consumption compared to on-off-keying (OOK) architecture [35,36], which uses a single chip area at the cost of higher power consumption during the logic high state of the signal modulation process. A set/reset architecture with a dual transformer is an example of edge-based communication with a high isolation rating. It, however, occupies twice the transformer area compared to single transformer architectures. Another example is the pulse count method [19,20], where the chip area and the power consumption stand in an acceptable range. When compared to the single-pulse method, the power is 1.5 times higher, the propagation delay is longer, and it operates at lower data rates since it requires more time to evaluate the pulse count.

Although the currently available maximum achievable data rate is sufficient for the current applications, future demands are expected to require higher data rates, lower latency, and lower BER. To the best of our knowledge, the maximum speed achieved with the minimum propagation delay for fully integrated inductive digital isolators in a 0.18 $\mathsf{\mu }$m CMOS is 0.5 Gbps and 3.6 ns, respectively. Moreover, to operate at higher speeds, two transformers are utilized, which increases the fabrication cost [25]. This work proposes high data rates, reduced delay, and a low BER fully integrated inductive digital isolation system based on the pulse polarity modulation scheme in a high-voltage 0.35 $\mathsf{\mu }$m CMOS process. The rest of this paper is organized as follows: design and implementation of the inductive-based digital isolation system are given in Section 2. Measurement results are presented in Section 3. Discussion and comparison with prior state-of-the-art are illustrated in Section 4, and final conclusions are drawn in Section 5.

2. Inductive-Based Digital Isolation System

The transceiver circuit of the implemented system utilizes the pulse polarity modulation scheme, which has the advantages of a compact circuit area, low power consumption, and high data rates. The presented scheme generates short pulses (in GHz sub-band) from the input digital signal for logic state transmission. The basic principle of GHz sub-band generation is demonstrated by the resulting CMOS inverter’s harmonic overtones. When a sinusoidal input signal with a frequency of half the bandwidth of the CMOS process is applied under a VDD/2 bias condition, the output waveform is enhanced to a square shape with a fast slew rate. The Tx can then modulate these overtones and transmit them to the Rx using a small on-chip isolation transformer area.

2.1. Tx Design

Figure 2 shows the circuit diagram, including the operation waveforms of the Tx side of the digital isolator system supporting single channel one direction (half duplex) data communication. The MLU input digital signal is processed through the Tx subcircuit stages and transmitted to the Rx side through inductive coupling. The Tx circuit consists of two differential parts: a negative pulse generator and a positive pulse generator, for shaping the negative pulses and positive impulses, respectively. Each of these branches consists of a pulse detector, cascaded inverters, a current limiter, and driver transistors.

The pulse detector is the first circuit of the Tx chain, and it is responsible for detecting the positive and negative edges of the input digital signal “IN.” The sizing of the transistors is designed so that it generates a 2 ns pulse width signal, negative edge (NE) or positive edge (PE), to accommodate the desired system bandwidth. The current limiting inverter controls the current passing through the large-sized driving transistors (M₅, M₆, M₇, and M₈) by shaping the generated pulse from the edge detector to have a sharp rise and a lower falling slope. This is achieved by increasing the current of M₁/M₃ and decreasing the current of M₂/M₄, i.e., the high change of the current with respect to time, the sharper the edge of the signal and vice versa. During the high-to-low transition of IN, the G₆ signal is determined and activates the driver transistor M₆. Then, the cascade-connected inverters output (G₅) at the upper circuit branch triggers the driving transistor M₅. This operation is repeated for the transmission of IN from low to high, which corresponds to the lower part of the Tx.

2.2. Transformer Design

We performed two case studies to investigate the isolation capability of the technology at different separation distances between the coils. The voltage at the secondary side of the transformer is formed by differentiating the current I₁ generated in the primary coil at the Tx side and can be controlled by proper magnetic coupling between the two coils. Since the design kit does not include inductor or transformer models, we customized the coils on two different metal layers separated by the inter-metal dielectric material. Among other configurations, such as tapped or interleaved, we chose the stacked structure due to its highest self-inductance and coupling efficiency. Figure 3a illustrates the lateral parameters of the square spiral coil with a number of turns $n$= 3 and a number of sides $N$ = 4. The coil width is denoted by $w$, while $s$ is the spacing between the adjacent turns, and inner and outer diameters are $d_{in}$ and $d_{out}$, respectively. Square spirals are chosen among other alternative geometries due to their layout simplicity. Also, they have the smallest effective area compared to hexagonal, circular, and octagonal shapes. Figure 3b shows the two versions of the on-chip transformer implemented on the three metal layers of a CMOS process. Higher isolation can be achieved between metal-1 and metal-3 due to the larger insulation material thickness. Our objective is to examine the effect of changing the isolation distance on the performance of the data communication link for the isolation system.

The isolation transformer is modeled by a non-ideal equivalent circuit consisting of an inductance, parasitic resistance, substrate resistance, and parasitic capacitances. The equivalent circuit of the non-ideal transformer formed by two $\pi$ models for the primary and secondary coils is shown in Figure 4. The series inductances, resistances, and parallel capacitances are defined by [37]

$$L_s=\frac{2\mu n^2{d}_{avg}}{\pi }\left[ln\left(\frac{2.067}{\rho }\right)+0.178\rho +0.125{\rho }^2\right],$$

(1)

$$R_s=\frac{\rho l}{\delta w\left(1-e^{-\frac{t}{\delta }}\right)},$$

(2)

and

$$C_{ox}=C_{ov}=0.5\frac{{\epsilon }_{ox}}{t_{ox}}lw,$$

(3)

respectively. The magnetic permeability is denoted by $\mu$, $d_{in}$ is the average diameter of turns, $\rho$ is the fill ratio, $\delta$ refers to the skin depth, and $t$ represents the thickness of the metal. ${\epsilon }_{ox}$ is the oxide permittivity, $t_{ox}$ is the oxide thickness, and the coil length is represented by $l$. The substrate coupling elements, $R_{si}$ and $C_{si}$, can be ignored by considering the pattern ground shield effect. Finally, the mutual inductance is related to the coupling coefficient $k$ and the primary/secondary inductances $L_{sp}$/$L_{ss}$ as [37]

$$M=k\sqrt{L_{sp}{L}_{ss}}.$$

(4)

The typical range of mutual inductance for the stacked spiral configuration is between 0.3 and 0.9, with the highest coupling coefficient being used in this design to ensure the correct functionality of the digital isolator system. In addition, the proper matching of the transformer’s inductance value should be considered to avoid distortion of the detected voltage pulse at the secondary side. The detected voltage pulse has been simulated at different inductance values, where a typical value of 10 nH has been selected based on the desired amplitude and pulse width at the Rx. Then, on-chip spiral coils of the transformer parameters are designed from the obtained inductance value.

2.3. Rx Design

The Rx circuit consists of a high pass filter (HPF), peak/bottom levels hold, a differential amplifier, and a hysteresis comparator. Figure 5 presents the schematic of the Rx with its operation waveforms. The isolation transformer’s secondary side is connected to the Rx front side using two bond wires between the corresponding pads.

The received signal (V_{_pulse}) with a frequency of 3–5 GHz is first filtered from low-frequency noise components caused by common mode transients (CMT) using the HPF. The diode circuit is formed by implementing two series diode connected BJTs adopted to detect positive and negative impulses according to the V_bias threshold applied between its terminals through resistances R_a and R_b. The capacitor C_b helps widen the detected pulses to a 10 MHz frequency so that they can be handled by the differential amplifier.

The single-stage amplifier design compares both inputs, V_{_pk} and V_{_bot,} with the reference voltage V_c [38,39], as shown in Figure 6. The reference current of the differential amplifier is settled by a Cascode current mirror, where the latter is referenced by the V_pm-biased external current source. This amplification stage is designed to further reject the magnitude of the slow swing pulses that exceed the threshold voltage of the diodes. The purpose of capacitive coupling elements (R_c and C_c) at the amplifier output V_O is to establish the DC level of the comparator input V__com at V_pm2.

The last block of the Rx is the hysteresis comparator, which consists of three stages: a differential input pair, a decision stage, and an output buffer [40]. Figure 7 shows the circuit of the hysteresis comparator. The cross-coupled differential stage transistors provide positive feedback to the decision stage inputs and control the switching point of the comparator. The tail current of the differential stage is adjusted by the current mirror biased at V_pm. Thus, if the comparator’s differential input signal exceeds/falls down this threshold level (i.e., positive/negative peak voltage), the output signal OUT switches to logic 1/0.

2.4. Common Mode Noise Analysis

One important characteristic of digital isolators is the system’s ability to reject CMT pulses while maintaining error-free transmission at the desired data rate. The common mode voltage refers to the voltage difference between the Tx ground and the Rx ground. The common mode voltage is related to the rapid switching of the integrated gate bipolar transistor (IGBT) at the high voltage side, which propagates through the overlapping capacitance of transformer coils ($C_{ov}$) and affects the Rx-detected signal level. Consequently, the Rx signal V_{_pulse} will follow similar rise/fall transitions of the common mode pulse in the range of hundreds of kV/$\mathsf{\mu }$s range. The unwanted slew rate added to V_{_pulse} can lead to false detection at the Rx side and hence miss-determining the correct logic level at the final system output. Since the common mode component of V_{_pulse} is with a frequency less than the actual modulation frequency ($f_{cm}<f_{mod}$), the amount of this noise can be further reduced by the HPF, the first element of the Rx circuit. The differential architecture of the Rx helps further improve the common mode rejection of the overall implemented system. Figure 8 illustrates the block diagram of the digital isolator under CMTI simulation. A high voltage pulse V_cmti = 550 V with a rising/falling time of 2.5 ns which corresponds to a CMTI of 220 kV/$\mathsf{\mu }$s is being injected between the Tx ground (GND_Tx) and the Rx ground (GND_Rx).

The system’s response to the CMT pulse is demonstrated in Figure 9. The input digital signal at the Tx with a frequency of 10 MHz is modulated and transmitted to the Rx input through the isolation transformer. The second waveform is the 42 MHz high-voltage pulse between the Tx and Rx grounds (V_cmti = 220 kV/$\mathsf{\mu }$s). In typical scenarios, the high-voltage pulse combinations are applied at multiple IN rising/falling edges, i.e., during different surge events: rising, high amplitude, falling, and low amplitude. Although the applied surge added additional top/bottom peaks on the comparator input V_{_com}, the final Rx output OUT is successfully recovered. This is because the unwanted peaks fall above/below the threshold level of the comparator within a small duration. The total system propagation delay from the Tx input to the Rx output during the surge event is 28 ns.

3. Measurement Results

The experimental test bench setup for the fabricated inductive-based digital isolator system is shown in Figure 10a. One power supply is used for supplying the printed circuit board (PCB) domain A_1/domain A_2 and domain B (Figure 10b), while the other power supply is employed to generate reference voltages for the Rx circuit. The continuous input digital signal is supplied to the system’s Tx input using a 0.4/0.68 Gbps pulse/pattern generator which is then recovered at the Rx output analyzed on an Agilent 13 GHz Infiniium digital signal analyzer through the 12 GHz active probes adopted for their noise immunity performance. The input and output signals are simultaneously displayed on the oscilloscope for the propagation delay measurement. The 1:1 isolation transformer is used to assign a floating ground to the Tx side’s equipment. The bottom layer of our custom PCB prototype is divided into three isolated domains, each one assigned to separate supply rail terminals. Pairs of surface-mounted ceramic capacitors (0.1 $\mathsf{\mu }$m and 10 $\mathsf{\mu }$m) are placed close to package pins to filter out power supply noise. The zoomed view of the two-layer PCB with 80 mm $\times$ 70 mm dimensions is also shown in Figure 10b. The HALFCUBE temperature chamber is used to measure the system functionality over a wide range of temperature variations (Figure 10c).

The implemented inductive-based digital isolator system is fabricated in a 5 V 0.35 $\mathsf{\mu }$m CMOS process. The total area for each die is 2 mm², and the two dies are assembled and bounded inside an 84-pins PGA package (Figure 11). Die A, which houses the Tx and the on-chip transformer, is powered from the domain A supply, while die B (which contains the Rx circuit) is driven from the domain B supply rails. The Tx and isolation transformers occupy a silicon area of 142 $\mathsf{\mu }$m $\times$ 126 $\mathsf{\mu }$m and 224 $\mathsf{\mu }$m $\times$ 224 $\mathsf{\mu }$m, respectively, while the Rx block consumes an active area of 7.3 $\times$ 10⁴ $\mathsf{\mu }$m². The coil width of the transformer is 6 $\mathsf{\mu }$m, and the spacing is 2 $\mathsf{\mu }$m. Two bonding arrangements were implemented to test the system functionality according to two customized coil designs for the isolation transformer: Figure 11a metal-1 to metal-3, and Figure 11b metal-1 to metal-2.

3.1. System Functionality

Isolated solutions for protocols such as USB3 and HMDI require data rates in the range of Gbps. Moreover, isolated high-speed clocks and data links for industrial sensor interfaces operate at the same range. For this purpose, we have performed the system measurements at high frequencies. Figure 12 demonstrates the input-output waveforms of the fabricated inductive-based digital isolation system at (a) 250 MHz and (b) 300 MHz frequencies. We have compared the input with outputs from both systems based on the two fabricated customized transformers. OUT1 is related to the system using the metal1-metal2 transformer, while the system’s output denoted by OUT2 utilizing the metal1-metal3 transformer is denoted by OUT2. The measured typical propagation delay from the generated Tx input IN and the recovered Rx output OUT1 is 800 ps at both rising and falling edges for 250 MHz, as shown in Figure 12a. Compared to OUT1, the propagation delay is increased to 3.25 times, and the amplitude is reduced by 59% for OUT2 at 250 MHz. This is because the separation between the coils maximizes the isolation voltage at the cost of reducing the energy of the detected signal at the Rx input. Figure 12b shows the measured outputs at 300 MHz, where the propagation delay for OUT1 and OUT2 is increased from 2.6 ns to 4.8 ns, respectively. Despite the increased propagation delay, the achieved results support fast transmission for high data rate applications.

3.2. Temperature Variations

To ensure the system functionality at extreme conditions, we performed the measurement under different temperatures. Figure 13 demonstrates the effect of temperature variations on the system functionality at −27 °C (Figure 13a) and 68 °C (Figure 13b). The digital isolator system is tested under the operational frequency of 250 MHz. The PCB is placed inside the chamber, and the temperature is gradually varied to monitor the waveform on the oscilloscope. The variation rate of the propagation delay from its typical value of 800 ps at room temperature is 9.7 ps/°C, for temperature variations from 27 °C and 68 °C, as shown in Figure 13b. Therefore, the propagation delay is insensitive to temperature variations.

3.3. Common Mode Rejection

Figure 14 shows the digital isolation system output in the presence of CMT noise. The high-voltage pulser is equipped with a 1:1000 divider to monitor the generated pulse on the oscilloscope. The system’s output response to the rising CMT surge is shown in Figure 14a, where a slew rate of 500 V/$\mathsf{\mu }$s is observed at an amplitude of 28 V during a 100 ns duration. The output glitch of 500 mV at the start of the surge is observed. The system’s output during the falling CMT surge demonstrated in Figure 14b shows only a 200 mV shift due to the slower transient slope of 80 ns. The difference in slope measurement between the rising and falling CMT noise is due to the accuracy of the high-voltage pulser device. Although the simulation results demonstrate a CMTI of 220 kV/$\mathsf{\mu }$s, higher CMTI could not be achieved due to the slow rise/fall times of the high-voltage pulser device (25 ns), which is limited to 125 V/$\mathsf{\mu }$s at the falling CMT surge.

3.4. Jitter Analysis

Jitter is a critical parameter characterizing high-speed data communication systems, as it can cause errors in transmitting bits, leading to incorrect estimation at the receiving end and increasing BER. Jitter can be caused by a system, data transmission, or random noise. Figure 15a shows the real-time eye diagram of the system output OUT at the Rx end captured at a 0.5 Gbps input digital signal. The Eye width indicates a clear opening of 1.9 ns mean-value. The measured total jitter (TJ) value at both edges of the eye is 100 ps, composed of the early/late transition deviations from the ideal time location. The BER bathtub curve of the eye diagram is shown in Figure 15b. Each symmetrical Gaussian tail is made of two segments: the measured section (in blue) and the extrapolated section (in gray). The digital isolator system achieved the lowest BER of 10^−15, which is computed by intersecting the effective eye width with the bathtub curve. The accumulated jitter is the main cause of bit errors that occurs below the threshold line. TJ of the system is the difference between the unit interval (UI) and the eye width, which is 188.18 ps.

Typically, TJ is composed of deterministic jitter (DJ) and random jitter (RJ). DJ is further categorized into data-dependent jitter (DDJ) and periodic jitter (PJ). RJ is related to thermal noise, shot noise, and pink noise. Figure 16a shows DDJ versus bit, where the first two bits of the generated stream are zoomed. The negative jitter value at the falling edge of the first bit (−10.9 ps) indicates that the transition arrived earlier than it should have, while for the second bit, the transition arrived later, resulting in increased transmission errors in the system. Figure 16b illustrates the extracted composite jitter histogram, showing the distribution of three types of jitters present in the system: TJ, RJ/PJ, and DDJ. The amount of RJ/PJ is evaluated by subtracting DDJ from TJ, which is 166.38 ps or 83.19 ps at each peak. By computing the peak frequencies of inter-symbol-interference (ISI) and duty cycle distortion (DCD) using a digital signal analyzer time interval error (TIE) algorithm, DDJ can be eliminated.

4. Discussion

A performance summary and comparison of this work with other fabricated state-of-the-art from the literature are given in

Table 1. Performance comparison and summary with other prior works.

Ref.	Process $\left(\mathsf{\mu }\mathbf{m}\right)$	Iso. Element	Area $(\times$${10}^4\mathsf{\mu }{\mathbf{m}}^2)$	Scheme	Max. VDD (V)	Iso. Rating (kVrms)	Max. CMTI $(\mathbf{kV}/\mathsf{\mu }\mathbf{s})$	Max. Speed (Gbps)	Delay (ns)	Energy @ 1 Mbps (pJ/b)
[9]	0.35	Cap.	-	Pulse	5	2.28 (b)	-	0.5	2	1200
[12]	0.5	Cap.	60 (a)	Pulse	1.8	-	-	0.26	15	99
[13]	0.4	Cap.	37.5	Pulse	3.3	2.3	-	0.1	10	363 (d)
[23]	0.5	Ind.	11.98	Pulse	5	2.5	35	0.25	5.5	8000
[25]	0.18	Ind.	12.26	Pulse	5	1	130 (c)	0.5	3.2	5800
[26]	0.25	Ind.	71.25 (a)	OOK	5	3.34	650	0.08	15.5	9500
[27]	0.18	Ind.	-	OOK	5	7.5	200	0.2	11	14,000
This work @ M1-M2 coils	0.35	Ind.	75.36	Pulse	5	0.5 (b)	0.5	0.6	0.8	8150
This work @ M1-M3 coils						1 (b)		0.5	2.6

^(a) estimated from chip micrograph, ^(b) calculation, ^(c) simulation, ^(d) at 50 Mbps.

. In this comparison table, we have included both capacitive and inductive-based isolation systems. Yun et al. [27] achieved the highest isolation voltage rating of 7.5 kV_rms within 30 $\mathsf{\mu }$m thick polyimide using an on-chip transformer implemented in a 5 V 0.18 $\mathsf{\mu }$m CMOS, however, at the cost of higher energy consumption. The capacitive isolator implemented in a 1.8 V 0.5 $\mathsf{\mu }$m process has the lowest energy of 99 pJ/b [12]. The work of Kaeriyama et al. [23] stands out among the others, with the smallest effective area using the pulse polarity scheme. Within the works presented in Table 1, our design achieved the maximum speed of 0.6 Gbps and a 0.8 ns minimum propagation delay for metal1-meta2 transformer implementation utilizing pulse polarity modulation implemented in a high-voltage 5 V 0.35 $\mathsf{\mu }$m CMOS process. The presented results show the effect of increasing the separation distance between coils, where it increases the isolation voltage from 0.5 kV_rms to 1 kV_rms. However, this comes with a trade-off of reduced speed and increased propagation delay to 0.5 Gbps and 2.6 ns, respectively.

5. Conclusions

An inductive-based digital isolator implementation was discussed in this paper. The system is suitable for the on-chip integration of multiple high-speed clocks and data links between MLU and the gate driver in industrial sensor interfaces. The utilized pulse polarity modulation scheme, as well as the metal1-metal2 transformer structure, allows the design to achieve a higher speed and a minimum propagation delay of 0.6 Gbps and 800 ps, respectively. Moreover, the designed system using the metal1-metal3 transformer has a maximum isolation voltage of 1 kV_rms at the expense of a slight reduction in the transmission speed and an approximately three-fold increase in the propagation delay. The tested chip can operate at temperature variations between −27 °C and 68 °C. Correct system functionality under the presence of CMT of 500 V/$\mathsf{\mu }$s was verified by measurement. The system has a minimum BER of 10⁻¹⁵ with a TJ of 188.18 ps.