A 12~14-Bit SAR-SS Hybrid ADC with SS Bit Shifting Resolution Reconfigurable Method for Bio-Signal Processing

Round 1

Reviewer 1 Report

Comments and Suggestions for Authors

 

The overall organization of this paper is not clear. However, I have some concerns about this manuscript.

1. How does the proposed ADC solve the issue of exponentially increasing sampling speed based on resolution?

2. The proposed ADC uses both SAR and single-slope ADCs.

In theory, how do you choose the 4 bits for a single-slope ADC and the rest for a SAR ADC?

3. From the simulation result, the proposed ADC only achieves 10-bit resolution. How many bits are contributed by SAR ADC for the 10-bit resolution?

4. Could you please explain why DNL and INL are over +-1LSB.

5. What is the power consumption of the ADC, and how is it divided between analog and digital power?

 

Author Response

Please see the attachment.

Author Response File: Author Response.pdf

Reviewer 2 Report

Comments and Suggestions for Authors

The paper presents a SAR and single-slop hybrid structure based reconfigurable ADC. The resolution of single-slop part is fixed to 4-bit for conversion cycles reduction, while the resolution of SAR is designed as 8-10-bit reconfigurable. Bit shifting method is proposed for SAR control and digital ramp generation to provide correct C-DAC voltage settling in different modes. The ADC achieves ENOB of 10.8-bit with a total power consumption of 34uW.

1. The authors mentioned that the resolution of single-slope ADC should be set properly large to promise the C-DAC linearity, but the later discussion mainly considers the total conversion time under different condition of resolution distribution. Analysis to the compromise of conversion speed and linearity should be given to explain the reason for choosing a 4-bit SS-ADC.

2. The input capacitance in reference work 3 is reconfigurable in different resolution mode, resulting in a scalable bandwidth. While in the proposed SAR-SS hybrid ADC, the total capacitance of C-DACs keeps the same, does this limit the application bandwidth? Please describe several advantages of this arrangement.

3. The manuscript should be revised carefully, since some errors have occurred, for example, the Fig. 15 and 16 seems to be repetitive. Besides, the structure of some key blocks such as the comparator or the detailed C-DAC weights should be detailed, and how the mismatch issue of C-DAC weights is dealt with.

4. The measured DNL in Figure 19(a) is wrong. Besides, why is there a big jump in INL curve?

5. The SNDR performance in different mode shows that the resolution enhancement in the proposed structure is not significant. The authors should explain the main reasons for both of the limited static and dynamic performance, and give some possible solutions for these issues.

6. Please compare with the following reference: X. Zhao et al., A 0.6-V 94-nW 10-bit 200-kS/s single-ended SAR ADC for implantable biosensor applications, IEEE Sensors Journal, 2022.

Comments on the Quality of English Language

N/A

Author Response

Please see the attachment.

Author Response File: Author Response.pdf

Round 2

Reviewer 1 Report

Comments and Suggestions for Authors

The reviewer's comments were addressed.

Author Response

There is no other comments from the reviewer 1. 

Reviewer 2 Report

Comments and Suggestions for Authors

Although most of the questions have been addressed. I suggest the author to carefully check the DNL as it cannot be lower than -1 LSB by definition.

Comments on the Quality of English Language

I have no more questions for the English writting.

Author Response

Please see the attachment.

Author Response File: Author Response.pdf