On the Minimum Value of Split DC Link Capacitances in Three-Phase Three-Level Grid-Connected Converters Operating with Unity Power Factor with Limited Zero-Sequence Injection

Abstract

This paper introduces an approach to calculating the minimum value of split DC link capacitance in three-phase three-level grid-connected DC-AC converters operating with unity power factor without either active balancing circuits or AC zero sequence injection. Due to the fact that partial DC link voltages and rectified mains phase voltages reach their maximum and minimum values, respectively, at different time instants, it is feasible to decrease the minimum value of the former below the maximum value of the latter while still maintaining proper functionality of the power stage. The minimum possible split DC link capacitance values are hence derived from the boundary condition where the above-mentioned voltages are tangent to each other. The accuracy of the analytical derivations is confirmed by simulations and experiments carried out on a 10 kVA T-type converter prototype, which show a high degree of agreement.

1. Introduction

Grid operators have established rigorous guidelines for maintaining high standards of mains current quality, which is measured in terms of total harmonic distortion (THD) [1,2]. As a result, power converters that are connected to the grid are required to ensure that the mains current waveform is almost sinusoidal and synchronized with the grid voltage, i.e., to operate with unity power factor [3]. Grid-connected power converters usually incorporate short-term energy storage components (typically in the form of capacitors) on the DC side in order to deal with pulsating power components [4], maintain desired operation during power mismatches that occur during transients [5] and provide hold-up energy (if necessary) [6].

Regrettably, DC link capacitance is often the limiting factor for reliability and/or physical size in grid-connected power conversion systems [7,8,9]. The value of required DC link capacitance is usually determined by hold-up time requirements. Conversely, for certain applications where short loss of mains may be handled, hold-up energy storage is unnecessary. In such cases, it may be feasible to decrease the amount of DC link capacitance. Various common methods for reducing the required amount of DC link capacitance have been proposed so far, including:

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Active power decoupling [10,11,12];

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Distorting the mains current to the lowest permissible power quality level [13,14];

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Increasing the DC link voltage ripple [15,16].

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The literature provides minimum values of DC link capacitance for:

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Single-phase grid-connected converters that employ active power decoupling circuitry [17];

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Line waveform control [14];

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PI + Notch DC link voltage controllers [18];

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Increased DC link ripple [16].

In three-phase converters operating under balanced conditions, the pulsating power component is eliminated at the DC side [19], resulting in a relatively small total DC link capacitance requirement for two-level three-phase converters [20]. Nevertheless, Ref. [21] conducted minimum DC link capacitance sizing based on stability requirements for photovoltaic inverters. Recently, three-level three-phase AC/DC and DC/AC converters with split two-capacitors DC links have emerged as a viable topology for power ratings ranging from 10 kVA to 100 kVA [22] (it should be emphasized that inverters producing more than three-levels of voltage containing multiple-split-capacitors DC links [23,24] are not addressed in this work). However, systems that use split DC links introduce an interesting phenomenon as follows: despite the absence of a pulsating power component at the DC side, split DC link capacitors in such systems are still subject to oscillating power components even though they sum up to zero. When the midpoint of the split DC link capacitors is isolated from the mains neutral line, it is feasible to remove the resultant ripples in the partial DC link voltage. This can be accomplished by supplementing the modulating signal with a third-harmonic zero-sequence component (in the case of a converter operating at unity power factor) in addition to the DC component, which is necessary for balancing the average values of split DC link voltages [25,26,27,28]. However, to prevent grid-side currents from containing zero-sequence components, it is important to avoid injecting high-frequency zero sequence components in three-phase four-wire three-level converters. Furthermore, the presence of high-frequency zero components can result in common mode currents in transformerless grid-connected photovoltaic systems [29]. If minimizing DC link capacitance is desired in such systems, it can be achieved by using additional specialized hardware, as suggested in [30,31]. Nevertheless, it should be noted that this solution would come at the expense of increased system cost and physical size. Recently, a methodology has been proposed in [30] to establish a baseline for split DC link capacitance values and voltage set points in three-phase three-level AC/DC (or DC/AC) converters. This methodology applies to converters that operate with unity power factor and a zero-sequence component injected into modulation signals comprising solely a DC component. The present study merges the approach introduced in reference [32] with the concept proposed in [15] to ascertain the lowest achievable values of split DC link capacitance through maximal increase of DC link voltage ripple. It is shown that the proposed methodology allows the attainment of a two-fold reduction of utilized DC link capacitance compared to the technique proposed in [32]. The proposed approach is validated through simulations and experiments.

2. Materials and Methods

A generalized three-phase three-level grid-connected AC-DC power converter operating with unity power factor which the present study focuses on is depicted in Figure 1 [33]. Possible realizations of three-way switches S_R, S_S and S_T may be found in [34,35,36]). The AC side of the converter is interfaced to the grid via L or LCL filters while its DC side is linked with either a two- or three-terminal equivalent power element, representing a downstream converter [37]. The split DC link is realized by two capacitors, namely C_DC1 and C_DC2.

Referring to Figure 1, vectors of mains voltages and currents are given by

$$\begin{array}{c}{\overrightarrow{v}}_{RST}\left(t\right)=\left(\begin{array}{c}{v}_{RN}\left(t\right)\\ v_{SN}\left(t\right)\\ v_{TN}\left(t\right)\end{array}\right)=V_M\left(\begin{array}{c}sin\left(\omega t\right)\\ sin\left(\omega t-\phi \right)\\ sin\left(\omega t+\phi \right)\end{array}\right)\\ {\overrightarrow{i}}_{RST}\left(t\right)=\left(\begin{array}{c}{i}_R\left(t\right)\\ i_S\left(t\right)\\ i_T\left(t\right)\end{array}\right)=I_M\left(\begin{array}{c}sin\left(\omega t\right)\\ sin\left(\omega t-\phi \right)\\ sin\left(\omega t+\phi \right)\end{array}\right)\end{array}$$

(1)

with $\phi =2\pi /3$. Consequently, the corresponding pulse-width modulation signals vector is approximately (neglecting voltage drops across filter components) given by

$${\overrightarrow{m}}_{RST}\left(t\right)=\left(\begin{array}{c}{m}_R\left(t\right)\\ m_S\left(t\right)\\ m_T\left(t\right)\end{array}\right)\approx M\left(t\right)\left(\begin{array}{c}sin\left(\omega t\right)\\ sin\left(\omega t-\phi \right)\\ sin\left(\omega t+\phi \right)\end{array}\right)+m_0\left(t\right)$$

(2)

with M(t) and m₀(t) denoting the modulation index and zero-sequence component (restricted to DC in this work), respectively. Corresponding converter-imposed AC-side voltages are given by

$${\overrightarrow{v}}_{ABC}\left(t\right)=\left(\begin{array}{c}{v}_{AO}\left(t\right)\\ v_{BO}\left(t\right)\\ v_{CO}\left(t\right)\end{array}\right)={\overrightarrow{m}}_{ABC}\left(t\right)·\left(\begin{array}{cc}{v}_{DC1}\left(t\right),& {\overrightarrow{m}}_{ABC}\left(t\right)>0\\ v_{DC2}\left(t\right),& {\overrightarrow{m}}_{ABC}\left(t\right)<0\end{array}\right)$$

(3)

with v_DC1(t) and v_DC2(t) denoting partial DC link capacitors C_DC1 and C_DC2 voltages, respectively. Considering (1), the instantaneous AC-side phase power vector is given by

$${\overrightarrow{p}}_{RST}\left(t\right)=\left(\begin{array}{c}{p}_R\left(t\right)\\ p_S\left(t\right)\\ p_T\left(t\right)\end{array}\right)=\left(\begin{array}{c}{v}_{RN}\left(t\right)i_R\left(t\right)\\ v_{SN}\left(t\right)i_S\left(t\right)\\ v_{TN}\left(t\right)i_T\left(t\right)\end{array}\right)=\frac{V_M{I}_M}{2}\left(\begin{array}{c}1-cos 2\left(\omega t\right)\\ 1-cos 2\left(\omega t-\phi \right)\\ 1-cos 2\left(\omega t+\phi \right)\end{array}\right),$$

(4)

hence total AC-side power is ripple-free,

$$p_{RST}\left(t\right)=p_R\left(t\right)+p_S\left(t\right)+p_T\left(t\right)=\frac{3}{2}{V}_M{I}_M=P_{RST}.$$

(5)

On the other hand, assuming that DC-side steady-state instantaneous power is also constant, given by

$$p_L\left(t\right)=P_L,$$

(6)

the instantaneous system power balance (neglecting conversion losses and energy stored in filter components) is given by

$$P_{RST}=P_L.$$

(7)

Consequently, p_C(t) = p_C1(t) + p_C2(t) = 0 in steady state and the total DC link voltage v_DC(t) is low-frequency-ripple-free. While AC-side voltages ${\overrightarrow{v}}_{RST}\left(t\right)$ and currents ${\overrightarrow{i}}_{RST}\left(t\right)$ do not contain any zero-sequence components, converter AC-side voltages ${\overrightarrow{v}}_{ABC}\left(t\right)$ may contain such components in case of nonzero m₀(t). Consequently, converter-imposed DC-side partial power vectors are obtained as

$$\begin{array}{c}{\overrightarrow{p}}_{A1B1C1}\left(t\right)=\left(\begin{array}{c}{p}_{A1}\left(t\right)\\ p_{B1}\left(t\right)\\ p_{C1}\left(t\right)\end{array}\right)=\left\{\begin{array}{cc}\begin{array}{c}{v}_{AO}\left(t\right)i_R\left(t\right)=p_R\left(t\right)+\frac{p_0\left(t\right)}{3}\\ v_{BO}\left(t\right)i_S\left(t\right)=p_S\left(t\right)+\frac{p_0\left(t\right)}{3}\\ v_{CO}\left(t\right)i_T\left(t\right)=p_T\left(t\right)+\frac{p_0\left(t\right)}{3}\end{array},& {\overrightarrow{i}}_{ABC}\left(t\right)>0\\ 0,& {\overrightarrow{i}}_{ABC}\left(t\right)<0\end{array}\right.\\ {\overrightarrow{p}}_{A2B2C2}\left(t\right)=\left(\begin{array}{c}{p}_{A2}\left(t\right)\\ p_{B2}\left(t\right)\\ p_{C2}\left(t\right)\end{array}\right)=\left\{\begin{array}{cc}0,& {\overrightarrow{i}}_{ABC}\left(t\right)>0\\ \begin{array}{c}{v}_{AO}\left(t\right)i_R\left(t\right)=p_R\left(t\right)-\frac{p_0\left(t\right)}{3}\\ v_{BO}\left(t\right)i_S\left(t\right)=p_S\left(t\right)-\frac{p_0\left(t\right)}{3}\\ v_{CO}\left(t\right)i_T\left(t\right)=p_T\left(t\right)-\frac{p_0\left(t\right)}{3}\end{array},& {\overrightarrow{i}}_{ABC}\left(t\right)<0\end{array}\right.\end{array}$$

(8)

with p₀(t) denoting the zero-sequence power component originated by m₀(t). Consequently, converter-imposed DC-side partial powers are given by (cf. (7)) [32]

$$\begin{array}{c}{p}_{ABC1}\left(t\right)=p_{A1}\left(t\right)+p_{B1}\left(t\right)+p_{C1}\left(t\right)\approx \frac{P_L}{2}+p_0\left(t\right)+\frac{P_L}{6}sin\left(3\omega t\right)\\ p_{ABC2}\left(t\right)=p_{A2}\left(t\right)+p_{B2}\left(t\right)+p_{C2}\left(t\right)\approx \frac{P_L}{2}-p_0\left(t\right)-\frac{P_L}{6}sin\left(3\omega t\right)\end{array}.$$

(9)

In case average components of split DC link capacitors’ voltages are balanced, then m₀(t) (and thus p₀(t)) are constant. Consequently, steady-state partial DC link capacitors’ powers are given by

$$\begin{array}{c}{p}_{C1}\left(t\right)=v_{DC1}\left(t\right)C_{DC1}\frac{d{v}_{DC1}\left(t\right)}{dt}\approx \frac{P_L}{6}sin\left(3\omega t\right)\\ p_{C2}\left(t\right)=v_{DC2}\left(t\right)C_{DC2}\frac{d{v}_{DC2}\left(t\right)}{dt}\approx -\frac{P_L}{6}sin\left(3\omega t\right)\end{array}.$$

(10)

In case set points of split DC link capacitor voltages are given by $V_{DC1}^{\ast }$ and $V_{DC2}^{\ast }$, respectively, corresponding steady-state DC link capacitors’ voltages are obtained as [32]

$$\begin{array}{c}{v}_{DC1}\left(t\right)=V_{DC1}^{\ast }\sqrt{1-\frac{P_L}{9\omega {\left(V_{DC1}^{\ast }\right)}^2{C}_{DC1}}cos\left(3\omega t\right),}\\ v_{DC2}\left(t\right)=V_{DC2}^{\ast }\sqrt{1+\frac{P_L}{9\omega {\left(V_{DC2}^{\ast }\right)}^2{C}_{DC2}}cos\left(3\omega t\right)}.\end{array}$$

(11)

Furthermore,

$$\begin{array}{cc}{V}_{DC1}^{\ast }=V_{DC2}^{\ast }=V_{DC}^{\ast },& C_{DC1}=C_{DC2}=C_{DC}\end{array}$$

(12)

are typically employed, hence (11) may be generalized into

$$v_{DC1,2}\left(t\right)=V_{DC}^{\ast }\sqrt{1\pm \frac{P_L}{9\omega {\left(V_{DC}^{\ast }\right)}^2{C}_{DC}}cos\left(3\omega t\right)}.$$

(13)

Denoting the voltage rating of the split DC link capacitors as V_R, maximum steady-state capacitors’ voltages should be set to αV_R with α < 1 to allow a safety margin for prolonging the lifetime of the devices, imposing (cf. (13))

$$V_{DC}^{\ast }\sqrt{1+\frac{P_L}{9\omega {\left(V_{DC}^{\ast }\right)}^2{C}_{DC}}}=\alpha V_R.$$

(14)

Hence, split DC link capacitance value must satisfy

$$C_{DC}=\frac{P_L}{9\omega {\left(V_{DC}^{\ast }\right)}^2\left({\left(\frac{\alpha V_R}{V_{DC}^{\ast }}\right)}^2-1\right)}.$$

(15)

On the other hand,

$$v_{DC1,2}\left(t\right)\ge \left|{\overrightarrow{v}}_{RST}\left(t\right)\right|$$

(16)

must hold at all times to allow correct functionality of the converter in Figure 1, imposing the boundary condition (cf. (1) and (13))

$$V_M\sin \left(\omega t\right)=V_{DC}^{\ast }\sqrt{1-\frac{P_L}{9\omega {\left(V_{DC}^{\ast }\right)}^2{C}_{DC}}\cos \left(3\omega t\right)},$$

(17)

yielding tangency of partial DC link voltage and grid phase voltage. Hence, split DC link capacitance value must also satisfy

$$C_{DC}=\frac{P_L}{9\omega {\left(V_{DC}^{\ast }\right)}^2\left(1-{\left(\frac{V_M\sin \left(\omega t\right)}{V_{DC}^{\ast }}\right)}^2\right)}\cos \left(3\omega t\right).$$

(18)

It is important to emphasize that the boundary condition allows the minimum value of partial DC link voltage to be lower than the maximum value of the rectified grid phase voltage, as illustrated in Figure 2. Such a situation was not considered in [32]. Consequently, the two boundary conditions yield the system of the two Equations (15) and (18) which must be solved simultaneously to obtain the required values of $V_{DC}^{\ast }$ and C_DC. In order to eliminate the trigonometric form of (18), note first that

$$\cos \left(3\omega t\right)=4co{s}^3\left(\omega t\right)-3cos\left(\omega t\right), si{n}^2\left(\omega t\right)=1-co{s}^2\left(\omega t\right).$$

(19)

Then, defining

$$\mathrm{x}=\cos \left(\omega t\right),$$

(20)

letting

$$a=\frac{V_M^2}{{\left(V_{DC}^{\ast }\right)}^2} , b=\frac{P_L}{9\omega {\left(V_{DC}^{\ast }\right)}^2{C}_{DC}}$$

(21)

and substituting (19)–(21) into (18) yields

$$x^3-\frac{a}{4b}{x}^2-\frac{3}{4}x+\frac{a-1}{4b}=0.$$

(22)

Solving (22) and applying (21) returns

$$C_{DC}=\frac{2P_L}{9\omega {\left(V_{DC}^{\ast }\right)}^2\sqrt{\frac{\sqrt{3}}{72}\sqrt{1331\frac{V_M^8}{{\left(V_{DC}^{\ast }\right)}^8}-9680\frac{V_M^6}{{\left(V_{DC}^{\ast }\right)}^6}+22176\frac{V_M^4}{{\left(V_{DC}^{\ast }\right)}^4}-20736\frac{V_M^2}{{\left(V_{DC}^{\ast }\right)}^2}+6912}-3\frac{V_M^8}{{\left(V_{DC}^{\ast }\right)}^8}+\frac{23}{24}·\frac{V_M^4}{{\left(V_{DC}^{\ast }\right)}^4}+2}}.$$

(23)

Combining (15) with (23) yields

$$\frac{1}{\left({\left(\frac{\alpha V_R}{V_{DC}^{\ast }}\right)}^2-1\right)}=\frac{2}{\sqrt{\frac{\sqrt{3}}{72}\sqrt{1331\frac{V_M^8}{{\left(V_{DC}^{\ast }\right)}^8}-9680\frac{V_M^6}{{\left(V_{DC}^{\ast }\right)}^6}+22176\frac{V_M^4}{{\left(V_{DC}^{\ast }\right)}^4}-20736\frac{V_M^2}{{\left(V_{DC}^{\ast }\right)}^2}+6912}-3\frac{V_M^8}{{\left(V_{DC}^{\ast }\right)}^8}+\frac{23}{24}·\frac{V_M^4}{{\left(V_{DC}^{\ast }\right)}^4}+2}},$$

(24)

which may be solved using any available computational package to obtain the value of $V_{DC}^{\ast }$. Then, C_DC should be obtained by substituting the resulting value of $V_{DC}^{\ast }$ with (15).

3. Verification

In order to verify the proposed methodology, consider a 10 kVA LCL-filter-based three-phase three-level T-type converter, shown in Figure 3. The corresponding system parameters are summarized in

Table 1. System parameter values.

Parameter	Value	Units
VM	$230\sqrt{2}$	V
ω	$2\pi ·50$	rad/s
Lf1	$350$	μH
Cf	$10$	μF
Lf2	$10$	μH
ESR(Lf1)	$50$	mΩ
ESR(Cf)	$316$	mΩ
ESR(Lf2)	$1$	mΩ
PL	$10$	kW
VR	$360$	V
α	0.97	-

.

Simultaneous solution of (15) and (23) for the parameters in Table 1 results in

$$\begin{array}{cc}{V}_{DC}^{\ast }=327.25\left[\mathrm{V}\right],& C_{DC}=430\left[\mathsf{\mu }\mathrm{F}\right].\end{array}$$

(25)

The graphical solution is shown in Figure 4 for demonstration purposes, where the “maximum voltage imposed value” curve relates to (15) while the “minimum voltage imposed value” curve relates to (23). It is well-evident that upper and lower bound constraints on DC link voltage yield a single optimal solution.

In order to compare the required DC link capacitances’ values obtained using the methodology proposed in this paper to the results presented in [32], the value of $V_{DC}^{\ast }$ in (24) was substituted with [32], Equation (19), while taking into account the constraint stated in Section 3B of [32], namely v_DC(t) > V_M, yielding

$$\begin{array}{cc}{V}_{DC}^{\ast }=327.25\left[\mathrm{V}\right],& C_{DC}^{\left[30\right]}=876\left[\mathsf{\mu }\mathrm{F}\right].\end{array}$$

(26)

It may be concluded that by employing the proposed methodology it is possible to attain a two-fold reduction of utilized DC link capacitance compared to [32].

Split DC link capacitances valued according to (25) were assumed to possess ESR of 0.5 mΩ each in simulation to match actual devices. The converter was operated in a semi-open-loop fashion by applying pulse-width modulation signals (2) with M(t) = 325/$V_{DC}^{\ast }$ (open loop) and m₀(t) determined as shown in Figure 5 (closed loop) with NF₁₅₀ representing a 150 Hz-centered notch filter employed to eliminate the triple-mains-frequency constituent to retain a DC-only zero-sequence component similar to [30], with K denoting constant gain.

The corresponding experimental prototype shown in Figure 6 was built according to design guidelines in [38]. The converter was operated at 50 kHz switching/sampling frequency by a Texas Instruments TMS320F28335 DSP Control Card. The power stage was fed by a DC power supply and terminated by a three-phase balanced resistive load, drawing nominal power for a phase voltages magnitude of V_M = 230$\sqrt{2}$ V ≈ 325 V. Four parallel connected 110 μF electrolytic capacitors (yielding slightly higher capacitance than the analytically predicted value in order to account for ESR-imposed ripple) were employed to realize each split DC link capacitance (i.e., eight devices in total were used, as seen in Figure 6). The system was simulated using PSIM software prior to conducting full-rating matching experiments. During the experiments, a 4-channel oscilloscope was employed, hence the total DC link voltage in Figure 8 was estimated by partial DC link voltage summation using an oscilloscope Math function.

Simulated and experimental grid-side phase voltages and currents are depicted in Figure 7. It is well-evident that the system operates with unity power factor and under rated loading. Partial DC link voltages and grid-side phase voltage waveforms are shown in Figure 8. It may be concluded that the instantaneous values of partial DC link voltages are never below their grid-side phase voltages counterparts even though the global minimums of the former are below the global maximum of the latter, as expected.

4. Conclusions

The study introduces a methodology for ascertaining the minimum split DC link capacitance values in three-phase three-level DC-AC power converters that operate with unity power factor and do not involve AC zero-sequence component injection or supplementary balancing circuitry. The proposed approach relies on the tangency between partial DC link voltages and the absolute values of AC-side voltages as the boundary case to ensure appropriate power stage operation. It was shown that the proposed methodology allows for a two-fold reduction of utilized DC link capacitance compared to the previously proposed technique for the same value of the DC link voltage set point. The validity of the proposed methodology is reinforced by 10 kVA T-type converter simulations and experimental results that exhibit excellent correspondence.