A Capacitive-Feedback Amplifier with 0.1% THD and 1.18 μV_rms Noise for ECG Recording

Abstract

This paper presents an amplifier with low noise, high gain, low power consumption, and high linearity for electrocardiogram (ECG) recording. The core of this design is a chopper-stabilized capacitive-feedback operational transconductance amplifier (OTA). The proposed OTA has a two-stage structure, with the first stage using a combination of current reuse and cascode techniques to obtain a large gain at low power and the second stage operating in Class A state for better linearity. The amplifier additionally uses a DC servo loop (DSL) to improve the rejection of DC offsets. The amplifier is implemented in a standard 0.13 μm CMOS process, consuming 1.647 μA current from the supply voltage of 1.5 V and occupying an area of 0.97 mm². The amplifier has a 0.5 Hz to 6.1 kHz bandwidth and 59.7 dB gain while having no less than a 65 dB common-mode rejection ratio (CMRR). The amplifier’s total harmonic distortion (THD) is less than 0.1% at 800 mV_pp output. The amplifier can provide a noise level of 1.18 μV_rms in the 0.5 Hz to 500 Hz bandwidth that the ECG signal is interested in and has 3.38 μV_rms input-referred noise (IRN) over the entire bandwidth, so its noise efficiency factor (NEF) is 2.13.

1. Introduction

With miniaturization and the low power consumption of electronic devices and sensors, the integration of wearable devices into people’s live is becoming increasingly common, allowing people to achieve long-term monitoring of infrastructure, environment, and health status [1]. From the perspective of people’s disease prevention, long-term health detection is necessary to help people to know their health status. The application of prolonged wearable devices places high demands on analog front-end (AFE) amplifiers, especially in low power consumption and noise. Common bio-potential signals include electrocardiogram (ECG), electroencephalogram (EEG), and electromyography (EMG) signals. Bio-potential signals can directly reflect a person’s physical state and are closely related to health parameters [2,3,4]. The electrocardiogram, as an important auxiliary tool for the diagnosis of myocarditis and acute heart failure, is often used to detect various cardiovascular diseases caused by arrhythmia [5,6,7]. These signals are usually with a tiny amplitude and low frequency, so the monitoring amplifier needs to have low-noise and high-gain characteristics. Portable biomedical signal detection devices are usually powered by batteries, so low power consumption is also critical.

There has been much research on the AFE circuit of ECG sensors, especially in terms of power, noise, and linearity. The main goal of low-power design is to maximize the transconductance of amplifiers under bias current, so the current reuse technique is widely used to reduce the power consumption of amplifiers [8]. Work [8] applies current reuse technology to multi-channel sensing, where the current is reused between multiple channels, and isolation is achieved through orthogonal bias. Work [2] applies current reuse technology to auxiliary amplifiers, reusing the current of the operational transconductance amplifier (OTA) with driven-right-leg (DRL) [9] circuits used to improve the common-mode rejection ratio (CMRR). Of course, most works apply current reuse technology to input differential pair [10]. Work [11] uses current reuse techniques in the input stage of amplifiers to reduce the amplifier power consumption, but the gain is low because of the inverter-based structure of the amplifier. Work [12] utilizes the stacking of OTA for noise and power efficiency improvements, but this multi-stacking structure limits the output swing. The chopper-stabilized technique is usually used to reduce the flicker noise of the ECG amplifier [12,13,14]. The chopper-stabilized technique requires OTA to have higher bandwidth, although it can significantly reduce the flicker noise. In order to suppress the DC electrode offsets of the ECG signal, many designs use a capacitive-feedback structure [11,13,15], which is AC coupling to create a high-pass characteristic with DC input resistance approaching infinity. In addition, some designs use an additional DC servo loop (DSL) to suppress the electrode DC offset (EDO), which can be achieved in various ways. Work [16] uses an analog integrator to achieve this, work [17] uses IDAC, which relies on an analog-to-digital converter (ADC) to achieve it, and work [18] adds a digital loop on top of the analog integrator to further improve the suppression of the DC offset. Many designs use the combination of these techniques to achieve low noise, high linearity, and low power consumption in the design of biomedical signal amplifiers [12,13,14,19,20,21]. Moreover, current feedback amplifiers are also used for the ECG recording amplifier, which have the advantages of a high CMRR and compact area [22]. A design of a current feedback amplifier is proposed in [23], which has a CMRR up to 120 dB with the cost of higher power consumption.

Our work focuses on the problem of low gain in a conventional current reuse inverter-based amplifier and small dynamic range in a conventional cascode amplifier. By directly combining cascode technology, current reuse, and chopping stabilization, high gain is provided under low power consumption. A high gain low-noise amplifier helps reduce the dependence of the programmable gain amplifier (PGA) and reduces the noise contribution of PGA in the ECG monitoring AFE. This paper describes an amplifier with low power, low noise, high gain, and low total harmonic distortion (THD) based on chopper-stabilized, capacitive-feedback, and current reuse techniques. The design combines cascode and the current reuse technique to achieve high gain with low power consumption, and we use two-stage OTA to achieve a 59.7 dB closed-loop gain. The design is optimized for linearity in the output stage and profits from the relatively higher supply voltage. High linearity can be maintained when the output amplitude is large, which makes the design have a THD of 0.1%. We use chopper stabilization to eliminate flicker noise, and the input-referred noise (IRN) can reach 1.18 μV_rms over 0.5 Hz to 500 Hz.

We organize this paper as follows: Section 2 presents the overall structure of this low-power amplifier. Section 3 presents the circuit details of the amplifier, and specific analysis is performed for the core circuit. The simulation results are presented in Section 4, and Section 5 concludes this paper. The design is verified by the Cadence software (San Jose, CA, USA) and Spectre simulator.

2. System Structure

In this design, the amplifier is a fully differential structure with a capacitive-feedback technique, chopper-stabilized technique, and DC servo loop. The system structure is shown in Figure 1. The amplifier adopts a fully differential structure to enhance the CMRR and power supply rejection ratio (PSRR). The fully differential structure reduces even harmonics, leading to lower THD levels. The THD is a vital parameter to consider when designing an ECG recording amplifier. We use the current reuse technique to reduce power consumption in the OTA. The OTA has high open-loop gain to ensure minimal error in the closed-loop gain.

The capacitive-feedback amplifier offers high input impedance and a high-pass characteristic, which enhances its ability to suppress the DC offset. Due to the isolation of the DC level through AC coupling, the input of OTA does not receive a DC level. As a solution, two large resistors, $R_{CM1}$ and $R_{CM2}$, are utilized to provide a DC level $V_{CM}$ to OTA. To achieve higher input impedance, we use appropriate capacitance values. It is worth noting that the capacitor does not add noise but rather amplifies the amplifier’s noise through parasitic effects. However, the capacitive-feedback’s overall noise level is better than that of the resistive-feedback. Therefore, a capacitive-feedback structure achieves the low-power and low-noise design requirements more easily than a resistive-feedback structure.

The chopper-stabilized circuit is employed to minimize the flicker noise. The chopper circuit mixes the useful signal up to the chopper frequency. After amplification by the amplifier, the low-frequency flicker noise is introduced. The useful signal on the chopper frequency is amplified, and then through a chopper, the useful signal on the chopper frequency is moved to DC. At the same time, low-frequency flicker noise is moved to the chopper frequency to eliminate the flicker noise.

The DC servo loop is included in the amplifier to eliminate the output offset caused by the mismatch and reduce the input DC offset. This loop integrates the output DC offset using an integrator and feeds it back to the input of the OTA to eliminate the DC offset. Since the chopper mixes the signal to $f_{sig}+f_{ch}$ at the input of OTA, the DSL output signal must also be modulated to $f_{sig}+f_{ch}$ by the chopper:

$$H_{AMP}\left(s\right)=\frac{A_{DC}}{1+\frac{s}{p_{AMP}}}$$

(1)

This design must analyze the overall transfer function and design bandpass transfer function to meet the bandwidth requirements of ECG recording. The chopper only mixes the signal up at the input and down at the output. It can be considered that all signals at the input end of the amplifier are at $f_{sig}+f_{ch}$, while all signals at the output are at the $f_{sig}$ frequency. Moreover, since the first-order coefficient of the Fourier series of the square wave is not 1, it will lead to a decline in the gain of the amplifier [24]. However, the frequency transfer effect of chopping will not be considered temporarily to simplify the analysis. To analyze the amplifier, we use a first-order approximation based on the equation shown in Equation (1). In Equation (1), $A_{DC}$ represents the DC gain of the OTA, while $p_{AMP}$ represents the time constant of the OTA. So the overall transfer function is Equation (2):

$$H_{SYS}=\frac{V_{OUT}\left(s\right)}{V_{IN}\left(s\right)}=\frac{s{R}_{CM1,2}{R}_{DSL1,2}{C}_{IN1,2}{C}_{DSL1,2}{A}_{DC}}{s^2{D}_2+s{D}_1+D_0},$$

(2)

where

$$D_2=R_{DSL1,2}{C}_{DSL1,2}{p}_{AMP}·(R_{CM1,2}{C}_{IN1,2}+R_{CM1,2}{C}_{DSL3,4}+R_{CM1,2}{C}_{FB1,2}),$$

(3)

$$D_1=R_{DSL1,2}{C}_{DSL1,2}·(R_{CM1,2}{C}_{FB1,2}{A}_{DC}+R_{CM1,2}{C}_{IN1,2}+R_{CM1,2}{C}_{DSL3,4}+R_{CM1,2}{C}_{FB1,2}+p_{AMP}),$$

(4)

$$D_0=R_{CM1,2}{A}_{DC}{C}_{DSL3,4}+R_{DSL1,2}{C}_{DSL1,2}.$$

(5)

By analyzing Equation (2), we can observe that there are two poles $p_1$ and $p_2$ and one zero $z_1$. If the frequency interval between two poles is far enough, meaning $p_1\ll p_2$, two poles satisfy the following:

$$p_1\approx -\frac{D_0}{2\pi D_1}=-\frac{R_{CM1,2}{A}_{DC}{C}_{DSL3,4}+R_{DSL1,2}{C}_{DSL1,2}}{2\pi R_{DSL1,2}{C}_{DSL1,2}·(R_{CM1,2}{C}_{FB1,2}{A}_{DC}+R_{CM1,2}{C}_{IN1,2}+R_{CM1,2}{C}_{DSL3,4}+R_{CM1,2}{C}_{FB1,2}+p_{AMP})},$$

(6)

$$p_2\approx -\frac{D_1}{2\pi D_2}=\frac{R_{CM1,2}{C}_{FB1,2}{A}_{DC}+R_{CM1,2}{C}_{IN1,2}+R_{CM1,2}{C}_{DSL3,4}+R_{CM1,2}{C}_{FB1,2}+p_{AMP}}{2\pi p_{AMP}·(R_{CM1,2}{C}_{IN1,2}+R_{CM1,2}{C}_{DSL3,4}+R_{CM1,2}{C}_{FB1,2})},$$

(7)

$$z_1=0.$$

(8)

After analyzing the circuit, it is clear that $C_{IN1,2}$ and $C_{FB1,2}$ determine the passband gain, gain $=C_{IN1,2}/C_{FB1,2}$. The design requires a closed-loop gain of 60 dB, which means that $C_{IN1,2}$ is 1000 times $C_{FB1,2}$. In this design, $C_{IN1,2}$ is set to 50 $pF$, and $C_{FB1,2}$ is set to 50 $fF$. The circuit has one zero and two poles, resulting in a bandpass characteristic for the overall frequency response of the amplifier.

3. Circuit Design

3.1. Architecture of OTA

The OTA adopts a two-stage structure with Ahuja compensation to provide a higher open-loop gain and reduce the closed-loop gain error. The circuit structure of the amplifier is shown in Figure 2.

The first stage adopts the cascode structure with current reuse, which can provide a gain of 84 dB. This design stacks seven transistors between VDD and GND, so the OTA has specific requirements for the voltage headroom. Even though transistors work in the subthreshold region, there are still high demands for supply voltage and voltage distribution. However, a higher supply voltage leads to higher power consumption, which is harmful in the ECG amplifier design. Therefore, the current reuse technique is introduced based on the cascode structure. The equivalent transconductance at a unit current can be doubled by adding an NMOS differential pair to the PMOS differential pair, allowing the same gain to be achieved with less current consumption. In addition, the dual tail current source structure is adopted to improve the PSRR.

We use the common source structure in the second stage to produce a larger output swing. Although the drive capability of this structure is lower than that of the inverter structure, it operates in the Class A state, giving it an advantage. Compared with the inverter structure working in the Class AB state, the common source structure will have better linearity and smaller THD. The second stage uses the cascode current mirror as the load, which may slightly reduce the output swing but will achieve a better PSRR. The output swing remains ample despite the limit of the cascode load, thanks to the higher supply voltage. To stabilize the loop, a frequency compensation capacitor $C_{C1,2}$ is added between the input and output of the second stage. However, the traditional Miller compensation generates a zero in the right half plane due to the feedforward effect. The Miller compensation needs to add a zeroing resistance to avoid a zero. In this design, the cascode structure’s characteristics are ingeniously used to connect the Miller compensation capacitor between the drain of $M_{9,10}$ and the source of $M_{5,6}$ [25]. The isolation effect of $M_{5,6}$ allows the feedback current to flow through the capacitor while preventing the feedforward current. This structure avoids the generation of zeroes without additional power consumption.

3.2. Analysis of Output Swing

This operational amplifier has a wide input range thanks to the current reuse technique of NMOS and PMOS as input differential pairs. The capacitive-feedback technique ensures that the input common-mode voltage is fixed and the differential mode signal generated by ECG is tiny, making it easy to meet the input range. However, the amplifier has high gain, making the output swing crucial for the large gain to be reflected. In the two-stage OTA, the output stage’s output swing will be the entire amplifier’s bottleneck. The output stage of the proposed amplifier uses a common source structure with the cascode current mirror as a load. A simple analysis of it reveals that

$$V_{High}=VDD-V_{ds11,12,13}-V_{ds14,15,16},$$

(9)

$$V_{Low}=GND+V_{gs9,10}.$$

(10)

For high output voltage, in order for the PMOS cascode current mirror to operate in the saturation region, it is necessary to ensure that

$$V_{ds11,12,13}\ge V_{dsat11,12,13},$$

(11)

$$V_{ds14,15,16}\ge V_{dsat14,15,16}.$$

(12)

Therefore, it can be concluded that the maximum output voltage of the output stage is

$$V_{High}\le VDD-V_{dsat11,12,13}-V_{dsat14,15,16}.$$

(13)

Similarly, to ensure that input transistor $M_{9,10}$ is in the saturation zone when the output voltage is low, $V_{ds9,10}\ge V_{dsat9,10}$, so the minimum output voltage is $V_{Low}\le V_{dsat9,10}$. Therefore, the output swing can be expressed as

$$V_{swing}=V_{High}-V_{Low}\le VDD-V_{dsat11,12,13}-V_{dsat14,15,16}-V_{dsat9,10}\cong VDD-3·V_{dsat}.$$

(14)

It is feasible to sacrifice some of the output swing to achieve a higher gain using the cascode load, despite leading to a decrease by $V_{ds}$. With a 1.5 V supply voltage and around 0.2 V $V_{ds}$, a single end can reach an output swing of approximately 0.9 V, while a differential swing can go up to 1.8 V. This output swing is sufficient for ECG signals with smaller amplitudes, even after 60 dB amplification.

3.3. Analysis of Transfer Function

It is necessary to split and simplify the circuit to obtain a transfer function of OTA simply and intuitively. The proposed OTA structure extensively adopts a cascode structure. Therefore, we analyze the cascode structure first. This structure is shown in Figure 3. We simplify it into a small-signal model as shown in Figure 3, where $g_{ma}$ and $r_{oa}$ are the transconductance and on-resistance of $M_a$, and $g_{mb}$ and $r_{ob}$ are the transconductance and on-resistance of $M_b$. The equivalent output impedance of this structure is $r_{oa}+r_{ob}+(g_{mb}+g_{mbb})·r_{oa}·r_{ob}$, where $g_{mbb}$ is the back gate transconductance of $M_b$. Usually, $(g_{mb}+g_{mb})·r_{oa}·r_{ob}\gg r_{oa}$, $(g_{mb}+g_{mb})·r_{oa}·r_{ob}\gg r_{ob}$, and $g_{mb}$≫$g_{mb}$, so the output impedance of cascode structure $R_O$ is simplified as $g_{mb}·r_{oa}·r_{ob}$. The small signal current generated by the transistor $M_a$ is diverted to GND by on-resistor $r_{oa}$, so the equivalent transconductance $G_m$ will be slightly smaller than $g_{ma}$. To simplify the analysis, an equivalent transconductance $G_m$ can be approximately equal to $g_{ma}$, and this error can be almost negligible.

Considering the frequency response of the cascode structure is essential. Except for the pole at the output, a pole also is generated between the drain of $M_a$ due to the parasitic capacitance of the transistors, especially the influence of $M_b$’s $C_{gs}$. However, the capacitance value at this point is minimal, paralleling $C_{bgs}$, $C_{agd}$, and $C_{ads}$, while the resistance is approximately the parallel connection of $1/g_{mb}$ and $r_{oa}$. Thus, the pole will be located at high frequencies, far higher than the frequency range of concern in this design, so it can be ignored. The cascode structure can be Norton equivalent to a voltage-controlled current source in parallel with an output resistor as shown in Figure 3, where the values of the equivalent transconductance $G_m$ and equivalent resistance $R_O$ are shown in Equations (15) and (16):

$$G_m=g_{ma}.$$

(15)

$$R_O=g_{mb}·r_{oa}·r_{ob}.$$

(16)

Small-signal model of the OTA can be obtained by representing all cascode structures as equivalent transconductance and equivalent output resistance as shown in Figure 4.

In Figure 4, $G_{mn}$ and $G_{mp}$ are the equivalent transconductance of the first-stage NMOS cascode structure and PMOS cascode structure. $R_{eq1}$ is the equivalent output resistance of the first stage, which is the parallel resistance of the NMOS cascode structure’s output impedance $R_{ON1}$ and PMOS cascode structure’s output impedance $R_{OP1}$. $C_{p1}$ is a parasitic capacitance at the first stage’s output node, mainly the $C_{gs9}$ of $M_9$. The transconductance of the second-stage input transistor is $g_{m9}$, and the equivalent output impedance of the second-stage $R_{eq2}$ is on-resistance $r_{O9}$ and output impedance $R_{ON2}$ of the cascode current source in parallel. The frequency compensation capacitor is connected between the input and output of the second stage, and the virtual ground is created by the isolation effect of Ahuja compensation on feedforward. The first-stage DC gain is $A_{V1}=-(G_{mn1}+G_{mp1})·R_{eq1}$, and the second-stage DC gain is $A_{V2}=-g_{m9}·R_{eq2}$. After simplification, the transfer function can be easily obtained as shown in (17). It can be seen that the OTA has two poles within the concerned frequency range. The secondary pole locates at the output terminal, while the dominant pole is at the first-stage output. The frequency compensation capacitor splits the two poles, ensuring the stability of the OTA [26]:

$$A_V=\frac{g_{m9}(G_{mn}+G_{mp})R_{eq1}{R}_{eq2}}{{\alpha }_2{s}^2+{\alpha }_{1}s+1},$$

(17)

where

$${\alpha }_2=R_{eq1}{R}_{eq2}{C}_{p1}(C_L+C_C),$$

(18)

$${\alpha }_1=R_{eq1}{C}_{p1}+R_{eq2}{C}_L+R_{eq2}{C}_C+g_{m9}{R}_{eq1}{R}_{eq2}{C}_C.$$

(19)

It should be noted that this analysis does not take into account the gain decrease caused by the chopper. If considering the mixing effect caused by the chopper, the low-frequency gain needs to be multiplied by a coefficient of 2/$\pi$ [27].

3.4. Analysis of Noise

For this particular design, it is essential to consider the noise analysis [28,29]. The ECG recording amplifier’s noise mainly originates from the OTA. All transistors are biased in the subthreshold region in this design to improve the noise-to-power efficiency [30]. The thermal current noise density of MOS transistors that operate in the subthreshold region can be expressed as

$$\overline{i_{n,t}^2}=2kTn{g}_m.$$

(20)

Among them, k is the Boltzmann constant, T is the absolute temperature, n is the subthreshold slope factor, and $g_m$ is the transconductance of the transistor. In low-frequency applications, in addition to thermal noise, the flicker noise of transistors cannot be ignored, which can be expressed as

$$\overline{i_{n,f}^2}=\frac{g_m^{2}K}{C_{OX}WLf}$$

(21)

where $g_m$ is the transconductance of the transistor, K is a process-related constant, $C_{OX}$ is the gate-oxide capacitance per unit area, W and L are the channel width and length of the transistor, and f is the frequency. So the noise of each MOSFET includes thermal noise and flicker noise, which can be represented as

$$\overline{i_n^2}=\overline{i_{n,t}^2}+\overline{i_{n,f}^2}=2kTn{g}_m+\frac{g_m^{2}K}{C_{OX}WLf}.$$

(22)

In order to achieve low noise, the chopper-stabilized technique can reduce flicker noise at the cost of power consumption and design complexity.

For the first stage of the OTA, thermal noise and flicker noise are equivalent to the input-referred noise voltage:

$$\overline{v_{n,in1}^2}=\frac{2}{{(G_{mn}+G_{mp})}^2}·(\overline{i_{n1,2}^2}+\overline{i_{n7,8}^2}+\frac{\overline{i_{n3,4}^2}}{g_{m3,4}^2{r}_{O3,4}^2}+\frac{\overline{i_{n5,6}^2}}{g_{m5,6}^2{r}_{O7,8}^2}).$$

(23)

For the second stage of this design, thermal noise and flicker noise are equivalent to the input-referred noise voltage of the first stage:

$$\overline{v_{n,in2}^2}=\frac{2}{{(G_{mn}+G_{mp})}^2·g_{m9,10}^2·R_{eq1}^2}·(\overline{i_{n9,10}^2}+\frac{\overline{i_{n14,16}^2}}{g_{m14,16}^2{r}_{O15,17}^2}).$$

(24)

To obtain the total input-referred noise voltage of the OTA, divide the input-referred noise voltage of the second stage by the gain of the first stage. It is important to note that since the first- and second-stages’ noise are unrelated, their noise can be added together directly. Due to the large gain of the first stage, the noise of the second stage equivalent to the OPA input will be very small, even negligible. The total input-referred noise voltage of the OTA can be expressed as

$$\overline{v_{n,in}^2}=\overline{v_{n,in1}^2}+\overline{v_{n,in2}^2}\approx \overline{v_{n,in1}^2}=\frac{2}{{(G_{mn}+G_{mp})}^2}·(\overline{i_{n1,2}^2}+\overline{i_{n7,8}^2}+\frac{\overline{i_{n3,4}^2}}{g_{m3,4}^2{r}_{O3,4}^2}+\frac{\overline{i_{n5,6}^2}}{g_{m5,6}^2{r}_{O7,8}^2}).$$

(25)

In this way, the overall input-referred noise voltage of the proposed OTA is given. It can be seen that the four input transistors of the first stage contribute the most, so the area of these four transistors is increased to further reduce the flicker noise. Considering the suppressive effect of the chopper on the flicker noise of $M_{1,2,7,8}$, the flicker noise of $M_{1,2,7,8}$ can be ignored, and the total noise can be expressed as

$$\overline{v_{n,in}^2}\approx \frac{2}{{(G_{mn}+G_{mp})}^2}·(2kTn{g}_{m1,2}+2kTn{g}_{m7,8}+\frac{\overline{i_{n3,4}^2}}{g_{m3,4}^2{r}_{O3,4}^2}+\frac{\overline{i_{n5,6}^2}}{g_{m5,6}^2{r}_{O7,8}^2}).$$

(26)

The thermal noise of the transistor is closely related to its transconductance. When the overdrive voltage of transistor is kept constant, the transconductance is determined by drain current $I_D$. Therefore, using the current reuse technique can help reduce the thermal noise of the transistor.

Feedback is provided to the first-stage NMOS tail current source to ensure the output common-mode voltage using a typical continuous time common-mode feedback structure as shown in Figure 5. The resistance detects the common-mode voltage and feedback to the gate of the tail current source through an error amplifier to achieve closed-loop feedback control. Choosing an extremely high resistance value is crucial to prevent the common-mode voltage detection resistor from affecting the gain. However, a large resistor can create a pole with the transistor’s parasitic capacitor. A capacitor can be connected in parallel to generate a zero to counteract the pole. We use the diode-connected NMOS transistors as the load to lower the gain of the error amplifier and maintain the stability of the common-mode feedback loop.

4. Results

We implemented the proposed ECG recording amplifier using the 0.13 μm CMOS process. Figure 6 shows the amplifier’s layout, with an effective area of 0.97 mm². The input capacitors occupy most of the area.

Based on our simulation results, the proposed amplifier has a total current consumption of 1.647 μA from a 1.5 V supply voltage. The overall power consumption is 2.471 μW. As shown in Figure 7, the current distribution is as follows: the first stage of OTA consumes 780.226 nA, the second stage consumes 417.81 nA, the common-mode feedback loop consumes 184.933 nA, the DSL consumes 205.772 nA, and the bias circuit consumes 58.142 nA.

Figure 8 displays the amplifier’s frequency response, indicating the closed-loop mid-band gain of 59.7 dB and the bandwidth ranging from 0.5 Hz to 6.1 kHz. Additionally, Figure 8 illustrates the common-mode gain and VDD-to-DM gain. The CMRR exceeds 87 dB within bandwidth, while the PSRR exceeds 70 dB.

A 100 Hz single-tone signal is utilized for testing to evaluate the THD performance of the amplifier. The output signal is simulated at 800 mV_pp, and a 2048-point DFT is conducted. Figure 9 displays the resulting spectrum. Statistical analysis reveals a THD of 0.07%.

We simulate the noise performance and demonstrate the effect of the chopper-stabilized technique as shown in Figure 10. Without the chopper-stabilized technique, the input-referred noise is 4.8 μV_rms integrated from 0.5 Hz to 500 Hz. However, when the chopper-stabilized technique is enabled, the input-referred noise is significantly reduced to 1.18 μV_rms. Moreover, the input-referred noise within the entire bandwidth is 3.38 μV_rms:

$$\mathrm{NEF}=V_{IRN,rms}\sqrt{\frac{2I_{tot}}{\pi ·4kT{V}_T·BW}}.$$

(27)

NEF is an essential parameter to measure the amplifiers’ noise and consumption current [31]. The calculation for NEF is provided in Equation (27), wherein $V_{IRN,rms}$ represents the IRN within the bandwidth, $I_{tot}$ denotes the total consumption current, and $BW$ stands for the bandwidth. The formula considers k as the Boltzmann constant, T as the absolute temperature, and $V_T$ as the thermal voltage. The NEF is calculated as 2.13 for this particular design.

We summarize the performance of this design and compare them with relevant designs in recent years as shown in

Table 1. Performance comparison with the states of the art.

	[11] TBCAS’18	[13] TCS II’19	[20] SSCL’19 a	[32] TBCAS’21	[33] ACCESS’20	[34] ACCESS’21	This Work b
Technology	0.35 μm	0.18 μm	0.18 μm	0.35 μm	0.18 μm	28 nm	0.13 μm
Area (mm2)	0.18	0.46	0.08	0.071	0.025	0.05	0.97
Voltage (V)	2	1.2	0.6, 1.2	2	1.8	1	1.5
Current (A)	160 n	2 μ	N.A.	0.336 μ	N.A.	1 μ	1.647 μ
Power (W)	320 n	2.4 μ	2.6 μ	0.672 μ	7.6 μ	1 μ	2.471 μ
Gain (dB)	39.8	40	41–59	40.6	14	39.5	59.7
Bandwidth (Hz)	0.2–200	0.5–500	200	7.84m-300	0.01–23 k	1 k	0.5-6.1 k
Input-Referred Noise (μVrms)	2.05 (0.1–10 kHz)	1.8 (0.5–500 Hz)	3.2	1.54 (0.1–300 Hz)	N.A.	2.74 (1–200 Hz)	1.18 (0.5–500 Hz)
THD	<1% 20 Hz 15 mVpp Input	0.01% 69 Hz 800 mVp Output	1.7% 1 kHz 1 mVpp Input	0.12% 100 Hz 5 mVp Input	−49 db 1 kHz 1 mVpp Input	−52.6 dB 100 Hz 1.5 mVp Input	<0.1% 100 Hz 800 mVpp Output
CMRR (dB)	>65	>90	70	83.24	61	94	≥87
PSRR (dB)	>70	N.A.	N.A.	84.2	57	79	≥70
NEF	2.26	4.4	3.2	2.02	4.7 c	7.5	2.13

^a Represents the results of the neural amplifier for the action potential. ^b Represents the simulation results. ^c Represents NEF of the neural amplifier for the action potential.

. Through comparison, we discover that this design has low noise (IRN of 1.18 μV_rms and NEF of 2.13) and high linearity (THD of 0.1%).

5. Conclusions

This article presents a new amplifier for ECG recording using a 0.13 μm CMOS process. The amplifier achieves low power, high gain, low noise, and high linearity through chopper-stabilized and current reuse techniques. The amplifier can maintain a large gain by implementing the OTA using the current reuse technique while reducing power consumption. The chopper-stabilized technique achieves low noise and minimizes flicker noise in low-frequency biomedical signals. The fully differential structure is used to suppress odd harmonics. The output stage operates in the Class A state with a higher power supply voltage, resulting in a lower THD when the output signal is large. The simulation results show that the design has advantages, such as high linearity, low power consumption, and low noise. Moreover, thanks to the wider signal bandwidth and larger gain, this design can be used not only for ECG recording but also for other biomedical signal monitoring, such as EEG, EMG, and more.