A Compact 5 GHz Power Amplifier Using a Spiral Transformer for Enhanced Power Supply Rejection in 180-nm CMOS Technology

Abstract

We present a compact 5 GHz, class A power amplifier (PA) applicable for a wireless combo-chip that supports multiple radio systems in 180 nm CMOS technology. The proposed two-stage linear PA consists of a cascode input stage with a transformer-based balun, combined with a balancing capacitor as the load, where the single-ended signal is converted into the balanced output and a second-stage, class A push–pull amplifier with another transformer-based balun, which efficiently combines the output power differentially to drive a single-ended 50 Ω load. The proposed single-ended PA with an internal balanced configuration can achieve a power supply rejection ratio of 9.5 to 65.9 dB at 0.1 to 3.5 GHz, which is around a 12 to 37 dB improvement compared to a conventional single-ended PA with the same power gain. The results show that the proposed PA has a gain of 15.5 dB, an output-referred 1 dB gain compression point of 13 dBm, an output intercept point of 22 dBm with a 5 MHz frequency offset, an output saturated power of 15.4 dBm, and a peak power-added efficiency of 15%. The implemented PA consumes a DC current of 72 mA under 1.8 V supply. The core chip size is 0.65 mm² without pads.

1. Introduction

In wireless communication for mobile applications, a power amplifier (PA) is an essential block in the radio frequency (RF) front-end. The PA must not only deliver the necessary power efficiently, but also should be robust towards the common mode interferences from other blocks around it. Notably, a robust design to cope with interference should be accomplished in multiple radio applications, since various wireless systems are combined in a single chip. A PA requires various design trade-offs between the supply voltage, output power, power efficiency, and linearity, in order to meet the desired specifications. Many researchers have put enormous effort and showed significant interest in improving the linearity and the efficiency of Pas, while lowering power consumption with low cost [1,2]. Although a switch-mode PA theoretically has 100% of the drain efficiency, it cannot be directly applicable to the modulation scheme, which utilizes the amplitude of the transmitting signal. To overcome this issue, a polar power amplifier has been introduced using a mixed-signal technique [3]. However, the size of the mixed-signal, 2.4 GHz PA is bulky (3.06 mm²), due to the extra RF digital-to-analog converter for the polar operation. Moreover, the switch-mode PA may generate a large amount of interference from the digitally-oriented blocks, which can seriously contaminate sensitive analog/RF blocks that are integrated into the same chipset.

The linearity of the PA directly affects the whole performance of a modern wireless system. In IEEE 802.11a wireless LAN applications, orthogonal frequency-division multiplexing (OFDM) is typically used to provide fast data rates at 5 GHz; this requires a high linear power amplifier, since the linearity of the power amplifier determines the data rates of the communication [4]. Contrary to the switch-mode PA, the linear PA can support any modulation scheme without limitations. Among them, the class A PA has the highest linearity and lowest distortion, both of which are essential characteristics for wireless communication [1,2]. With a differential configuration, the class A PA can also achieve an excellent common-mode rejection, with relatively good power-added efficiency (PAE) with an inductive load. Therefore, class A PAs have been widely used in practice, specifically in WLAN transceivers [5]. Unfortunately, a typical single-ended PA has a poor common-mode rejection, which is not directly applicable to a combo-chip with multiple wireless transceivers integrated into a single chipset.

In this paper, we present a compact class A PA for operation at 5 GHz. Since the power supply noise can combine with the RF signal and reduce the performance of the power amplifier [6], the proposed PA utilizes an on-chip transformer balun to achieve improved power supply rejection ratio, as well as a compact design. At the output of the first stage, the balun with a balancing shunt capacitor converts the single-ended signal to a differential one, which also works as the inter-stage matching network, while the second balun combines the output power and converts the output port from the differential to the single-ended configuration. With this architecture, the proposed PA can achieve substantially improved RF power supply rejection under multiple radio-system scenarios while delivering consistent performance, with a saturated power output of 15.4 dBm and a peak PAE of 15%. The implemented PA consumes only 0.65 mm² without pads, owing to the transformer-based compact baluns.

2. Circuit Design

The schematic diagram of the proposed PA is illustrated in Figure 1. Input matching is performed with C₁, L₁, and source degeneration inductor L_S. C₁ and L₁ are also used together as a biasing circuit. The input stage of the PA is a cascode structure, to improve the voltage gain of the driving amplifier. A compact on-chip balun is realized by modifying a symmetric inductor whose half of a winding coil is magnetically coupled to the other half, in order to convert a single-ended signal to a balanced output by connecting the center tap to the power supply node. The converted differential output from the balun of the first stage is amplified by the second-stage, differential, common-source amplifier, having the primary coil of the second transformer as the load. Then the differential output is converted to the single-ended output, using the transformer-based balun. Therefore, when we assume a reasonable input and output matching condition, the magnitude of the transducer power gain (G_T) in differential mode at the center frequency (f_o = ω_o/2π) can be approximated as

$$G_T=\frac{P_L}{P_{avs}}\approx {\eta }_M{Q}_i{}^2{R}_o\left[\frac{{\left(g_{m1}{Q}_{T1}{\omega }_o{L}_{T1P}\right)}^2}{1+{\left(g_{m1}{\omega }_o{L}_S\right)}^2}\right]\left[\frac{g_{m2}{}^2{r}_{o3}{Q}_{T2P}{\omega }_o{L}_{T2P}}{r_{o3}+Q_{T2P}{\omega }_o{L}_{T2P}}\right]{\eta }_T$$

(1)

$${\eta }_M\approx \frac{1}{1+\frac{r}{Q_i{}^2}}$$

(2)

$${\eta }_T=\frac{1}{1+\frac{2}{Q_{T2P}{Q}_{T2S}{k}^2}+2\sqrt{\frac{1}{Q_{T2P}{Q}_{T2S}{k}^2}\left(1+\frac{1}{Q_{T2P}{Q}_{T2S}{k}^2}\right)}}$$

(3)

where R_o is the source and load impedance; Q_i = 1/ωC_gs1R_o, Q_T1 is the quality factor (Q-factor) of the first transformer (TF₁); η_M, and η_T are the power efficiency of the input (L-matching) and output (TF₂) matching networks, respectively [7]; the resistance transformation ratio r = R_o/Re{Z_in} = 1; k is the magnetic coupling coefficient; and Q_T2P and Q_T2S are the Q-factors of the primary and secondary coil of the TF₂, respectively.

The symmetric spiral inductor is used as a balun to provide a differential signal to the second stage. In addition, it suppresses the RF interferences from the supply node [8]. For the designed balun, L_T1P and L_T1S are both 1.425 nH, and their resistances are 4.372 Ω (quality factor (Q) = 10.2) and 4.744 Ω (Q = 9.4), respectively; the difference in Q of the symmetric inductor is because L_T1S includes two bridges with a thin metal layer (M5), as presented in Figure 1. The thickness of M5 is 0.525 μm, while that of layer M6 is 2.1 μm, which means that L_T1S is more resistive than L_T1P. Note that symmetric inductors are widely used instead of two spiral inductors, because this saves on the circuit area and results in a higher Q [9].

A tunable balancing capacitor of 410 fF is employed at one of the TF₁ output ports to emulate parasitic capacitance from the drain node of the cascode structure, so that the power supply rejection ratio (PSRR) and the drain efficiency can be significantly improved. The power supply rejection ratio (PSRR) is given by

$$PSRR(dB)=20\log \frac{\Delta V_{DD}}{\Delta V_{OUT}}$$

(4)

The value of C_Balance is chosen to balance out the voltage at each differential node, which improves the achieved balance of the output. Figure 2 shows the parametric sweep of the symmetric inductor (L_T1P,S), the balancing capacitance (C_balance), and the inductance of the output transformer (L_T2P,S), which shows that other circuit parameters, except C_balance, are not critical to the interference suppression from the supply. By sweeping C_Balance from 200 fF to 750 fF, it indicates that 410 fF of C_Balance optimally balances the output voltage at the differential node, while providing approximately 180° of phase difference.

Figure 3 shows the simulated PSRR comparison between a conventional PA, the proposed PA, and the proposed PA without C_Balance. At the operating frequencies of the various wireless communication systems that can be integrated into a single chip, the designed single-to-differential conversion network with a balancing capacitor, as well as the symmetric inductor having a center-tap to V_DD, achieves relatively reasonable PSRR in the inter-stage. This is important because blocks like power amplifiers are fragile to external interference [10]. Moreover, it is difficult to improve the PSRR for an RF regime with low dropout regulators (LDO).

The output stage is configured as a differential, common-source amplifier to enhance the power gain; it can achieve better common-mode rejection from the supply, which is represented by the PSRR. The differential stage suffers from common-mode interference if its differential pair becomes asymmetric, and has a finite tail current source impedance [9]. A 1:1 transformer is used to achieve output impedance matching in the second stage. The transformer operating as a balun converts the differential signal to a single-ended one at the output. The parallel capacitors C_T1 and C_T2 are optimized to minimize the loss between the primary and secondary inductors. The values of L_T2P, L_T2S, C_T1, and C_T2 in Figure 1 are 1.01 nH, 1.16 nH, 810 fF, and 300 fF, respectively. The resistance of L_T2P is 3.9 Ω (Q_T2P = 7.5), and that of L_T2S is 4.25 Ω (Q_T2S = 7.9). When designing the output 1:1 transformer-based balun, power contours and mismatch circles are used with the load-pull method in Cadence SpectreRF to achieve optimal power matching at the output. The output transformer is implemented based on the extracted output impedance for optimal power matching [11,12].

3. Measurement Results

Figure 4 shows a photograph of the implemented power amplifier with a chip size of 0.65 mm² and without pads, while Figure 5 shows the measurement and probing setup of the proposed PA. The S-parameter measurements were performed with Keysight N5224A PNA. V_BIAS11 and V_BIAS2 were set to 0.95 V. The total DC current consumption was 72 mA under a 1.8 V voltage supply, which made the total DC power consumption 130 mW. Both the measured and simulated S-parameters are shown in Figure 6. There was a frequency shift of 0.2 GHz, which equates to roughly 4.5% error in the center frequency. The maximum value of S21 was 15.5 dB at 4.6 GHz. The 3 dB bandwidth of the implemented PA was 1 GHz (from 4.1 GHz to 5.1 GHz).

The output-referred 1 dB compression point (OP1dB) and the PAE were measured with an Agilent E4405B spectrum analyzer and an Agilent 83623B signal generator. The results show that the OP1dB was 13 dBm, P_SAT was 15.4 dBm, and the peak PAE was 15% when the input power was −1.5 dBm, as depicted in Figure 7. Figure 8 presents the measured output signal of the proposed PA when intermodulation was performed with a 5 MHz frequency offset, while Figure 9 shows the measured third-order intercept point (IP3) of the implemented PA (the simulated input-referred IP3 (IIP3) was 8 dBm); the measured output-referred IP3 (OIP3) was 24.5 dBm, while the measured IIP3 was 6.5 dBm and the measured OIP3 was 22 dBm.

Figure 10 illustrates the measurement setup for the PSRR presented in Figure 3 [13]. A reference AC signal and 1.8 V supply voltage are simultaneously applied to the VDD pad through the bias tee (Picosecond 5550B) and ground-signal-ground (GSG) probe tip. The measured PSRR of the proposed PA at 50 MHz~800 MHz is around 58.6~52.4 dB, which demonstrates the substantial improvement in the PSRR of the proposed PA for the RF regime.

Table 1. Comparison of the power amplifiers.

PA	This Work	[3]	[6]	[10]	[14]	[15]	[16]	[17]	[18]
Technology [nm]	180	55	180	350	180	180	180	180	180
Frequency [GHz]	4.1–5.1	2.4	2.4	10.6 MHz	2.4	5.8	5	5	2.5
Supply Voltage [V]	1.8	3.3	1.8	3	1.8	1.8	1.8	1.8	1
PSAT [dBm]	15.4	29	15	-	5	26.7	17.4	24.1	10.1
PAE(1) [%]	15	-	-	-	20	19	27.1	13	34.5
OP1dB [dBm]	13	27.5	-	-	4	24.2	15.4	21.8	8
OIP3(2) [dBm]	22	-15	-	-	15	-	25	-	-
PSRR [dB at 10 MHz]	82.5	-	25	30	-	-	-	-	-
Area [mm2]	0.65	6.6	1.96	-	0.8	1.92	.84	1.8	-
FoM* [(dBm∙GHz2)/mm2]	45	-	-	-	21.6	-	51.5	-	-

(1) $PAE=\frac{P_{RFout}-P_{RFin}}{P_{diss}}\times 100\%$, (2) $OIP3=IIP{3}_{(3)}+Gain$, (3) $IIP3=P_{RFout}+\frac{IMD}{2}-Gain$

summarizes the comparison of our work with previously published PAs; the figure of merit (FoM) is given by

$$FoM=\frac{P_{RFout}\times \mathrm{PAE}\times \mathrm{OIP}3\times f^2}{Area}$$

(5)

where f is the center frequency, P_Rfout is the output power and Area is the chip occupation size. The FoM of the proposed design is 45 (dBm∙GHz²)/mm², which demonstrates a comparable PA performance while providing a substantially improved PSRR at the frequencies used for various wireless communications.

4. Conclusions

A compact, 5 GHz power amplifier (PA) was implemented with a transformer-based balun in an 180 nm CMOS process. With the proposed single-ended PA having an internally operating, in-balanced configuration, we could achieve a compact PA with a dramatically improved PSRR in the RF regime, for a combo-chip integrated with multiple wireless transceivers. The implemented PA achieved a PAE of 15% and a P_SAT of 15.4 dBm. The proposed PA could be applicable to combo-chips, when considering the dramatically reduced common-mode interference with a comparable RF performance, as well as its compact size. The chip consumes 130 mW under a supply voltage of 1.8 V, with a chip occupancy of 0.65 mm².