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14 pages, 3227 KiB

Open AccessEditor’s ChoiceArticle

Device and Circuit Exploration of Multi-Nanosheet Transistor for Sub-3 nm Technology Node

by Yoongeun Seon, Jeesoo Chang, Changhyun Yoo and Jongwook Jeon

Electronics 2021, 10(2), 180; https://doi.org/10.3390/electronics10020180 - 15 Jan 2021

Cited by 24 | Viewed by 7772

Abstract

A multi-nanosheet field-effect transistor (mNS-FET) device was developed to maximize gate controllability while making the channel in the form of a sheet. The mNS-FET has superior gate controllability for the stacked channels; consequently, it can significantly reduce the short-channel effect (SCE); however, punch-through [...] Read more.

A multi-nanosheet field-effect transistor (mNS-FET) device was developed to maximize gate controllability while making the channel in the form of a sheet. The mNS-FET has superior gate controllability for the stacked channels; consequently, it can significantly reduce the short-channel effect (SCE); however, punch-through inevitably occurs in the bottom channel portion that is not surrounded by gates, resulting in a large leakage current. Moreover, as the size of the semiconductor device decreases to several nanometers, the influence of the parasitic resistance and parasitic capacitance increases. Therefore, it is essential to apply design–technology co-optimization, which analyzes not only the characteristics from the perspective of the device but also the performance from the circuit perspective. In this study, we used Technology Computer Aided Design (TCAD) simulation to analyze the characteristics of the device and directly fabricated a model that describes the current–voltage and gate capacitance characteristics of the device by using Berkeley short-channel insulated-gate field-effect transistor–common multi-gate (BSIM–CMG) parameters. Through this model, we completed the Simulation Program with Integrated Circuit Emphasis (SPICE) simulation for circuit analysis and analyzed it from the viewpoint of devices and circuits. When comparing the characteristics according to the presence or absence of bottom oxide by conducting the above research method, it was confirmed that subthreshold slope (SS) and drain-induced barrier lowering (DIBL) are improved, and power and performance in circuit characteristics are increased. Full article

(This article belongs to the Special Issue New CMOS Devices and Their Applications)

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6 pages, 2106 KiB

Open AccessArticle

Ferroelectric Polarization Aided Low Voltage Operation of 3D NAND Flash Memories

by Ilsik Ham, Youngseok Jeong, Seung Jae Baik and Myounggon Kang

Electronics 2021, 10(1), 38; https://doi.org/10.3390/electronics10010038 - 29 Dec 2020

Cited by 6 | Viewed by 3776

Abstract

In this paper, we proposed a novel structure enabling the low voltage operation of three-dimensional (3D) NAND flash memory. The proposed structure has a ferroelectric thin film just beneath the control gate, where the inserted ferroelectric material is assumed to have two stable [...] Read more.

In this paper, we proposed a novel structure enabling the low voltage operation of three-dimensional (3D) NAND flash memory. The proposed structure has a ferroelectric thin film just beneath the control gate, where the inserted ferroelectric material is assumed to have two stable polarization states. A voltage for ferroelectric polarization (V_PF) that is lower than the program or erase voltage is used to toggle the polarization state of the ferroelectric thin film, whose impact on the channel potential profile is analyzed to optimize operation voltage reduction. The channel potential of select word line (WL), where the natural local self-boosting (NLSB) effect occurs, increases due to the polarization state. Model parameters for the ferroelectric thin film of 8 nm are fixed to 15 µC/cm² for remanent polarization (P_r), 30 µC/cm² for saturation polarization (P_s), and 2 MV/cm for coercive field (E_c). Within our simulation conditions, a program voltage (V_PGM) reduction from 18 V to 14 V is obtained. Full article

(This article belongs to the Special Issue New CMOS Devices and Their Applications)

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12 pages, 3741 KiB

Open AccessArticle

A Novel Structure and Operation Scheme of Vertical Channel NAND Flash with Ferroelectric Memory for Multi String Operations

by Seonjun Choi, Changhwan Choi, Jae Kyeong Jeong, Myounggon Kang and Yun-heub Song

Electronics 2021, 10(1), 32; https://doi.org/10.3390/electronics10010032 - 28 Dec 2020

Cited by 3 | Viewed by 4461

Abstract

In this study, the operation method of the proposed ferroelectric memory structure as a method to overcome the limitations of the existing Charge Trap Flash (CTF) memory Vertical NAND (V-NAND) structure was presented and verified through device simulation. The proposed structure and operation [...] Read more.

In this study, the operation method of the proposed ferroelectric memory structure as a method to overcome the limitations of the existing Charge Trap Flash (CTF) memory Vertical NAND (V-NAND) structure was presented and verified through device simulation. The proposed structure and operation method applied the BiCS (Bit Cost Scalable) structure GIDL (Gate Induce Drain Leakage) deletion method to confirm that selective program operation is possible in the ferroelectric memory V-NAND (Vertical Channel NAND) structure. In particular, we confirmed that the proposed method can easily suppress the program operation by adjusting the hole density of the channel even in the “Y-mode” operation. The channel hole density adjustment that makes this possible can be easily controlled by the voltage difference between the bit line (BL) and drain select line (DSL) contacts. The proposed structure was verified through a device simulation, and as a result of the verification, it was confirmed that the channel hole can be selectively charged in the program operation. Through this, when the cell to be programmed shows the program operation of 2.3 V, the other cells do not. It was confirmed that it could be suppressed to 0.4 V. Full article

(This article belongs to the Special Issue New CMOS Devices and Their Applications)

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12 pages, 5106 KiB

Open AccessArticle

One-Transistor Dynamic Random-Access Memory Based on Gate-All-Around Junction-Less Field-Effect Transistor with a Si/SiGe Heterostructure

by Young Jun Yoon, Jae Sang Lee, Dong-Seok Kim, Sang Ho Lee and In Man Kang

Electronics 2020, 9(12), 2134; https://doi.org/10.3390/electronics9122134 - 13 Dec 2020

Cited by 12 | Viewed by 3914

Abstract

This paper presents a one-transistor dynamic random-access memory (1T-DRAM) cell based on a gate-all-around junction-less field-effect transistor (GAA-JLFET) with a Si/SiGe heterostructure for high-density memory applications. The proposed 1T-DRAM achieves the sensing margin using the difference in hole density in the body region [...] Read more.

This paper presents a one-transistor dynamic random-access memory (1T-DRAM) cell based on a gate-all-around junction-less field-effect transistor (GAA-JLFET) with a Si/SiGe heterostructure for high-density memory applications. The proposed 1T-DRAM achieves the sensing margin using the difference in hole density in the body region between ‘1’ and ‘0’ states. The Si/SiGe heterostructure forms a quantum well in the body and reduces the band-to-band tunneling (BTBT) barrier between the body and drain. Compared with the performances of the 1T-DRAM with Si homo-structure, the proposed 1T-DRAM improves the sensing margin and retention time because its storage ability is enhanced by the quantum well. In addition, the thin BTBT barrier reduced the bias condition for the program operation. The proposed 1T-DRAM showed a high potential for memory applications by obtaining a high read current ratio at ‘1’ and ‘0’ states about 10⁸ and a long retention time above 10 ms. Full article

(This article belongs to the Special Issue New CMOS Devices and Their Applications)

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9 pages, 13333 KiB

Open AccessArticle

A New Read Scheme for Alleviating Cell-to-Cell Interference in Scaled-Down 3D NAND Flash Memory

by Jae-Min Sim, Myounggon Kang and Yun-Heub Song

Electronics 2020, 9(11), 1775; https://doi.org/10.3390/electronics9111775 - 26 Oct 2020

Cited by 12 | Viewed by 4792

Abstract

In this paper, we investigated the cell-to-cell interference in scaled-down 3D NAND flash memory by using a Technology Computer-Aided Design (TCAD) simulation. The fundamental cause of cell-to-cell interference is that the electric field crowding point is changed by the programmed adjacent cell so [...] Read more.

In this paper, we investigated the cell-to-cell interference in scaled-down 3D NAND flash memory by using a Technology Computer-Aided Design (TCAD) simulation. The fundamental cause of cell-to-cell interference is that the electric field crowding point is changed by the programmed adjacent cell so that the electric field is not sufficiently directed to the channel surface. Therefore, the channel concentration of the selected cell is changed, leading to a V_th shift. Furthermore, this phenomenon occurs more severely when the selected cell is in an erased state rather than in a programmed state. In addition, it was confirmed that the cell-to-cell interference by the programmed WL_n+1 is more severe than that of WL_n−1 due to the degradation of the effective mobility effect. To solve this fundamental problem, a new read scheme is proposed. Through TCAD simulation, the cell-to-cell interference was alleviated with a bias having a ΔV of 1.5 V from V_read through an optimization process to have appropriate bias conditions in three ways that are suitable for each pattern. As a result, this scheme narrowed the V_th shift of 67.5% for erased cells and narrowed the V_th shift of 70% for programmed cells. The proposed scheme is one way to solve the cell-to-cell interference that may occur as the cell-to-cell distance decreases for a high stacked 3D NAND structure. Full article

(This article belongs to the Special Issue New CMOS Devices and Their Applications)

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10 pages, 1641 KiB

Open AccessArticle

Hybrid Non-Volatile Flip-Flops Using Spin-Orbit-Torque (SOT) Magnetic Tunnel Junction Devices for High Integration and Low Energy Power-Gating Applications

by Jaeyoung Park

Electronics 2020, 9(9), 1406; https://doi.org/10.3390/electronics9091406 - 1 Sep 2020

Cited by 1 | Viewed by 2922

Abstract

This paper presents two novel hybrid non-volatile flip-flops (NVFFs) comprised of the conventional CMOS flip-flop for static storage in normal operations and Spin-Orbit-Torque Magnetic Tunnel Junction (SOT-MTJ) devices for temporary storage during power gating. The proposed NVFFs re-utilize a part of the standard [...] Read more.

This paper presents two novel hybrid non-volatile flip-flops (NVFFs) comprised of the conventional CMOS flip-flop for static storage in normal operations and Spin-Orbit-Torque Magnetic Tunnel Junction (SOT-MTJ) devices for temporary storage during power gating. The proposed NVFFs re-utilize a part of the standard CMOS flip-flop infrastructure for storing and restoring data onto MTJs for reducing the area. Furthermore, the proposed NVFFs re-use a write current, which is used for storing an MTJ, to write the other MTJ at a time, resulting in 50% storing energy reduction. To reduce the area further, the number of external terminals of an MTJ is reduced by shorting the shorting physical terminals. Removing a terminal using the proposed STT-Like SOT configuration results in fewer transistors to control. The proposed NVFF circuits are evaluated using a compact MTJ model targeting implementation in a 14-nm technology node. Analysis indicates that area overheads are only 10.3% and 6.9% compared to the conventional D flip-flop because three or two minimum-sized NMOS transistors are added for accessing MTJs. Compared to the best previously known NVFFs, the proposed NVFF has an improvement by a factor of 2–8 in terms of the area overhead. Full article

(This article belongs to the Special Issue New CMOS Devices and Their Applications)

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14 pages, 1695 KiB

Open AccessFeature PaperArticle

Fast Characterization of Input-Output Behavior of Non-Charge-Based Logic Devices by Machine Learning

by Arun Kaintura, Kyle Foss, Odysseas Zografos, Ivo Couckuyt, Adrien Vaysset, Tom Dhaene and Bart Sorée

Electronics 2020, 9(9), 1381; https://doi.org/10.3390/electronics9091381 - 26 Aug 2020

Viewed by 2219

Abstract

Non-charge-based logic devices are promising candidates for the replacement of conventional complementary metal-oxide semiconductors (CMOS) devices. These devices utilize magnetic properties to store or process information making them power efficient. Traditionally, to fully characterize the input-output behavior of these devices a large number [...] Read more.

Non-charge-based logic devices are promising candidates for the replacement of conventional complementary metal-oxide semiconductors (CMOS) devices. These devices utilize magnetic properties to store or process information making them power efficient. Traditionally, to fully characterize the input-output behavior of these devices a large number of micromagnetic simulations are required, which makes the process computationally expensive. Machine learning techniques have been shown to dramatically decrease the computational requirements of many complex problems. We use state-of-the-art data-efficient machine learning techniques to expedite the characterization of their behavior. Several intelligent sampling strategies are combined with machine learning (binary and multi-class) classification models. These techniques are applied to a magnetic logic device that utilizes direct exchange interaction between two distinct regions containing a bistable canted magnetization configuration. Three classifiers were developed with various adaptive sampling techniques in order to capture the input-output behavior of this device. By adopting an adaptive sampling strategy, it is shown that prediction accuracy can approach that of full grid sampling while using only a small training set of micromagnetic simulations. Comparing model predictions to a grid-based approach on two separate cases, the best performing machine learning model accurately predicts 99.92% of the dense test grid while utilizing only 2.36% of the training data respectively. Full article

(This article belongs to the Special Issue New CMOS Devices and Their Applications)

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8 pages, 2396 KiB

Open AccessArticle

A 2.4 GHz 20 W 8-channel RF Source Module with Solid-State Power Amplifiers for Plasma Generators

by Hyosung Nam, Taejoo Sim and Junghyun Kim

Electronics 2020, 9(9), 1378; https://doi.org/10.3390/electronics9091378 - 26 Aug 2020

Cited by 2 | Viewed by 3640

Abstract

This paper presents a novel multi-channel type RF source module with solid-state power amplifiers for plasma generators. The proposed module is consisted of a DC control part, RF source generation part, and power amplification part. A 2-stage power amplifier (PA) is combined with [...] Read more.

This paper presents a novel multi-channel type RF source module with solid-state power amplifiers for plasma generators. The proposed module is consisted of a DC control part, RF source generation part, and power amplification part. A 2-stage power amplifier (PA) is combined with a gallium arsenide hetero bipolar transistor (GaAs HBT) as a drive PA and a gallium nitride high electron mobility transistor (GaN HEMT) as a main PA, respectively. By employing 8 channels, the proposed module secures better area coverage on the wafer during semiconductor processes such as chemical vapor deposition (CVD), etching and so on. Additionally, each channel can be maintained at a constant output power because they have a gain factor tunable by a variable gain amplifier (VGA). For that reason, it is possible to have uniform plasma density on the wafer. The operating sequence is controllable by an external DC control port. Moreover, copper–tungsten (CuW) heat spreaders were applied to prevent RF performance degradation from heat generated by the high power amplifier (HPA), and a water jacket was implemented at the bottom of the power amplification part for liquid cooling. Drawing upon the measurement results, the output power at each channel was over 43 dBm (20 W) and the drain efficiency was more than 50% at 2.4 GHz. Full article

(This article belongs to the Special Issue New CMOS Devices and Their Applications)

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8 pages, 2125 KiB

Open AccessArticle

RETRACTED: Achievement of Gradual Conductance Characteristics Based on Interfacial Phase-Change Memory for Artificial Synapse Applications

by Shinyoung Kang, Juyoung Lee, Myounggon Kang and Yunheub Song

Electronics 2020, 9(8), 1268; https://doi.org/10.3390/electronics9081268 - 7 Aug 2020

Cited by 9 | Viewed by 3861 | Retraction

Abstract

In this paper, gradual and symmetrical long-term potentiation (LTP) and long-term depression (LTD) were achieved by applying the optimal electrical pulse condition of the interfacial phase-change memory (iPCM) based on a superlattice (SL) structure fabricated by stacking GeTe/Sb₂Te₃ alternately to [...] Read more.

In this paper, gradual and symmetrical long-term potentiation (LTP) and long-term depression (LTD) were achieved by applying the optimal electrical pulse condition of the interfacial phase-change memory (iPCM) based on a superlattice (SL) structure fabricated by stacking GeTe/Sb₂Te₃ alternately to implement an artificial synapse in neuromorphic computing. Furthermore, conventional phase-change random access memory (PCRAM) based on a Ge–Sb–Te (GST) alloy with an identical bottom electrode contact size was fabricated to compare the electrical characteristics. The results showed a reduction in the reset energy consumption of the GeTe/Sb₂Te₃ (GT/ST) iPCM by more than 69% of the GST alloy for each bottom electrode contact size. Additionally, the GT/ST iPCM achieved gradual conductance tuning and 90.6% symmetry between LTP and LTD with a relatively unsophisticated pulse scheme. Based on the above results, GT/ST iPCM is anticipated to be exploitable as a synaptic device used for brain-inspired computing and to be utilized for next-generation non-volatile memory. Full article

(This article belongs to the Special Issue New CMOS Devices and Their Applications)

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11 pages, 3100 KiB

Open AccessEditor’s ChoiceArticle

Optimization Considerations for Short Channel Poly-Si 1T-DRAM

by Songyi Yoo, Woo-Kyung Sun and Hyungsoon Shin

Electronics 2020, 9(6), 1051; https://doi.org/10.3390/electronics9061051 - 25 Jun 2020

Cited by 2 | Viewed by 4255

Abstract

Capacitorless one-transistor dynamic random-access memory cells that use a polysilicon body (poly-Si 1T-DRAM) have been studied to overcome the scaling issues of conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM). Generally, when the gate length of a silicon-on-insulator (SOI) structure metal-oxide-silicon field-effect transistor [...] Read more.

Capacitorless one-transistor dynamic random-access memory cells that use a polysilicon body (poly-Si 1T-DRAM) have been studied to overcome the scaling issues of conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM). Generally, when the gate length of a silicon-on-insulator (SOI) structure metal-oxide-silicon field-effect transistor (MOSFET) is reduced, its body thickness is reduced in order to suppress the short-channel effects (SCEs). TCAD device simulations were used to investigate the transient performance differences between thin and thick-body poly-Si DRAMs to determine whether reduced body thickness is also appropriate for those devices. Analysis of the simulation results revealed that operating bias conditions are as important as body thickness in 1T-DRAM operation. Since a thick-body device has more trapped hole charge in its grain boundary (GB) than a thin-body device in both the “0” and “1” states, the transient performance of a thick-body device is better than a thin-body device regardless of the Write”1” drain voltage. We also determined that the SCEs in the memory cells can be improved by lowering the Write”1” drain voltage. We conclude that an optimization method for the body thickness and voltage conditions that considers both the cell’s SCEs and its transient performance is necessary for its development and application. Full article

(This article belongs to the Special Issue New CMOS Devices and Their Applications)

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12 pages, 1595 KiB

Open AccessArticle

Analytical Drain Current Model for a-SiGe:H Thin Film Transistors Considering Density of States

by Silvestre Salas-Rodríguez, Francisco López-Huerta, Agustín L. Herrera-May, Joel Molina-Reyes and Jaime Martínez-Castillo

Electronics 2020, 9(6), 1016; https://doi.org/10.3390/electronics9061016 - 18 Jun 2020

Cited by 2 | Viewed by 2776

Abstract

Thin film transistors (TFTs) fabricated on flexible and large area substrates have been studied with great interest due to their future applications. Recent studies have developed new semiconductors such as a-SiGe:H for fabrication of high performance TFTs. These films have important advantages, including [...] Read more.

Thin film transistors (TFTs) fabricated on flexible and large area substrates have been studied with great interest due to their future applications. Recent studies have developed new semiconductors such as a-SiGe:H for fabrication of high performance TFTs. These films have important advantages, including deposition at low temperatures and low pressures, and higher carrier mobilities. Due to these advantages, the a-SiGe:H films can be used in the fabrication of TFTs. In this work, we present an analytical drain current model for a-SiGe:H TFTs considering density of states and free charges, which describes the current behavior at sub-and above- threshold region. In addition, 2D numerical simulations of a-SiGe:H TFTs are developed. The results of the analytical drain current model agree well with those of the 2D numerical simulations. For all characteristics of the drain current curves, the average absolute error of the analytical model is close to 5.3%. This analytical drain current model can be useful to estimate the performance of a-SiGe:H TFTs for applications in large area electronics. Full article

(This article belongs to the Special Issue New CMOS Devices and Their Applications)

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7 pages, 2017 KiB

Open AccessFeature PaperArticle

Investigation of Inhibited Channel Potential of 3D NAND Flash Memory According to Word-Line Location

by Sangwoo Han, Youngseok Jeong, Heesauk Jhon and Myounggon Kang

Electronics 2020, 9(2), 268; https://doi.org/10.3390/electronics9020268 - 5 Feb 2020

Cited by 8 | Viewed by 5296

Abstract

Natural local self-boosting (NLSB) was analyzed according to the location of a selected word-line (WL) where potential boosting occurs. When the same pattern occurred, it was found that the top cells (WL11 through WL15) and bottom cells (WL0 through WL4) have identically symmetrical [...] Read more.

Natural local self-boosting (NLSB) was analyzed according to the location of a selected word-line (WL) where potential boosting occurs. When the same pattern occurred, it was found that the top cells (WL11 through WL15) and bottom cells (WL0 through WL4) have identically symmetrical potential boosting. In addition, in the region of the middle cells (WL6 through WL10), a slight change in the potential boosting was also almost the same. In the 3D NAND, where there was a dummy WL (DWL), the NLSB for the edge WL changed as the pattern of the DWL changed. The DWL did not affect the NLSB of the main cell, regardless of the pattern. Therefore, the high potential of the edge WL could reduce the potential difference between the main cell and the edge WL using the DWL. Full article

(This article belongs to the Special Issue New CMOS Devices and Their Applications)

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9 pages, 5032 KiB

Open AccessArticle

A Programmable Impedance Tuner with a High Resolution Using a 0.18-um CMOS SOI Process for Improved Linearity

by Younghwan Bae, Heesauk Jhon and Junghyun Kim

Electronics 2020, 9(1), 7; https://doi.org/10.3390/electronics9010007 - 19 Dec 2019

Cited by 3 | Viewed by 3950

Abstract

In this paper, a novel coupler/reflection-type programmable electronic impedance tuner combined with switches that were fabricated by a 0.18-um complementary metal–oxide–semiconductor (CMOS) silicon-on-insulator (SOI) process is proposed for replacement of the conventional mechanical tuner in power amplifier (PA) load-pull test. By employing the [...] Read more.

In this paper, a novel coupler/reflection-type programmable electronic impedance tuner combined with switches that were fabricated by a 0.18-um complementary metal–oxide–semiconductor (CMOS) silicon-on-insulator (SOI) process is proposed for replacement of the conventional mechanical tuner in power amplifier (PA) load-pull test. By employing the multi-stacked field-effect transistors (FETs) as a single-branch switch, the proposed tuner has the advantage of precise impedance variation with systematic and magnitude and phase adjustment. Additionally, it led to high standing wave ratio (SWR) coverage and a good impedance resolution with a high power handling capability. Furthermore, the double-branch based on multi-stacked FET was applied to switches for additional enhancement of the intermodulation distortion (IMD) performance through the mitigated drain-source voltage of the single-FET. Drawing upon the measurement results, we demonstrated that SWR changed from 2 to 6 sequentially with a 12–15° phase angle step over a mid/high-band range of a 1.5–2.1 GHz band for 3G/4G handset application. In addition, the PA load-pull measurement results obtained using the proposed tuners verified their practicality and competitive performance with mechanical tuners. Finally, the measured linearity using the double-branch switch demonstrated the good IMD3 performance of −78 dBc, and this result is noteworthy when compared with conventional electronic impedance tuners. Full article

(This article belongs to the Special Issue New CMOS Devices and Their Applications)

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7 pages, 3259 KiB

Open AccessArticle

Cost-Effective 4 GHz VCO Using Only Miniature Spirals Realized in a 0.18 μm CMOS Process for Wireless Sensor Network (WSN) Applications

by Heesauk Jhon, Min-Su Kim and Myounggon Kang

Electronics 2019, 8(11), 1369; https://doi.org/10.3390/electronics8111369 - 19 Nov 2019

Cited by 4 | Viewed by 3303

Abstract

This paper presents an extremely cost-effective radio-frequency integrated circuit (RFIC) implementation technique by employing a digital logic CMOS process and reducing area occupation for voltage-controlled oscillators (VCOs) using all miniature inductors for wireless sensor network (WSN) applications. The designed VCO operates in the [...] Read more.

This paper presents an extremely cost-effective radio-frequency integrated circuit (RFIC) implementation technique by employing a digital logic CMOS process and reducing area occupation for voltage-controlled oscillators (VCOs) using all miniature inductors for wireless sensor network (WSN) applications. The designed VCO operates in the 4.0 GHz band with a power consumption of 1.4 mW and a phase noise of −113.6 dBc/Hz at 1 MHz, occupying a Si area of 0.283 × 0.682 mm². In addition, we confirmed that the figure of merit (FOM) of 183.8 in our design is competitive with that of other LC-VCOs that were fabricated using the RF option and designed with conventional inductors. Full article

(This article belongs to the Special Issue New CMOS Devices and Their Applications)

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11 pages, 5084 KiB

Open AccessFeature PaperArticle

A Ruggedness Improved Mobile Radio Frequency Power Amplifier Module with Dynamic Impedance Correction by Software Defined Atomization

by Jooyoung Jeon and Myounggon Kang

Electronics 2019, 8(11), 1317; https://doi.org/10.3390/electronics8111317 - 8 Nov 2019

Cited by 1 | Viewed by 4711

Abstract

A ruggedness improved multi-band radio frequency (RF) power amplifier (PA) module applicable to mobile handsets, which are required to survive against a serious load impedance change under extreme power and bias conditions, is presented. In this method, the load impedance of PA is [...] Read more.

A ruggedness improved multi-band radio frequency (RF) power amplifier (PA) module applicable to mobile handsets, which are required to survive against a serious load impedance change under extreme power and bias conditions, is presented. In this method, the load impedance of PA is adaptively adjusted with a digitally controlled impedance corrector to keep the PA safe by performing a load mismatch detection. The impedance mismatch detector, impedance corrector, and other RF switches were all integrated into a single integrated circuit (IC) using silicon on insulator (SOI) complementary metal oxide semiconductor (CMOS). For the verification purpose, a 2-stage hetero junction bipolar transistor (HBT) PA module adopting this method was fabricated. At a frequency of 1915 MHz, a collector bias voltage of 4.2 V, and over a wider range of load impedance variation between a VSWR of 1 and a VSWR of 5.5, it did not fail. When this technique was not applied with a voltage standing wave ratio (VSWR) range of 1 to 4, it resulted in an acceptable RF performance degradation of 1% power added efficiency (PAE) in envelope tracking (ET) mode. Moreover, it survived at a bias voltage 1V larger than when the technique was not applied for the same mismatch condition. Full article

(This article belongs to the Special Issue New CMOS Devices and Their Applications)

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10 pages, 4326 KiB

Open AccessArticle

Software-Based Adaptive Protection Control against Load Mismatch for a Mobile Power Amplifier Module

by Jooyoung Jeon, Youngho Jung and Myounggon Kang

Electronics 2019, 8(11), 1226; https://doi.org/10.3390/electronics8111226 - 27 Oct 2019

Viewed by 3237

Abstract

A closed-loop protection method for a radio frequency (RF) power amplifier (PA) module applicable to mobile handsets has been introduced. The load impedance of the PA was adaptively sensed by an embedded impedance detector which was digitally controlled and the system adjusted PA [...] Read more.

A closed-loop protection method for a radio frequency (RF) power amplifier (PA) module applicable to mobile handsets has been introduced. The load impedance of the PA was adaptively sensed by an embedded impedance detector which was digitally controlled and the system adjusted PA power using a feedback circuit to keep the PA safe based on a load mismatch detection. For verification, a two-stage hetero junction bipolar transistor (HBT) PA module for handsets was fabricated and tested against load mismatch. Measurement results showed that the technique could help PA survive at a 0.5V larger collector bias voltage condition than when the technique was not applied for the same mismatch condition with an acceptable RF performance degradation at nominal condition. Full article

(This article belongs to the Special Issue New CMOS Devices and Their Applications)

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9 pages, 3492 KiB

Open AccessArticle

Delta-Sigma Modulator with Relaxed Feedback Timing for High Speed Applications

by Youngho Jung and Jooyoung Jeon

Electronics 2019, 8(10), 1138; https://doi.org/10.3390/electronics8101138 - 9 Oct 2019

Viewed by 3405

Abstract

In this paper, a ΔΣ analog-to-digital converter (ADC) was designed and measured for broadband and high-resolution applications by applying the simple circuit technique to alleviate the feedback timing of input feed-forward architecture. With the proposed technique, a low-speed comparator and dynamic element matching [...] Read more.

In this paper, a ΔΣ analog-to-digital converter (ADC) was designed and measured for broadband and high-resolution applications by applying the simple circuit technique to alleviate the feedback timing of input feed-forward architecture. With the proposed technique, a low-speed comparator and dynamic element matching (DEM) logic can be applied even for high-speed implementation, which helps to decrease power dissipation. Two prototypes using slightly different input branch topologies were fabricated with a 0.18 um 2-poly and 4-metal CMOS process, and measured to demonstrate the effectiveness of the proposed circuit technique. The sampling capacitor and feedback DAC capacitors were separated in prototype A, while they were shared in prototype B. The prototypes achieved 81.2 dB and 72.4 dB of SNDR in a 2.1 MHz signal band, respectively. Full article

(This article belongs to the Special Issue New CMOS Devices and Their Applications)

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6 pages, 2866 KiB

Open AccessArticle

Investigation on Temperature Dependency of Recessed-Channel Reconfigurable Field-Effect Transistor

by Jang Hyun Kim and Sangwan Kim

Electronics 2019, 8(10), 1124; https://doi.org/10.3390/electronics8101124 - 6 Oct 2019

Cited by 1 | Viewed by 3095

Abstract

Current-voltage (I-V) characteristics of a recessed-channel reconfigurable field-effect transistor (RC-RFET) is discussed, herein, depending on the variation of temperature (T) to understand the operation mechanisms, in depth. Assuming that RC-RFET can be simply modeled as a channel resistance ( [...] Read more.

Current-voltage (I-V) characteristics of a recessed-channel reconfigurable field-effect transistor (RC-RFET) is discussed, herein, depending on the variation of temperature (T) to understand the operation mechanisms, in depth. Assuming that RC-RFET can be simply modeled as a channel resistance (R_CH) and a Schottky contact resistance (R_SC) connected in series, the validity has been examined by a technology computer-aided design (TCAD) simulation with different Schottky barrier heights (SBHs) and carrier mobilities (μ). As a result, it was clearly determined that the drain current (I_D) of RC-RFET is dominated by the bigger component, since R_CH and R_SC have an opposite correlation with T. Full article

(This article belongs to the Special Issue New CMOS Devices and Their Applications)

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11 pages, 1604 KiB

Open AccessArticle

Analytical Current-Voltage Model for Gate-All-Around Transistor with Poly-Crystalline Silicon Channel

by Yoongeun Seon, Jongmin Kim, Soowon Kim and Jongwook Jeon

Electronics 2019, 8(9), 988; https://doi.org/10.3390/electronics8090988 - 4 Sep 2019

Cited by 4 | Viewed by 3899

Abstract

Poly-crystalline silicon channel transistors have been used as a display TFT for a long time and have recently been used in a 3D vertical NAND Flash which is a transistor with 2D plane NAND upright. In addition, multi-gate transistors such as FinFETs and [...] Read more.

Poly-crystalline silicon channel transistors have been used as a display TFT for a long time and have recently been used in a 3D vertical NAND Flash which is a transistor with 2D plane NAND upright. In addition, multi-gate transistors such as FinFETs and a gate-all-around (GAA) structure has been used to suppress the short-channel effects for logic/analog and memory applications. Compact models for poly-crystalline silicon (poly-silicon) channel planar TFTs and single crystalline silicon channel GAA MOSFETs have been developed separately, however, there are few models consider these two physics at the same time. In this work, we derived new analytical current-voltage model for GAA transistor with poly-silicon channel by considering the cylindrical coordinates and the grain boundary effect. Based on the derived formula, the compact I-V model for various operating regions and threshold voltage was proposed for the first time. The proposed model was compared with the measured data and good agreements were observed. Full article

(This article belongs to the Special Issue New CMOS Devices and Their Applications)

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8 pages, 2592 KiB

Open AccessArticle

Development of an Advanced TDDB Analysis Model for Temperature Dependency

by Kiron Park, Keonho Park, Sujin Im, SeungEui Hong, Kwonjoo Son and Jongwook Jeon

Electronics 2019, 8(9), 942; https://doi.org/10.3390/electronics8090942 - 27 Aug 2019

Cited by 5 | Viewed by 9314

Abstract

This paper proposes a hybrid model to describe the temperature dependence of the time-dependent dielectric breakdown (TDDB) phenomenon. TDDB can be expressed in terms of two well-known representative degradation mechanisms: The thermo-chemical (TC) mechanism and the anode hole injection (AHI) mechanism. A single [...] Read more.

This paper proposes a hybrid model to describe the temperature dependence of the time-dependent dielectric breakdown (TDDB) phenomenon. TDDB can be expressed in terms of two well-known representative degradation mechanisms: The thermo-chemical (TC) mechanism and the anode hole injection (AHI) mechanism. A single model does not account for the measured lifetime, due to TDDB under different temperature conditions. Hence, in the proposed model, two different degradation mechanisms are considered simultaneously in an appropriate manner to describe the trap generation in the dielectric layer. The proposed model can be used to simulate the generation of the percolation path in a dielectric layer, and it is in agreement with the measured lifetime because of TDDB at different temperatures. Therefore, the proposed model can be used to predict guarantee time or initial failure detection, using the accelerated life test for industrial purposes. Full article

(This article belongs to the Special Issue New CMOS Devices and Their Applications)

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Review

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16 pages, 1723 KiB

Open AccessReview

Neuromorphic Computing Using Emerging Synaptic Devices: A Retrospective Summary and an Outlook

by Jaeyoung Park

Electronics 2020, 9(9), 1414; https://doi.org/10.3390/electronics9091414 - 1 Sep 2020

Cited by 41 | Viewed by 6950

Abstract

In this paper, emerging memory devices are investigated for a promising synaptic device of neuromorphic computing. Because the neuromorphic computing hardware requires high memory density, fast speed, and low power as well as a unique characteristic that simulates the function of learning by [...] Read more.

In this paper, emerging memory devices are investigated for a promising synaptic device of neuromorphic computing. Because the neuromorphic computing hardware requires high memory density, fast speed, and low power as well as a unique characteristic that simulates the function of learning by imitating the process of the human brain, memristor devices are considered as a promising candidate because of their desirable characteristic. Among them, Phase-change RAM (PRAM) Resistive RAM (ReRAM), Magnetic RAM (MRAM), and Atomic Switch Network (ASN) are selected to review. Even if the memristor devices show such characteristics, the inherent error by their physical properties needs to be resolved. This paper suggests adopting an approximate computing approach to deal with the error without degrading the advantages of emerging memory devices. Full article

(This article belongs to the Special Issue New CMOS Devices and Their Applications)

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Other

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1 pages, 429 KiB

Open AccessRetraction

RETRACTED: Kang et al. Achievement of Gradual Conductance Characteristics Based on Interfacial Phase-Change Memory for Artificial Synapse Applications. Electronics 2020, 9, 1268

by Shinyoung Kang, Juyoung Lee, Myounggon Kang and Yunheub Song

Electronics 2021, 10(4), 408; https://doi.org/10.3390/electronics10040408 - 8 Feb 2021

Cited by 1 | Viewed by 1974

Abstract

The authors and journal retract the article, “Achievement of Gradual Conductance Characteristics Based on Interfacial Phase-Change Memory for Artificial Synapse Applications” [...] Full article

(This article belongs to the Special Issue New CMOS Devices and Their Applications)

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