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A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Computer Science & Engineering".

Deadline for manuscript submissions: closed (30 April 2023) | Viewed by 30133

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Special Issue Editors

Dr. Andres Upegui

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Guest Editor

inIT, Hepia, University of Applied Sciences of Western Switzerland, 1202 Geneva, Switzerland
Interests: reconfigurable computing; self-adaptive hardware; neuromorphic architectures
Special Issues, Collections and Topics in MDPI journals

Prof. Dr. Andrea Guerrieri

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Guest Editor

School of Engineering, HES-SO Valais-Wallis, 1950 Sion, Switzerland
Interests: reconfigurable computing; electronic design automation; software-defined hardware
Special Issues, Collections and Topics in MDPI journals

Dr. Laurent Gantel

E-Mail Website
Guest Editor

inIT, Hepia, University of Applied Sciences of Western Switzerland, 1202 Geneva, Switzerland
Interests: FPGAs; dynamic reconfiguration; heterogeneous computing

Special Issue Information

Dear Colleagues,

Field-programmable gate array (FPGA) technology represents a potential alternative to classical CPUs in the post-Moore era from edge computing to data centers. FPGAs offer performance improvements when compared with traditional processing architectures due to their spatial computation capability and energy efficiency.

In recent years, FPGA technologies have evolved in the form of tools, design methodologies, and FPGA architectural features. These technologies have enabled or boosted novel application domains. This Special Issue aims to present these application domains and how recent advances in FPGA technologies have made it possible. Topics of interest include but are not limited to:

Application of models, methods, tools, and architectures for reconfigurable computing;
Applied self-adapting or evolvable systems;
Compilation, simulation, debugging, synthesis, verification, and test of reconfigurable systems;
FPGA-based applications including (but not limited to):
- Cryptography;
- Security;
- Astronomy;
- Signal and image processing;
- Communications;
- Biomedical applications;
- Embedded systems;
- Automation;
- Intelligent systems;
- Scientific computing;
- Industrial applications;
- Data compression;
- Robotics;

Dr. Andres Upegui
Dr. Andrea Guerrieri
Dr. Laurent Gantel
Guest Editors

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Keywords

FPGA
reconfigurable computing
hardware acceleration
heterogeneous reconfigurable systems
design automation

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Published Papers (12 papers)

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Editorial

Jump to: Research

4 pages, 176 KiB

Open AccessEditorial

Applications Enabled by FPGA-Based Technology

by Andrea Guerrieri, Andres Upegui and Laurent Gantel

Electronics 2023, 12(15), 3302; https://doi.org/10.3390/electronics12153302 - 1 Aug 2023

Cited by 1 | Viewed by 1886

Abstract

Field-programmable gate array (FPGA) technology represents a potential alternative to classical CPUs and GPUs in the post-Moore era from edge computing to data centers [...] Full article

(This article belongs to the Special Issue Applications Enabled by FPGA-Based Technology)

Research

Jump to: Editorial

13 pages, 1184 KiB

Open AccessArticle

Improving Seed-Based FPGA Packing with Indirect Connection for Realization of Neural Networks

by Le Yu, Baojin Guo, Tian Zhi and Lida Bai

Electronics 2023, 12(12), 2691; https://doi.org/10.3390/electronics12122691 - 15 Jun 2023

Cited by 1 | Viewed by 1309

Abstract

FPGAs are gaining favor among researchers in fields including artificial intelligence and big data due to their configurability and high level of parallelism. As the packing methods indisputably affect the implementation performance of FPGA chips, packing techniques play an important role in the design automation flow of FPGAs. In this paper, we propose a quantitative rule for packing priority of neural network circuits, and optimize the traditional seed-based packing methods with special primitives. The experiment result indicates that the proposed packing method achieves an average decrease of 8.45% in critical path delay compared to the VTR8.0 on Koios deep learning benchmarks. Full article

(This article belongs to the Special Issue Applications Enabled by FPGA-Based Technology)

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14 pages, 3852 KiB

Open AccessArticle

Accurate Multi-Channel QCM Sensor Measurement Enabled by FPGA-Based Embedded System Using GPS

by Adrien Bourennane, Camel Tanougast, Camille Diou and Jean Gorse

Electronics 2023, 12(12), 2666; https://doi.org/10.3390/electronics12122666 - 14 Jun 2023

Cited by 1 | Viewed by 4036

Abstract

This paper presents a design and implementation proposal for a real-time frequency measurement system for high-precision, multi-channel quartz crystal microbalance (QCM) sensors using a field programmable gate array (FPGA). The key contribution of this work lies in the integration of a frequency measurement and mass resolution computation based on Global Positioning System (GPS) signals within a single FPGA chip, utilizing Input/Output Blocks to incorporate logic QCM oscillator circuits. The FPGA design enables parallel processing, ensuring accurate measurements, faster calculations, and reduced hardware complexity by minimizing the need for external components. As a result, a cost-effective and accurate multi-channel sensor system is developed, serving as a reconfigurable standalone measurement platform with communication capabilities. The system is implemented and tested using the FPGA Xilinx Virtex-6, along with multiple QCM sensors. The implementation on a Xilinx XC6VLX240T FPGA achieves a maximum frequency of 324 MHz and consumes a dynamic power of 120 mW. Notably, the design utilizes a modest number of resources, requiring only 188 slices, 733 flip-flops, and 13 IOBs to perform a double-channel sensor microbalance. The proposed system meets the precision measurement requirements for QCM sensor applications, exhibiting low measurement error when monitoring QCM frequencies ranging from 1 to 50 MHz, with an accuracy of 0.2 ppm and less than 0.1 Hz. Full article

(This article belongs to the Special Issue Applications Enabled by FPGA-Based Technology)

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21 pages, 3063 KiB

Open AccessArticle

Finding the Top-K Heavy Hitters in Data Streams: A Reconfigurable Accelerator Based on an FPGA-Optimized Algorithm

by Ali Ebrahim

Electronics 2023, 12(11), 2376; https://doi.org/10.3390/electronics12112376 - 24 May 2023

Viewed by 1983

Abstract

This paper presents a novel approach for accelerating the top-k heavy hitters query in data streams using Field Programmable Gate Arrays (FPGAs). Current hardware acceleration approaches rely on the direct and strict mapping of software algorithms into hardware, limiting their performance and practicality due to the lack of hardware optimizations at an algorithmic level. The presented approach optimizes a well-known software algorithm by carefully relaxing some of its requirements to allow for the design of a practical and scalable hardware accelerator that outperforms current state-of-the-art accelerators while maintaining near-perfect accuracy. This paper details the design and implementation of an optimized FPGA accelerator specifically tailored for computing the top-k heavy hitters query in data streams. The presented accelerator is entirely specified at the C language level and is easily reproducible with High-Level Synthesis (HLS) tools. Implementation on Intel Arria 10 and Stratix 10 FPGAs using Intel HLS compiler showed promising results—outperforming prior state-of-the-art accelerators in terms of throughput and features. Full article

(This article belongs to the Special Issue Applications Enabled by FPGA-Based Technology)

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18 pages, 4007 KiB

Open AccessArticle

FPGA-Flux Proprietary System for Online Detection of Outer Race Faults in Bearings

by Jonathan Cureño-Osornio, Israel Zamudio-Ramirez, Luis Morales-Velazquez, Arturo Yosimar Jaen-Cuellar, Roque Alfredo Osornio-Rios and Jose Alfonso Antonino-Daviu

Electronics 2023, 12(8), 1924; https://doi.org/10.3390/electronics12081924 - 19 Apr 2023

Cited by 5 | Viewed by 2025

Abstract

Online fault detection in industrial machinery, such as induction motors or their components (e.g., bearings), continues to be a priority. Most commercial equipment provides general measurements and not a diagnosis. On the other hand, commonly, research works that focus on fault detection are tested offline or over processors that do not comply with an online diagnosis. In this sense, the present work proposes a system based on a proprietary field programmable gate array (FPGA) platform with several developed intellectual property cores (IPcores) and tools. The FPGA platform together with a stray magnetic flux sensor are used for the online detection of faults in the outer race of bearings in induction motors. The integrated parts comprising the monitoring system are the stray magnetic flux triaxial sensor, several developed IPcores, an embedded processor for data processing, and a user interface where the diagnosis is visualized. The system performs the fault diagnosis through a statistical analysis as follows: First, a triaxial sensor measures the stray magnetic flux in the motor’s surroundings (this flux will vary as symptoms of the fault). Second, an embedded processor in an FPGA-based proprietary board drives the developed IPcores in calculating the statistical features. Third, a set of ranges is defined for the statistical features values, and it is used to indicate the condition of the bearing in the motor. Therefore, if the value of a statistical feature belongs to a specific range, the system will return a diagnosis of whether a fault is present and, if so, the severity of the damage in the outer race. The results demonstrate that the values of the root mean square (RMS) and kurtosis, extracted from the stray magnetic field from the motor, provide a reliable diagnostic of the analyzed bearing. The results are provided online and displayed for the user through interfaces developed on the FPGA platform, such as in a liquid crystal display or through serial communication by a Bluetooth module. The platform is based on an FPGA XC6SLX45 Spartan 6 of Xilinx, and the architecture of the modules used are described through hardware description language. This system aims to be an online tool that can help users of induction motors in maintenance tasks and for the early detection of faults related to bearings. Full article

(This article belongs to the Special Issue Applications Enabled by FPGA-Based Technology)

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18 pages, 2261 KiB

Open AccessArticle

A New FPGA-Based Task Scheduler for Real-Time Systems

by Lukáš Kohútka and Ján Mach

Electronics 2023, 12(8), 1870; https://doi.org/10.3390/electronics12081870 - 15 Apr 2023

Cited by 3 | Viewed by 2443

Abstract

This research demonstrates a novel design of an FPGA-implemented task scheduler for real-time systems that supports both aperiodic and periodic tasks. The periodic tasks are automatically restarted once their period has expired without any need for software intervention. The proposed scheduler utilizes the Earliest-Deadline First (EDF) algorithm and is optimized for multi-core CPUs, capable of executing up to four threads simultaneously. The scheduler also provides support for task suspension, resumption, and enabling inter-task synchronization. The design is based on priority queues, which play a crucial role in decision making and time management. Thanks to the hardware acceleration of the scheduler and the hardware implementation of priority queues, it operates in only two clock cycles, regardless of the number of tasks in the system. The results of the FPGA synthesis, performed on an Intel FPGA device (Cyclone V family), are presented in the paper. The proposed solution was validated through a simplified version of the Universal Verification Methodology (UVM) with millions of test instructions and random deadline and period values. Full article

(This article belongs to the Special Issue Applications Enabled by FPGA-Based Technology)

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15 pages, 349 KiB

Open AccessArticle

An Instruction-Driven Batch-Based High-Performance Resource-Efficient LSTM Accelerator on FPGA

by Ning Mao, Haigang Yang and Zhihong Huang

Electronics 2023, 12(7), 1731; https://doi.org/10.3390/electronics12071731 - 5 Apr 2023

Cited by 1 | Viewed by 1951

Abstract

In recent years, long short-term memory (LSTM) has been used in many speech recognition tasks, due to its excellent performance. Due to a large amount of calculation and complex data dependencies of LSTM, it is often not so efficient to deploy on the field-programmable gate array (FPGA) platform. This paper proposes an LSTM accelerator, driven by a specific instruction set. The accelerator consists of a matrix multiplication unit and a post-processing unit. The matrix multiplication unit uses staggered timing of read data to reduce register usage. The post-processing unit can complete various calculations with only a small amount of digital signal processing (DSP) slices, through resource sharing, and at the same time, the memory footprint is reduced, through the well-designed data flow design. The accelerator is batch-based and capable of computing data from multiple users simultaneously. Since the calculation process of LSTM is divided into a sequence of instructions, it is feasible to execute multi-layer LSTM networks as well as large-scale LSTM networks. Experimental results show that our accelerator can achieve a performance of 2036 GOPS at 16-bit data precision, while having higher hardware utilization compared to previous work. Full article

(This article belongs to the Special Issue Applications Enabled by FPGA-Based Technology)

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19 pages, 7913 KiB

Open AccessArticle

FPGA Implementation of Shack–Hartmann Wavefront Sensing Using Stream-Based Center of Gravity Method for Centroid Estimation

by Fanpeng Kong, Manuel Cegarra Polo and Andrew Lambert

Electronics 2023, 12(7), 1714; https://doi.org/10.3390/electronics12071714 - 4 Apr 2023

Cited by 2 | Viewed by 2000

Abstract

We present a fast and reconfigurable architecture for Shack–Hartmann wavefront sensing implemented on FPGA devices using a stream-based center of gravity to measure the spot displacements. By calculating the center of gravity around each incoming pixel with an optimal window matching the spot size, the common trade-off between noise and bias errors and dynamic range due to window size existing in conventional center of gravity methods is avoided. In addition, the accuracy of centroid estimation is not compromised when the spot moves to or even crosses the sub-aperture boundary, leading to an increased dynamic range. The calculation of the centroid begins while the pixel values are read from an image sensor and further computation such as slope and partial wavefront reconstruction follows immediately as the sub-aperture centroids are ready. The result is a real-time wavefront sensing system with very low latency and high measurement accuracy feasible for targeting on low-cost FPGA devices. This architecture provides a promising solution which can cope with multiple target objects and work in moderate scintillation. Full article

(This article belongs to the Special Issue Applications Enabled by FPGA-Based Technology)

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14 pages, 4831 KiB

Open AccessArticle

Electromyogram (EMG) Signal Classification Based on Light-Weight Neural Network with FPGAs for Wearable Application

by Hyun-Sik Choi

Electronics 2023, 12(6), 1398; https://doi.org/10.3390/electronics12061398 - 15 Mar 2023

Cited by 6 | Viewed by 2389

Abstract

Recently, the application of bio-signals in the fields of health management, human–computer interaction (HCI), and user authentication has increased. This is because of the development of artificial intelligence technology, which can analyze bio-signals in numerous fields. In the case of the analysis of bio-signals, the results tend to vary depending on the analyst, owing to a large amount of noise. However, when a neural network is used, feature extraction is possible, enabling a more accurate analysis. However, if the bio-signal time series is analyzed as is, the total neural network increases in size. In this study, to accomplish a light-weight neural network, a maximal overlap discrete wavelet transform (MODWT) and a smoothing technique are used for better feature extraction. Moreover, the learning efficiency is increased using an augmentation technique. In designing the neural network, a one-dimensional convolution layer is used to ensure that the neural network is simple and light-weight. Consequently, the light-weight attribute can be achieved, and neural networks can be implemented in edge devices such as the field programmable gate array (FPGA), yielding low power consumption, high security, fast response times, and high user convenience for wearable applications. The electromyogram (EMG) signal represents a typical bio-signal in this study. Full article

(This article belongs to the Special Issue Applications Enabled by FPGA-Based Technology)

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11 pages, 13207 KiB

Open AccessArticle

A Model of Thermally Activated Molecular Transport: Implementation in a Massive FPGA Cluster

by Grzegorz Jabłoński, Piotr Amrozik and Krzysztof Hałagan

Electronics 2023, 12(5), 1198; https://doi.org/10.3390/electronics12051198 - 2 Mar 2023

Cited by 1 | Viewed by 1341

Abstract

In this paper, a massively parallel implementation of Boltzmann’s thermally activated molecular transport model is presented. This models allows taking into account potential energy barriers in molecular simulations and thus modeling thermally activated diffusion processes in liquids. The model is implemented as an extension to the basic Dynamic Lattice Liquid (DLL) algorithm on ARUZ, a massively parallel FPGA-based simulator located at BioNanoPark Lodz. The advantage of this approach is that it does not use any exponentiation operations, minimizing resource usage and allowing one to perform simulations containing up to 4,608,000 nodes. Full article

(This article belongs to the Special Issue Applications Enabled by FPGA-Based Technology)

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16 pages, 1728 KiB

Open AccessArticle

Acceleration of Trading System Back End with FPGAs Using High-Level Synthesis Flow

by Sunil Puranik, Mahesh Barve, Swapnil Rodi and Rajendra Patrikar

Electronics 2023, 12(3), 520; https://doi.org/10.3390/electronics12030520 - 19 Jan 2023

Cited by 1 | Viewed by 4357

Abstract

FPGA technology is widely used in the finance domain. We describe the design of a financial trading system order processing component using FPGAs, implemented with high-level synthesis (HLS) flow. The order processing component is the major contributor to increased delays and low throughput in the current software implementation of trading systems. The objective of FPGA implementation is to reduce the latency of order processing and increase the throughput of trading systems as compared to software implementation. Our design is one of the first attempts to speed up order processing in a trading system using FPGA technology and HLS flow. HLS was used in implementing the design for higher productivity and faster turnaround time. The design shows orders of magnitude of improvement in performance indicating that more complex FPGA systems could be designed using HLS. We obtained more than 2X of an advantage in order processing speed and a reduction in latency with FPGA technology. Moreover, we gained a 4X advantage in terms of productivity using HLS. Full article

(This article belongs to the Special Issue Applications Enabled by FPGA-Based Technology)

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17 pages, 1621 KiB

Open AccessArticle

FPGA-Based High-Throughput Key-Value Store Using Hashing and B-Tree for Securities Trading System

by Sunil Puranik, Mahesh Barve, Swapnil Rodi and Rajendra Patrikar

Electronics 2023, 12(1), 183; https://doi.org/10.3390/electronics12010183 - 30 Dec 2022

Cited by 1 | Viewed by 2333

Abstract

Field-Programmable Array (FPGA) technology is extensively used in Finance. This paper describes a high-throughput key-value store (KVS) for securities trading system applications using an FPGA. The design uses a combination of hashing and B-Tree techniques and supports a large number of keys (40 million) as required by the Trading System. We have used a novel technique of using buckets of different capacities to reduce the amount of Block-RAM (BRAM) and perform a high-speed lookup. The design uses high-bandwidth-memory (HBM), an On-chip memory available in Virtex Ultrascale+ FPGAs to support a large number of keys. Another feature of this design is the replication of the database and lookup logic to increase the overall throughput. By implementing multiple lookup engines in parallel and replicating the database, we could achieve high throughput (up to 6.32 million search operations/second) as specified by our client, which is a major stock exchange. The design has been implemented with a combination of Verilog and high-level-synthesis (HLS) flow to reduce the implementation time. Full article

(This article belongs to the Special Issue Applications Enabled by FPGA-Based Technology)

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