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Electronics
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Nanoscale CMOS Technologies
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Nanoscale CMOS Technologies

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Microelectronics".

Deadline for manuscript submissions: closed (31 January 2020) | Viewed by 48428

Special Issue Editors

Prof. Dr. Kamal El-Sankary

E-Mail Website
Guest Editor
Electrical & Computer Engineering Department, Dalhousie University, C367, Halifax, NS, Canada
Interests: microelectronics; analog; mixed-signal; digital and RF integrated circuits design in nanoscale CMOS technologies; and embedded systems design
Special Issues, Collections and Topics in MDPI journals
Dr. Tejinder Sandhu

E-Mail Website
Guest Editor
Mixed signal design engineer at Synopsys Inc. Toronto, ON, Canada
Interests: analog and digital circuit design; low power integrated circuits; switched capacitor circuits; analog to digital converters; delay locked loops; phase locked loops

Special Issue Information

Dear Colleagues,

CMOS technology will continue to expand its dominance for the next decade or so despite challenges resulting from the continuous reduction of transistor dimensions. Several promising alternatives to CMOS technology are being actively developed, but CMOS will remain at the forefront of integrated circuit design in the near future owing to process maturity, low manufacturing costs, high speed, and low power consumption.

Continuous transistor scaling comes with many trade-offs: On one hand, it reduces gate delay, which allows transistors to switch faster. Alternatively, size scaling necessitates reduced supply voltages, which severely limits the allowable voltage dynamic range, thereby degrading the signal to noise ratio. Therefore, it is increasingly difficult to design high-speed, low-noise integrated circuits while maintaining the operational reliability of complex ultra-low power devices.  

The scope of this Special Issue is to focus and report on the development of emerging techniques to overcome these challenges.

Specifically, the research portfolio for this issue includes research on low-power RF, mixed-signal and analog CMOS design of circuits and systems, and power-efficient integrated circuit design for communications, sensing and biomedical applications. The topics of primary research include but are not limited to:

  • Recent developments in nanoscale circuits and systems including mixed-signal circuits, RFICs and analog building blocks;
  • Circuit design for emerging 2.5D or 3D IC CMOS technologies;
  • Sub-threshold digital and analog circuits;
  • Process and mismatch insensitive integrated circuit design;
  • Signal processing and digital assisted methods for high performances circuits;
  • Biologically-Inspired system and circuit design;
  • Optimization methods for energy-efficient integrated circuits

Prof. Dr. Kamal El-Sankary
Dr. Tejinder Sandhu
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

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Published Papers (10 papers)

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Research

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11 pages, 4425 KiB  
Article
A 2.4 GHz 2.9 mW Zigbee RF Receiver with Current-Reusing and Function-Reused Mixing Techniques
by Zhikuang Cai, Mingmin Shi, Shanwen Hu and Zixuan Wang
Electronics 2020, 9(4), 697; https://doi.org/10.3390/electronics9040697 - 24 Apr 2020
Cited by 3 | Viewed by 3297
Abstract
This study presents a low-power Zigbee receiver with a current-reusing structure and function-reused mixing techniques. To reduce the overall power consumption, a low noise amplifier (LNA) and a power amplifier (PA) share the biasing current with a voltage-controlled oscillator (VCO) in the receiving [...] Read more.
This study presents a low-power Zigbee receiver with a current-reusing structure and function-reused mixing techniques. To reduce the overall power consumption, a low noise amplifier (LNA) and a power amplifier (PA) share the biasing current with a voltage-controlled oscillator (VCO) in the receiving (RX) mode and transmitting (TX) mode, respectively. The function-reused mixer reuses the radio frequency trans-conductance (RF gm) stage to amplify the down-converted intermediate frequency (IF) signal, obtaining a free IF gain without extra power consumption. A peak detector circuit detects the receiving signal strength and auto-adjusts the biasing current to save power when a strong signal strength is detected. Meanwhile, the peak detector helps to provide a coarse gain control as part of the auto-gain-control function. As part of the IF gain range is shared by the multiple-feedback (MFB) low-pass filter, the number of programmable-gain IF amplifier stages can be reduced, which also means a decrease in power consumption. A prototype of this wireless sensor network (WSN) receiver was designed and fabricated using the TSMC 130 nm CMOS process under a supply voltage of 1 V. The entire receiver realizes a noise figure (NF) of 3.5 dB and a receiving sensitivity of −90 dBm for the 0.25 Mbps offset quadrature phase shift keying (O-QPSK) signal with a power consumption of 2.9 mW. Full article
(This article belongs to the Special Issue Nanoscale CMOS Technologies)
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9 pages, 2567 KiB  
Article
A CMOS Programmable Fourth-Order Butterworth Active-RC Low-Pass Filter
by Changchun Zhang, Long Shang, Yongkai Wang and Lu Tang
Electronics 2020, 9(2), 204; https://doi.org/10.3390/electronics9020204 - 21 Jan 2020
Cited by 15 | Viewed by 5353
Abstract
This paper presents a low-pass filter (LPF) for an ultra-high frequency (UHF) radio frequency identification (RFID) reader transmitter in standard SMIC 0.18 μm CMOS technology. The active-RC topology and Butterworth approximation function are employed mainly for high linearity and high flatness respectively. Two [...] Read more.
This paper presents a low-pass filter (LPF) for an ultra-high frequency (UHF) radio frequency identification (RFID) reader transmitter in standard SMIC 0.18 μm CMOS technology. The active-RC topology and Butterworth approximation function are employed mainly for high linearity and high flatness respectively. Two cascaded fully-differential Tow-Thomas biquads are chosen for low sensitivity to process errors and strong resistance to the imperfection of the involved two-stage fully-differential operational amplifiers. Besides, the LPF is programmable in order to adapt to the multiple data rate standards. Measurement results show that the LPF has the programmable bandwidths of 605/870/1020/1330/1530/2150 kHz, the optimum input 1dB compression point of −7.81 dBm, and the attenuation of 50 dB at 10 times cutoff frequency, with the overall power consumption of 12.6 mW from a single supply voltage of 1.8 V. The silicon area of the LPF core is 0.17 mm2. Full article
(This article belongs to the Special Issue Nanoscale CMOS Technologies)
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18 pages, 6556 KiB  
Article
A 0.5~0.7 V LC Digitally Controlled Oscillator Based on a Multi-Stage Capacitance Shrinking Technique
by Zixuan Wang, Hongyang Wu, Xin Wang, Mingmin Shi, Shanwen Hu, Yufeng Guo and Zhikuang Cai
Electronics 2019, 8(11), 1336; https://doi.org/10.3390/electronics8111336 - 12 Nov 2019
Cited by 3 | Viewed by 3395
Abstract
This paper presents a 2.4 GHz LC digitally controlled oscillator (DCO) at near-threshold supplies (0.5~0.7 V). It was a challenge to achieve a low voltage, low power, and high resolution simultaneously. DCOs with metal oxide semiconductor (MOS) varactors consume low power, but their [...] Read more.
This paper presents a 2.4 GHz LC digitally controlled oscillator (DCO) at near-threshold supplies (0.5~0.7 V). It was a challenge to achieve a low voltage, low power, and high resolution simultaneously. DCOs with metal oxide semiconductor (MOS) varactors consume low power, but their resolution is limited. ΔΣ-DCOs can achieve a high resolution at the cost of high power consumption. A multi-stage capacitance shrinking technique was proposed in this paper to address the tradeoff mentioned above. The unit variable capacitance of the LC tank was largely reduced by the bridging capacitors and the number of stages. A current-reuse technique was used to further lower the power. Based on the above techniques, the prototype was fabricated using a 130-nm complementary MOS (CMOS) technology with multiple supplies (0.5~0.7 V for the DCO core, 1.2 V for the buffer). The measurement results showed that the phase noise at a 0.6-V supply was −126.27 dBc/Hz at 1 MHz and −125.9480 dBc/Hz at 1 MHz at the carriers of 2.4 GHz and 2.5 GHz, respectively. The best figure of merit (FoM) of 195.68 was obtained when VDD = 0.6 V. The DCO core consumed 1.1 mA at a 0.6-V supply. Full article
(This article belongs to the Special Issue Nanoscale CMOS Technologies)
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17 pages, 8465 KiB  
Article
CMOS Voltage Reference Using a Self-Cascode Composite Transistor and a Schottky Diode
by Thaironi M. Brito, Dalton M. Colombo, Robson L. Moreno and Kamal El-Sankary
Electronics 2019, 8(11), 1271; https://doi.org/10.3390/electronics8111271 - 1 Nov 2019
Cited by 3 | Viewed by 4998
Abstract
This work presents an investigation of the temperature behavior of self-cascode composite transistors (SCCTs). Results supported by silicon measurements show that SCCTs can be used to generate a proportional to absolute temperature voltage or even a temperature-compensated voltage. Based on the achieved results, [...] Read more.
This work presents an investigation of the temperature behavior of self-cascode composite transistors (SCCTs). Results supported by silicon measurements show that SCCTs can be used to generate a proportional to absolute temperature voltage or even a temperature-compensated voltage. Based on the achieved results, a new circuit topology of a resistorless voltage reference circuit using a Schottky diode is also presented. The circuit was fabricated in a 130 nm BiCMOS process and occupied a silicon area of 67.98 µm × 161.7 µm. The averaged value of the output voltage is 720.4 mV, and its averaged line regulation performance is 2.3 mV/V, calculated through 26 characterized chip samples. The averaged temperature coefficient (TC) obtained through five chip samples is 56 ppm/°C in a temperature range from −40 to 85 °C. A trimming circuit is also included in the circuit topology to mitigate the impact of the fabrication process effects on its TC. The circuit operates with a supply voltage range from 1.1 to 2.5 V. Full article
(This article belongs to the Special Issue Nanoscale CMOS Technologies)
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15 pages, 2465 KiB  
Article
System Level Optimization for High-Speed SerDes: Background and the Road Towards Machine Learning Assisted Design Frameworks
by Shiming Song and Yu Sui
Electronics 2019, 8(11), 1233; https://doi.org/10.3390/electronics8111233 - 28 Oct 2019
Cited by 5 | Viewed by 7000
Abstract
This decade has witnessed wide use of data-driven systems, from multimedia to scientific computing, and in each case quality data movement infrastructure is required, many with SerDes as a cornerstone. On the one hand, HPC and machine learning cloud infrastructure carry exabytes of [...] Read more.
This decade has witnessed wide use of data-driven systems, from multimedia to scientific computing, and in each case quality data movement infrastructure is required, many with SerDes as a cornerstone. On the one hand, HPC and machine learning cloud infrastructure carry exabytes of data in a year through the backplanes of data centers. On the other hand, the growing need for edge computing in the IoT places a tight envelope on the energy per bits. In this survey, we give a system level overview of the common design challenges in implementing SerDes solutions under different scenarios and propose simulation methods benefiting from advanced machine learning techniques. Preliminary results with the proposed simulation platform are demonstrated and analyzed through machine learning based design methodologies. Full article
(This article belongs to the Special Issue Nanoscale CMOS Technologies)
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15 pages, 1712 KiB  
Article
High-CMRR Low-Noise Fully Integrated Front-End for EEG Acquisition Systems
by Robert Chebli, Mohamed Ali and Mohamad Sawan
Electronics 2019, 8(10), 1157; https://doi.org/10.3390/electronics8101157 - 12 Oct 2019
Cited by 5 | Viewed by 4447
Abstract
We present in this paper a fully integrated low-noise high common-mode rejection ratio (CMRR) logarithmic programmable gain amplifier (LPGA) and chopped LPGA circuits for EEG acquisition systems. The proposed LPGA is based on a rail-to-rail true logarithmic amplifier (TLA) stage. The high CMRR [...] Read more.
We present in this paper a fully integrated low-noise high common-mode rejection ratio (CMRR) logarithmic programmable gain amplifier (LPGA) and chopped LPGA circuits for EEG acquisition systems. The proposed LPGA is based on a rail-to-rail true logarithmic amplifier (TLA) stage. The high CMRR achieved in this work is a result of cascading three amplification stages to construct the LPGA in addition to the lower common-mode gain of the proposed logarithmic amplification topology. In addition, the 1 / f noise and the inherent DC offset voltage of the input transistors are reduced using a chopper stabilization technique. The CMOS 180 nm standard technology is used to implement the circuits. Experimental results for the integrated LPGA show a CMRR of 140 dB, a differential gain of 37 dB, an input-referred noise of 0.754 μ Vrms, a 189 μ W power consumption from 1.8 V power supply and occupies an active area of 0.4 mm 2 . Full article
(This article belongs to the Special Issue Nanoscale CMOS Technologies)
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9 pages, 2312 KiB  
Article
K-Band Low Phase Noise VCO Based on Q-Boosted Switched Inductor
by Zhe Chen, Ji-Xin Chen, Pinpin Yan, Debin Hou and Fang Zhu
Electronics 2019, 8(10), 1132; https://doi.org/10.3390/electronics8101132 - 8 Oct 2019
Cited by 5 | Viewed by 3229
Abstract
In this article, the development of the K-band low phase noise voltage-controlled oscillator (VCO) based on Q-boosted switched inductor is presented. Compared with the conventional switched inductor, the eddy current will be decreased using a 2-turn secondary coil, and then the dissipated power [...] Read more.
In this article, the development of the K-band low phase noise voltage-controlled oscillator (VCO) based on Q-boosted switched inductor is presented. Compared with the conventional switched inductor, the eddy current will be decreased using a 2-turn secondary coil, and then the dissipated power from the switch on-resistance will also be decreased, leading to a boosted inductor Q at switch ON-state. The equivalent inductance, quality factor, and self-resonance frequency at switch ON/OFF states are analyzed and derived. For comparison, K-band VCOs have been designed and fabricated in a 130nm BiCMOS process with the Q-boosted and conventional switched inductors. Measured results show that the phase noise has been typically improved by 2–5dB at 100 kHz and 1 MHz offset at switch ON-state, using the Q-boosted switched inductor. Full article
(This article belongs to the Special Issue Nanoscale CMOS Technologies)
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19 pages, 9563 KiB  
Article
A PVT-Robust Super-Regenerative Receiver with Background Frequency Calibration and Concurrent Quenching Waveform
by Yadong Yin, Ximing Fu and Kamal El-Sankary
Electronics 2019, 8(10), 1119; https://doi.org/10.3390/electronics8101119 - 4 Oct 2019
Cited by 3 | Viewed by 3924
Abstract
A process-voltage-temperature (PVT)-robust, low power, low noise, and high sensitivity, super-regenerative (SR) receiver is proposed in this paper. To enable high sensitivity and robust-PVT operation, a fast locking phase-locked-loop (PLL) with initial random phase error reduction is proposed to continuously adjust the center [...] Read more.
A process-voltage-temperature (PVT)-robust, low power, low noise, and high sensitivity, super-regenerative (SR) receiver is proposed in this paper. To enable high sensitivity and robust-PVT operation, a fast locking phase-locked-loop (PLL) with initial random phase error reduction is proposed to continuously adjust the center frequency deviations of the SR oscillator (SRO) without interrupting the input data stream. Additionally, a concurrent quenching waveform (CQW) technique is devised to improve the SRO sensitivity and its noise performance. The proposed SRO architecture is controlled by two separate biasing branches to extend the sensitivity accumulation (SA) phase and reduce its noise during the SR phase, compared to the conventional optimal quenching waveform (OQW). The proposed SR receiver is implemented at 2.46 GHz center frequency in 180 nm SMIC CMOS technology and achieves better sensitivity, power consumption, noise performance, and PVT immunity compared with existent SR receiver architectures. Full article
(This article belongs to the Special Issue Nanoscale CMOS Technologies)
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12 pages, 4238 KiB  
Article
Innovative Strategy for Mixer Design Optimization Based on gm/ID Methodology
by Giovanni Piccinni, Claudio Talarico, Gianfranco Avitabile and Giuseppe Coviello
Electronics 2019, 8(9), 954; https://doi.org/10.3390/electronics8090954 - 29 Aug 2019
Cited by 8 | Viewed by 4767
Abstract
This work introduces a process to optimize the design of a down-conversion mixer using an innovative strategy based on the gm/ID methodology. The proposed process relies on a set of technology-oriented lookup tables to optimize the trade-off between gain, power [...] Read more.
This work introduces a process to optimize the design of a down-conversion mixer using an innovative strategy based on the gm/ID methodology. The proposed process relies on a set of technology-oriented lookup tables to optimize the trade-off between gain, power dissipation, noise, and distortion. The design is implemented using a 0.13 μm CMOS technology, and to the best of our knowledge, it possesses the best (post-layout simulation) figure of merit (FOM) among the works presented in literature. The FOM is defined as the product of gain and third-order intercept divided the product between average noise figure and power dissipation. Finally, the core of the mixer takes only 31 µm by 28 µm and it draws a current of 1 mA from the 1.5 V DC supply. Full article
(This article belongs to the Special Issue Nanoscale CMOS Technologies)
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21 pages, 4952 KiB  
Review
Design Architectures of the CMOS Power Amplifier for 2.4 GHz ISM Band Applications: An Overview
by Mohammad Arif Sobhan Bhuiyan, Md Torikul Islam Badal, Mamun Bin Ibne Reaz, Maria Liz Crespo and Andres Cicuttin
Electronics 2019, 8(5), 477; https://doi.org/10.3390/electronics8050477 - 29 Apr 2019
Cited by 20 | Viewed by 7204
Abstract
Power amplifiers (PAs) are among the most crucial functional blocks in the radio frequency (RF) frontend for reliable wireless communication. PAs amplify and boost the input signal to the required output power. The signal is amplified to make it sufficiently high for the [...] Read more.
Power amplifiers (PAs) are among the most crucial functional blocks in the radio frequency (RF) frontend for reliable wireless communication. PAs amplify and boost the input signal to the required output power. The signal is amplified to make it sufficiently high for the transmitter to propagate the required distance to the receiver. Attempted advancements of PA have focused on attaining high-performance RF signals for transmitters. Such PAs are expected to require low power consumption while producing a relatively high output power with a high efficiency. However, current PA designs in nanometer and micrometer complementary metal–oxide semiconductor (CMOS) technology present inevitable drawbacks, such as oxide breakdown and hot electron effect. A well-defined architecture, including a linear and simple functional block synthesis, is critical in designing CMOS PA for various applications. This article describes the different state-of-the art design architectures of CMOS PA, including their circuit operations, and analyzes the performance of PAs for 2.4 GHz ISM (industrial, scientific, and medical) band applications. Full article
(This article belongs to the Special Issue Nanoscale CMOS Technologies)
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