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Electronics
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New Trends for High-Performance Computing
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New Trends for High-Performance Computing

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Computer Science & Engineering".

Deadline for manuscript submissions: closed (1 July 2022) | Viewed by 12677

Special Issue Editors

Dr. Xin Liang

E-Mail Website
Guest Editor
Department of Computer Science, Missouri University of Science and Technology, Rolla, MO 65409, USA
Interests: high-performance computing; parallel and distributed systems; scientific data management; large-scale data analytics; distributed machine learning
Dr. Dingwen Tao

E-Mail Website
Guest Editor
School of Electrical Engineering & Computer Science, Washington State University, Pullman, WA 99164, USA
Interests: high-performance computing; data reduction; deep learning; GPU; FPGA

Special Issue Information

Dear colleagues,

High-performance computing (HPC) has revolutionized many domains of science and engineering, including scientific simulation, knowledge discovery, and artificial intelligence. Fully harnessing and exploiting the computing power of HPC systems is expected to further advance those disciplines, but this is becoming more challenging because of the rapid evolution in the designs of recent and future HPC systems. On the one hand, the increasing heterogeneity and deepening memory/storage hierarchy in HPC systems may raise new issues in both computation and data movement. On the other hand, emerging architectures such as tensor processing units, neuromorphic computing, and quantum circuits may require a different paradigm for efficient deployment.

This Special Issue seeks novel research in the context of algorithms, software, and architectures for current and next-generation HPC, including (but not limited to) parallel algorithms that exploit the existing and incoming architectures; system software that enhances the HPC cyberinfrastructure; large-scale applications that take advantage of HPC systems; and novel architectures that feature performance, energy efficiency, or resilience.

Dr. Xin Liang
Dr. Dingwen Tao
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • High-performance computing
  • Parallel, distributed, and heterogeneous systems
  • Big data analytics and visualization
  • Data-intensive computing
  • Large-scale AI/ML/DL algorithms and applications
  • Quantum computing and neuromorphic computing
  • File and storage systems, I/O, and data management
  • Scheduling and resource management
  • Performance modeling
  • Programming systems
  • HPC as a service.

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Published Papers (2 papers)

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Research

11 pages, 360 KiB  
Article
Edge-Based Heuristics for Optimizing Shortcut-Augmented Topologies for HPC Interconnects
by Kazi Ahmed Asif Fuad, Kai Zeng and Lizhong Chen
Electronics 2022, 11(17), 2778; https://doi.org/10.3390/electronics11172778 - 3 Sep 2022
Viewed by 1203
Abstract
Interconnection network topology is critical for the overall performance of HPC systems. While many regular and irregular topologies have been proposed in the past, recent work has shown the promise of shortcut-augmented topologies that offer multi-fold reduction in network diameter and hop count [...] Read more.
Interconnection network topology is critical for the overall performance of HPC systems. While many regular and irregular topologies have been proposed in the past, recent work has shown the promise of shortcut-augmented topologies that offer multi-fold reduction in network diameter and hop count over conventional topologies. However, the large number of possible shortcuts creates an enormous design space for this new type of topology, and existing approaches are extremely slow and do not find shortcuts that are globally optimal. In this paper, we propose an efficient heuristic approach, called EdgeCut, which generates high-quality shortcut-augmented topologies. EdgeCut can identify more globally useful shortcuts by making its considerations from the perspective of edges instead of vertices. An additional implementation is proposed that approximates the costly all-pair shortest paths calculation, thereby further speeding up the scheme. Quantitative comparisons over prior work show that the proposed approach achieves a 1982× reduction in search time while generating better or equivalent topologies in 94.9% of the evaluated cases. Full article
(This article belongs to the Special Issue New Trends for High-Performance Computing)
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23 pages, 3662 KiB  
Article
A Survey of High-Performance Interconnection Networks in High-Performance Computer Systems
by Ping-Jing Lu, Ming-Che Lai and Jun-Sheng Chang
Electronics 2022, 11(9), 1369; https://doi.org/10.3390/electronics11091369 - 25 Apr 2022
Cited by 9 | Viewed by 10406
Abstract
High-performance interconnection network is the key to realizing high-speed, collaborative, parallel computing at each node in a high-performance computer system. Its performance and scalability directly affect the performance and scalability of the whole system. With continuous improvements in the performance of high-performance computer [...] Read more.
High-performance interconnection network is the key to realizing high-speed, collaborative, parallel computing at each node in a high-performance computer system. Its performance and scalability directly affect the performance and scalability of the whole system. With continuous improvements in the performance of high-performance computer systems, the trend in the development of high-performance interconnection networks is mainly reflected in network sizes and network bandwidths. With the slowdown of Moore’s Law, it is necessary to adopt new packaging design technologies to implement high-performance interconnection networks for high-performance computing. This article analyzes the main interconnection networks used by high-performance computer systems in the Top500 list of November 2021, and it elaborates the design of representative, state-of-the-art, high-performance interconnection networks, including NVIDIA InfiniBand, Intel Omni-Path, Cray Slingshot/Aries, and custom or proprietary networks, including Fugaku Tofu, Bull BXI, TH Express, and so forth. This article also comprehensively discusses the latest technologies and trends in this field. In addition, based on the analysis of the challenges faced by high-performance interconnection network design in the post-Moore era and the exascale computing era, this article presents a perspective on high-performance interconnection networks. Full article
(This article belongs to the Special Issue New Trends for High-Performance Computing)
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