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13 pages, 5748 KiB

Open AccessArticle

Development and Characterization of Low Temperature Wafer-Level Vacuum Packaging Using Cu-Sn Bonding and Nanomultilayer Getter

by Taehyun Kim, Sangwug Han, Jubum Lee, Yeeun Na, Joontaek Jung, Yun Chang Park, Jaesub Oh, Chungmo Yang and Hee Yeoun Kim

Micromachines 2023, 14(2), 448; https://doi.org/10.3390/mi14020448 - 14 Feb 2023

Cited by 1 | Viewed by 2211

Abstract

Most microsensors are composed of devices and covers. Due to the complicated structure of the cover and various other requirements, it difficult to use wafer-level packaging with such microsensors. In particular, for monolithic microsensors combined with read-out ICs, the available process margins are [...] Read more.

Most microsensors are composed of devices and covers. Due to the complicated structure of the cover and various other requirements, it difficult to use wafer-level packaging with such microsensors. In particular, for monolithic microsensors combined with read-out ICs, the available process margins are further reduced due to the thermal and mechanical effects applied to IC wafers during the packaging process. This research proposes a low-temperature, wafer-level vacuum packaging technology based on Cu-Sn bonding and nano-multilayer getter materials for use with microbolometers. In Cu-Sn bonding, the Cu/Cu₃Sn/Cu microstructure required to ensure reliability can be obtained by optimizing the bonding temperature, pressure, and time. The Zr-Ti-Ru based nanomultilayer getter coating inside the cap wafer with high step height has been improved by self-aligned shadow masking. The device pad, composed of bonded wafer, was opened by wafer grinding, and the thermoelectrical properties were evaluated at the wafer-level. The bonding strength and vacuum level were characterized by a shear test and thermoelectrical test using microbolometer test pixels. The vacuum level of the packaged samples showed very narrow distribution near 50 mTorr. This wafer-level packaging platform could be very useful for sensor development whereby high reliability and excellent mechanical/optical performance are both required. Due to its reliability and the low material cost and bonding temperature, this wafer-based packaging approach is suitable for commercial applications. Full article

(This article belongs to the Special Issue Advanced Packaging for Microsystem Applications)

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11 pages, 3994 KiB

Open AccessArticle

Effect of Acceptor Traps in GaN Buffer Layer on Breakdown Performance of AlGaN/GaN HEMTs

by Maodan Ma, Yanrong Cao, Hanghang Lv, Zhiheng Wang, Xinxiang Zhang, Chuan Chen, Linshan Wu, Ling Lv, Xuefeng Zheng, Wenchao Tian, Xiaohua Ma and Yue Hao

Micromachines 2023, 14(1), 79; https://doi.org/10.3390/mi14010079 - 28 Dec 2022

Cited by 8 | Viewed by 2644

Abstract

In this paper, Silvaco TCAD software is used to simulate the buffer traps in AlGaN/GaN high electron mobility transistors (HEMTs), and its effects on the breakdown performance and key parameters of the devices are investigated by changing the position and concentration of the [...] Read more.

In this paper, Silvaco TCAD software is used to simulate the buffer traps in AlGaN/GaN high electron mobility transistors (HEMTs), and its effects on the breakdown performance and key parameters of the devices are investigated by changing the position and concentration of the acceptor traps in the buffer layer. The results show that with the increase of trap concentration, the traps capture electrons and reduce the off-state leakage current, which can improve breakdown voltage of the devices. At the same time, as the trap concentration increases, the ionized traps make a high additional electric field near the drain edge, leading to the decrease of breakdown voltage. With the combined two effects above, the breakdown voltage almost ultimately saturates. When the source-to-gate (Access-S) region in the GaN buffer layer is doped alone, the minimum and most linear leakage current for the same trap concentrations are obtained, and the additional electric field has a relatively small effect on the electric field peak near the drain as the ionized traps are furthest from drain. All these factors make the breakdown voltage increase more controllably with the Access-S region doping, and it is a more potential way to improve the breakdown performance. Full article

(This article belongs to the Special Issue Advanced Packaging for Microsystem Applications)

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8 pages, 1732 KiB

Open AccessArticle

Void Suppression in Glass Frit Bonding Via Three-Step Annealing Process

by Yifang Liu, Junyu Chen, Jiaxin Jiang and Gaofeng Zheng

Micromachines 2022, 13(12), 2104; https://doi.org/10.3390/mi13122104 - 29 Nov 2022

Viewed by 2583

Abstract

In this work, void formation was systematically observed for the glass frit bonding technique as a function of the annealing temperature, annealing time, and annealing ambient. High annealing temperature and long annealing time were adopted to reach the maximum heat flux to avoid [...] Read more.

In this work, void formation was systematically observed for the glass frit bonding technique as a function of the annealing temperature, annealing time, and annealing ambient. High annealing temperature and long annealing time were adopted to reach the maximum heat flux to avoid voids/bubbles. As demonstrated in the experiments, the voids appearing during glass frit bonding are related to the quantity of byproducts from the combustion of organic matter. The experimental results indicate that solely in air, under vacuum, or annealed for short time, the combustion products cannot be fully degassed, and voids occur. It was shown that the alternating three-step conditioning process including glass liquid forming in air, bubble removal under vacuum, and void filling-up in air can lead to void-free and uniform wafer bonding. The glass frit bonding samples with lots of voids/bubbles were compared to the ones without any defects. Full article

(This article belongs to the Special Issue Advanced Packaging for Microsystem Applications)

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11 pages, 7049 KiB

Open AccessArticle

Combined Effect of TID Radiation and Electrical Stress on NMOSFETs

by Yanrong Cao, Min Wang, Xuefeng Zheng, Enxia Zhang, Ling Lv, Liang Wang, Maodan Ma, Hanghang Lv, Zhiheng Wang, Yongkun Wang, Wenchao Tian, Xiaohua Ma and Yue Hao

Micromachines 2022, 13(11), 1860; https://doi.org/10.3390/mi13111860 - 29 Oct 2022

Viewed by 1696

Abstract

The combined effect of total ionizing dose (TID) and electrical stress is investigated on NMOSFETs. For devices bearing both radiation and electrical stress, the threshold voltage shift is smaller than those only bearing electrical stress, indicating that the combined effect alleviates the degradation [...] Read more.

The combined effect of total ionizing dose (TID) and electrical stress is investigated on NMOSFETs. For devices bearing both radiation and electrical stress, the threshold voltage shift is smaller than those only bearing electrical stress, indicating that the combined effect alleviates the degradation of the devices. The H bond is broken during the radiation process, which reduces the participation of H atoms in the later stage of electrical stress, thereby reducing the degradation caused by electrical stress. The positive charges of the oxide layer generated by radiation neutralize part of the tunneling electrons caused by electrical stress, and consume some of the electrons that react with the H bond, resulting in weaker degradation. In addition, the positive charges in shallow trench isolation (STI) generated by radiation create parasitic leakage paths at the interfaces of STI/Si, which increase the leakage current and reduce the positive shift of the threshold voltage. The parasitic effect generated by the positive charges of STI makes the threshold voltage of the narrow-channel device degrade more, and due to the gate edge effect, the threshold voltage of short-channel devices degrades more. Full article

(This article belongs to the Special Issue Advanced Packaging for Microsystem Applications)

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18 pages, 5082 KiB

Open AccessArticle

Comprehensive Assessments in Bonding Energy of Plasma Assisted Si-SiO₂ Direct Wafer Bonding after Low Temperature Rapid Thermal Annealing

by Youngseok Lee, Yebin You, Chulhee Cho, Sijun Kim, Jangjae Lee, Minyoung Kim, Hanglim Lee, Youngjun You, Kyungman Kim and ShinJae You

Micromachines 2022, 13(11), 1856; https://doi.org/10.3390/mi13111856 - 29 Oct 2022

Cited by 1 | Viewed by 2907

Abstract

Direct wafer bonding is one of the most attractive techniques for next-generation semiconductor devices, and plasma has been playing an indispensable role in the wider adoption of the wafer bonding technique by lowering its process temperature. Although numerous studies on plasma-assisted direct wafer [...] Read more.

Direct wafer bonding is one of the most attractive techniques for next-generation semiconductor devices, and plasma has been playing an indispensable role in the wider adoption of the wafer bonding technique by lowering its process temperature. Although numerous studies on plasma-assisted direct wafer bonding have been reported, there is still a lack of deep investigations focusing on the plasma itself. Other than the plasma surface treatment, the wafer bonding process includes multiple steps such as surface cleaning and annealing that require comprehensive studies to maximize the bonding strengths. In this work, we evaluate the various process steps of Si-SiO₂ wafer bonding through case-by-case experimental studies, covering factors including the plasma conditions for surface treatment and secondary factors such as the time intervals between some process steps. The results show that plasma treatment with increasing input power has a trade-off between bonding strengths and interfacial voids, requiring the optimization of the plasma conditions. It is also noticeable that the effects of plasma treatment on wafer bonding can be improved when the plasma-treated wafers are stored in ambient atmosphere before the subsequent process step, which may suggest that wafer exposure to air during the bonding process is advantageous compared to processing entirely in vacuum. The results are expected to allow plasma-assisted direct wafer bonding technology to play a bigger role in the packaging process of semiconductor device manufacturing. Full article

(This article belongs to the Special Issue Advanced Packaging for Microsystem Applications)

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14 pages, 6094 KiB

Open AccessArticle

Thermo-Mechanical Reliability Study of Through Glass Vias in 3D Interconnection

by Jin Zhao, Zuohuan Chen, Fei Qin and Daquan Yu

Micromachines 2022, 13(10), 1799; https://doi.org/10.3390/mi13101799 - 21 Oct 2022

Cited by 12 | Viewed by 6274

Abstract

Three-dimensional (3D) interconnection technology based on glass through vias (TGVs) has been used to integrate passive devices, and optoelectronic devices due to its superior electrical qualities, outstanding mechanical stability, and lower cost. Nevertheless, the performance and reliability of the device will be impacted [...] Read more.

Three-dimensional (3D) interconnection technology based on glass through vias (TGVs) has been used to integrate passive devices, and optoelectronic devices due to its superior electrical qualities, outstanding mechanical stability, and lower cost. Nevertheless, the performance and reliability of the device will be impacted by the thermal stress brought on by the mismatch of the coefficient of thermal expansion among multi-material structures and the complicated structure of TGV. This paper focuses on thermal stress evolution in different geometric and material parameters and the development of a controlled method for filling polymers in TGV interconnected structures. In addition, a numerical study based on the finite element (FE) model has been conducted to analyze the stress distribution of the different thicknesses of TGV-Cu. Additionally, a TGV interconnected structure model with a polymer buffer layer is given to solve the crack problem appearing at the edge of RDL. Meanwhile, after practical verification, in comparison to the experimental results, the FE model was shown to be highly effective and accurate for predicting the evolution of stress, and several recommendations were made to alleviate stress-related reliability concerns. An improved manufacturing process flow for the TGV interconnected structure was proposed and verified as feasible to address the RDL crack issue based on the aforementioned research. It provides helpful information for the creation of highly reliable TGV connection structures. Full article

(This article belongs to the Special Issue Advanced Packaging for Microsystem Applications)

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11 pages, 3966 KiB

Open AccessArticle

Effects of Moisture Diffusion on a System-in-Package Module by Moisture–Thermal–Mechanical-Coupled Finite Element Modeling

by Zhiwen Chen, Zheng Feng, Meng Ruan, Guoliang Xu and Li Liu

Micromachines 2022, 13(10), 1704; https://doi.org/10.3390/mi13101704 - 10 Oct 2022

Cited by 6 | Viewed by 2189

Abstract

Epoxy molding compounds (EMCs) are commonly used in electronic products for chip encapsulation, but the moisture absorption of EMC can induce significant reliability challenges. In this study, the effects of hygrothermal conditions and structure parameters on moisture diffusion and the consequent influences (such [...] Read more.

Epoxy molding compounds (EMCs) are commonly used in electronic products for chip encapsulation, but the moisture absorption of EMC can induce significant reliability challenges. In this study, the effects of hygrothermal conditions and structure parameters on moisture diffusion and the consequent influences (such as moisture content on die surfaces and stress distribution) on a system-in-package module have been systematically investigated by moisture–thermal–mechanical-coupled modeling. Hygroscopic tests were carried out on a new commercial EMC at 60 °C/60% RH and 85 °C/85% RH, followed by evaluations of diffusion coefficients by Fick’s law. It was found that the moisture diffusion coefficients and saturation concentrations at 85 °C/85% RH were higher than those at 60 °C/60% RH. From the modeling, it was found that the consequent maximum out-of-plane deformation and stress of the module at 85 °C/85% RH were both higher than those at 60 °C/60% RH. Influences of thicknesses of EMC and PCB on the moisture diffusion behavior have also been studied for design optimization. It was found that the maximum moisture concentration on die surfaces and resultant stress increased notably with thinner PCB, whereas the effects of EMC thickness were limited. This can be attributed to the comparison between the thicknesses of EMC and PCB and the shortest existing diffusion path within the module. These findings can provide helpful insights to the design optimization of electronic modules for hygrothermal conditions. Full article

(This article belongs to the Special Issue Advanced Packaging for Microsystem Applications)

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17 pages, 6187 KiB

Open AccessArticle

Height Uniformity Simulation and Experimental Study of Electroplating Gold Bump for 2.5D/3D Integrated Packaging

by Wenchao Tian, Zhao Li, Yongkun Wang and Guoguang Zhang

Micromachines 2022, 13(9), 1537; https://doi.org/10.3390/mi13091537 - 17 Sep 2022

Cited by 4 | Viewed by 3286

Abstract

With the rapid development of nano/micro technology for commercial electronics, the typical interconnection method could not satisfy the high power-density packaging requirement. The 2.5D/3D integrated packaging was seen as a promising technology for nano/micro systems. The gold (Au) bump was the frequently used [...] Read more.

With the rapid development of nano/micro technology for commercial electronics, the typical interconnection method could not satisfy the high power-density packaging requirement. The 2.5D/3D integrated packaging was seen as a promising technology for nano/micro systems. The gold (Au) bump was the frequently used bonding method for these systems because of its excellent thermal, electric, and mechanical performance. However, relatively little work has been performed to analyze its height uniformity. In this study, the simulation and experimental methods were used to analyze the Au bump height uniformity. Firstly, the electroplating process of Au bump under different flow field parameters was simulated by COMSOL software. The simulated results indicated that the Au⁺ concentration polarization was the significant reason that caused the non-uniform distribution of Au bump along the wafer radius. Meanwhile, the flow field parameters, such as inlet diameter, inlet flow, titanium (Ti), wire mesh height, and Ti wire mesh density, were optimized, and their values were 20 mm, 20 L/min, 12 mm, and 50%, respectively. Subsequently, the Au bump height uniformity under different current densities was analyzed through an experimental method based on these flow field parameters. The experimental results showed that the increases of current density would decrease the Au bump height uniformity. When the current density was 0.2 A/dm², the average height, range, and deviance values of Au bump were 9.04 μm, 1.33 μm, and 0.43 μm, respectively, which could reach the requirement of high density and precision for 2.5D/3D integrated packaging. Full article

(This article belongs to the Special Issue Advanced Packaging for Microsystem Applications)

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16 pages, 4959 KiB

Open AccessArticle

Visualization and Heat Transfer Performance of Mini-Grooved Flat Heat Pipe Filled with Different Working Fluids

by Fei Xin, Qiang Lyu and Wenchao Tian

Micromachines 2022, 13(8), 1341; https://doi.org/10.3390/mi13081341 - 18 Aug 2022

Cited by 4 | Viewed by 1850

Abstract

Mini-grooved flat heat pipe (MGFHP) possesses the advantages of high compactness, no mechanical component, super thermal conductivity, and excellent temperature uniformity, which can meet the demand for electronic devices efficiently cooling. In this research, visual and heat transfer experiments were performed to investigate [...] Read more.

Mini-grooved flat heat pipe (MGFHP) possesses the advantages of high compactness, no mechanical component, super thermal conductivity, and excellent temperature uniformity, which can meet the demand for electronic devices efficiently cooling. In this research, visual and heat transfer experiments were performed to investigate the flow and thermal characteristics inside the MGFHP. Fluid flow and distribution are observed to be quite different in the MGFHP containing different working fluids, which is affected by the physical properties of working fluid, the surface state of the grooved wick, and limited working space. Additionally, the input heat, working fluid type, filling ratio, and wettability obviously affect the thermal conductivity and temperature uniformity of the MGFHP. The deionized water-filled MGFHP possesses lower thermal resistance and higher heat transfer capacity than anhydrous ethanol or hexane filled MGFHP, especially for the copper oxide MGFHP filled with deionized water with a filling ratio of 1.0. Thermal resistance, maximum temperature, and temperature nonuniformity at the condensation section of deionized water-filled copper oxide MGFHP are lower than those of the original copper MGFHP by 31.1%, 3.7 °C, and 0.11 °C for the anhydrous ethanol filled MGFHP and 34.4%, 3.1 °C, and 0.13 °C for the hexane filled MGFHP, respectively. Full article

(This article belongs to the Special Issue Advanced Packaging for Microsystem Applications)

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13 pages, 1989 KiB

Open AccessArticle

A Method for Broadband Polyimide Permittivity Measurement of Silicon Interposer Applied for High Speed Digital Microsystem

by Zhuoyue Zheng, Yongkun Wang, Lei Han, Daowei Wu, Defeng Mo and Wenchao Tian

Micromachines 2022, 13(7), 1138; https://doi.org/10.3390/mi13071138 - 18 Jul 2022

Cited by 1 | Viewed by 1889

Abstract

High-speed digital microsystems has emerged as one of the most important solutions for improving system performance, bandwidth, and power consumption. Based on mature micro-system processing technology, a material extraction approach for silicon interposer applied for high-speed digital microsystems was presented in order to [...] Read more.

High-speed digital microsystems has emerged as one of the most important solutions for improving system performance, bandwidth, and power consumption. Based on mature micro-system processing technology, a material extraction approach for silicon interposer applied for high-speed digital microsystems was presented in order to obtain frequency-dependent precise material parameters. By combining microwave theory and mathematical model of iterative algorithm, the dielectric constant (Dk) and the dissipation factor (Df) of polyimide dielectric layer is acquired, which minimizes testing costs and streamlines testing process. The method is based on two-port transmission/reflection measurements. Vector Network Analyzer (VNA) is used to extract the scattering parameters with an extraction range of 1 MHz to 10 GHz. The algorithm is programmed using MATLAB. The observed Dk values at 2 GHz, 6 GHz, 8 GHz, and 10 GHz are, respectively, 3.22, 3.04, 2.96, 3.03, and 2.91, while the corresponding Df values are 0.021, 0.025, 0.026, 0.026, and 0.024. Finally, the complex permittivity derived is simulated and analyzed using Ansys HFSS. The results verify the validity of the theoretical method and proves that the values of the complex permittivity obtained by the method in this paper are reliable. Full article

(This article belongs to the Special Issue Advanced Packaging for Microsystem Applications)

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17 pages, 2894 KiB

Open AccessArticle

Bond Wire Damage Detection Method on Discrete MOSFETs Based on Two-Port Network Measurement

by Minghui Yun, Miao Cai, Daoguo Yang, Yiren Yang, Jing Xiao and Guoqi Zhang

Micromachines 2022, 13(7), 1075; https://doi.org/10.3390/mi13071075 - 7 Jul 2022

Cited by 5 | Viewed by 2630

Abstract

Bond wire damage is one of the most common failure modes of metal-oxide semiconductor field-effect transistor (MOSFET) power devices in wire-welded packaging. This paper proposes a novel bond wire damage detection approach based on two-port network measurement by identifying the MOSFET source parasitic [...] Read more.

Bond wire damage is one of the most common failure modes of metal-oxide semiconductor field-effect transistor (MOSFET) power devices in wire-welded packaging. This paper proposes a novel bond wire damage detection approach based on two-port network measurement by identifying the MOSFET source parasitic inductance (L_S). Numerical calculation shows that the number of bond wire liftoffs will change the L_S, which can be used as an effective bond wire damage precursor. Considering a power MOSFET as a two-port network, L_S is accurately extracted from frequency domain impedance (Z−parameter) using a vector network analyzer under zero biasing conditions. Bond wire cutoff experiments are employed to validate the proposed approach for bond wire damage detection. The result shows that L_S increases with the rising severity of bond wire faults, and even the slight fault shows a high sensitivity, which can be effectively used to quantify the number of bond wire liftoffs of discrete MOSFETs. Meanwhile, the source parasitic resistance (R_S) extracted from the proposed two-port network measurement can be used for the bond wire damage detection of high switching frequency silicon carbide MOSFETs. This approach offers an effective quality screening technology for discrete MOSFETs without power on treatment. Full article

(This article belongs to the Special Issue Advanced Packaging for Microsystem Applications)

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8 pages, 2690 KiB

Open AccessArticle

Effect of Grain Structure and Ni/Au-UBM Layer on Electromigration-Induced Failure Mechanism in Sn-3.0Ag-0.5Cu Solder Joints

by Yuanxiang Zhang, Jicheng Zhang, Yong Wang and Yike Fang

Micromachines 2022, 13(6), 953; https://doi.org/10.3390/mi13060953 - 16 Jun 2022

Cited by 4 | Viewed by 2815

Abstract

The development of advanced electronic devices leads to highly miniaturized interconnect circuits (ICs), which significantly increases the electromigration (EM) phenomenon of solder and circuits due to higher current density. The electromigration of solder joints under high current density has become a severe reliability [...] Read more.

The development of advanced electronic devices leads to highly miniaturized interconnect circuits (ICs), which significantly increases the electromigration (EM) phenomenon of solder and circuits due to higher current density. The electromigration of solder joints under high current density has become a severe reliability concern in terms of microelectronic product reliability. The microstructure of the solder plays an important role in the electromigration induced degradation. In this study, Sn-3.0Ag-0.5Cu solder bumps with Ni/Au under bump metallization (UBM) layer were fabricated and electromigration acceleration tests were conducted under current density of 1.4 × 10⁴ A/cm² and 120 °C to investigate the effect of grain structure and Ni/Au-UBM layer on EM-induced failure. Grain structures of solder bumps were determined by utilizing the Electron Backscatter Diffraction (EBSD) technique, and single-crystal solder, single-crystal dominated solder, and polycrystalline solder are observed in different test samples. According to the Scanning Electron Microscope (SEM) images, it is observed that the Ni/Au-UBM layer of the Cu pad can inhibit atom diffusion between solder bump and Cu pad, which reduces the consumption of Cu pad but causes a large void and crack at the interface. The EM lifetime of single crystal solder bumps is lower than that of polycrystalline solder bumps when the c-axis of single crystal solder bumps is perpendicular to the electron flow direction. Additionally, the single crystal structure will increase the brittleness of the solder bump, and cracks are easily generated and expanded under the stress caused by the mismatch of thermal expansion coefficients between the solder bump and Ni/Au-UBM layer near Cu pad. Polycrystalline solder bumps with a higher misorientation angle (15–55°) have a higher atom diffusion rate, which will result in the acceleration of the EM-induced failure. Full article

(This article belongs to the Special Issue Advanced Packaging for Microsystem Applications)

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23 pages, 7627 KiB

Open AccessFeature PaperEditor’s ChoiceArticle

Thermal Induced Interface Mechanical Response Analysis of SMT Lead-Free Solder Joint and Its Adaptive Optimization

by Shaoyi Liu, Yuefei Yan, Yijiang Zhou, Baoqing Han, Benben Wang, Daxing Zhang, Song Xue, Zhihai Wang, Kunpeng Yu, Yu Shi and Congsi Wang

Micromachines 2022, 13(6), 908; https://doi.org/10.3390/mi13060908 - 8 Jun 2022

Cited by 7 | Viewed by 5201

Abstract

Surface mount technology (SMT) plays an important role in integrated circuits, but due to thermal stress alternation caused by temperature cycling, it tends to have thermo-mechanical reliability problems. At the same time, considering the environmental and health problems of lead (Pb)-based solders, the [...] Read more.

Surface mount technology (SMT) plays an important role in integrated circuits, but due to thermal stress alternation caused by temperature cycling, it tends to have thermo-mechanical reliability problems. At the same time, considering the environmental and health problems of lead (Pb)-based solders, the electronics industry has turned to lead-free solders, such as ternary alloy Sn-3Ag-0.5Cu (SAC305). As lead-free solders exhibit visco-plastic mechanical properties significantly affected by temperature, their thermo-mechanical reliability has received considerable attention. In this study, the interface delamination of an SMT solder joint using a SAC305 alloy under temperature cycling has been analyzed by the nonlinear finite element method. The results indicate that the highest contact pressure at the four corners of the termination/solder horizontal interface means that delamination is most likely to occur, followed by the y-direction side region of the solder/land interface and the top arc region of the termination/solder vertical interface. It should be noted that in order to keep the shape of the solder joint in the finite element model consistent with the actual situation after the reflow process, a minimum energy-based morphology evolution method has been incorporated into the established finite element model. Eventually, an Improved Efficient Global Optimization (IEGO) method was used to optimize the geometry of the SMT solder joint in order to reduce the contact pressure at critical points and critical regions. The optimization result shows that the contact pressure at the critical points and at the critical regions decreases significantly, which also means that the probability of thermal-induced delamination decreases. Full article

(This article belongs to the Special Issue Advanced Packaging for Microsystem Applications)

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15 pages, 6140 KiB

Open AccessArticle

Investigation on SMT Product Defect Recognition Based on Multi-Source and Multi-Dimensional Data Reconstruction

by Jiantao Chang, Zixuan Qiao, Qibin Wang, Xianguang Kong and Yunsong Yuan

Micromachines 2022, 13(6), 860; https://doi.org/10.3390/mi13060860 - 30 May 2022

Cited by 4 | Viewed by 2875

Abstract

The recognition of defects in the solder paste printing process significantly influences the surface-mounted technology (SMT) production quality. However, defect recognition via inspection by a machine has poor accuracy, resulting in a need for the manual rechecking of many defects and a high [...] Read more.

The recognition of defects in the solder paste printing process significantly influences the surface-mounted technology (SMT) production quality. However, defect recognition via inspection by a machine has poor accuracy, resulting in a need for the manual rechecking of many defects and a high production cost. In this study, we investigated SMT product defect recognition based on multi-source and multi-dimensional data reconstruction for the SMT production quality control process in order to address this issue. Firstly, the correlation between features and defects was enhanced by feature interaction, selection, and conversion. Then, a defect recognition model for the solder paste printing process was constructed based on feature reconstruction. Finally, the proposed model was validated on a SMT production dataset and compared with other methods. The results show that the accuracy of the proposed defect recognition model is 96.97%. Compared with four other methods, the proposed defect recognition model has higher accuracy and provides a new approach to improving the defect recognition rate in the SMT production quality control process. Full article

(This article belongs to the Special Issue Advanced Packaging for Microsystem Applications)

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Review

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17 pages, 2590 KiB

Open AccessReview

Using Chiplet Encapsulation Technology to Achieve Processing-in-Memory Functions

by Wenchao Tian, Bin Li, Zhao Li, Hao Cui, Jing Shi, Yongkun Wang and Jingrong Zhao

Micromachines 2022, 13(10), 1790; https://doi.org/10.3390/mi13101790 - 20 Oct 2022

Cited by 14 | Viewed by 6677

Abstract

With the rapid development of 5G, artificial intelligence (AI), and high-performance computing (HPC), there is a huge increase in the data exchanged between the processor and memory. However, the “storage wall” caused by the von Neumann architecture severely limits the computational performance of [...] Read more.

With the rapid development of 5G, artificial intelligence (AI), and high-performance computing (HPC), there is a huge increase in the data exchanged between the processor and memory. However, the “storage wall” caused by the von Neumann architecture severely limits the computational performance of the system. To efficiently process such large amounts of data and break up the “storage wall”, it is necessary to develop processing-in-memory (PIM) technology. Chiplet combines processor cores and memory chips with advanced packaging technologies, such as 2.5D, 3 dimensions (3D), and fan-out packaging. This improves the quality and bandwidth of signal transmission and alleviates the “storage wall” problem. This paper reviews the Chiplet packaging technology that has achieved the function of PIM in recent years and analyzes some of its application results. First, the research status and development direction of PIM are presented and summarized. Second, the Chiplet packaging technologies that can realize the function of PIM are introduced, which are divided into 2.5D, 3D packaging, and fan-out packaging according to their physical form. Further, the form and characteristics of their implementation of PIM are summarized. Finally, this paper is concluded, and the future development of Chiplet in the field of PIM is discussed. Full article

(This article belongs to the Special Issue Advanced Packaging for Microsystem Applications)

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