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13 pages, 5511 KiB

Open AccessArticle

A Novel 4H-SiC SGT MOSFET with Improved P+ Shielding Region and Integrated Schottky Barrier Diode

by Xiaobo Cao, Jing Liu, Yingnan An, Xing Ren and Zhonggang Yin

Micromachines 2024, 15(7), 933; https://doi.org/10.3390/mi15070933 - 22 Jul 2024

Viewed by 962

A silicon carbide (SiC) SGT MOSFET featuring a “一”-shaped P+ shielding region (PSR), named SPDT-MOS, is proposed in this article. The improved PSR is introduced as a replacement for the source trench to enhance the forward performance of the device. Its improvement consists [...] Read more.

A silicon carbide (SiC) SGT MOSFET featuring a “一”-shaped P+ shielding region (PSR), named SPDT-MOS, is proposed in this article. The improved PSR is introduced as a replacement for the source trench to enhance the forward performance of the device. Its improvement consists of two parts. One is to optimize the electric field distribution of the device, and the other is to expand the current conduction path. Based on the improved PSR and grounded split gate (SG), the device remarkably improves the conduction characteristics, gate oxide reliability, and frequency response. Moreover, the integrated sidewall Schottky barrier diode (SBD) prevents the inherent body diode from being activated and improves the reverse recovery characteristics. As a result, the gate-drain capacitance, gate charge, and reverse recovery charge (Q_rr) of the SPDT-MOS are 81.2%, 41.2%, and 90.71% lower than those of the DTMOS, respectively. Compared to the double shielding (DS-MOS), the SPDT-MOS exhibits a 20% reduction in on-resistance and an 8.1% increase in breakdown voltage. Full article

(This article belongs to the Special Issue Power Semiconductor Devices and Applications, 2nd Edition)

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18 pages, 9329 KiB

Open AccessArticle

Switching and Frequency Response Assessment of Photovoltaic Drivers and Their Potential for Different Applications

by Walid Issa, Jose Ortiz Gonzalez and Olayiwola Alatise

Micromachines 2024, 15(7), 832; https://doi.org/10.3390/mi15070832 - 27 Jun 2024

Viewed by 740

Abstract

Newly introduced Photovoltaic (PV) devices, featuring a built-in chip with an illuminating Light Emitting Diode (LED), have emerged in the commercial market. These devices are touted for their utility as both low- and high-side power switch drivers and for data acquisition coupling. However, [...] Read more.

Newly introduced Photovoltaic (PV) devices, featuring a built-in chip with an illuminating Light Emitting Diode (LED), have emerged in the commercial market. These devices are touted for their utility as both low- and high-side power switch drivers and for data acquisition coupling. However, comprehensive knowledge and experimentation regarding the limitations of these Photovoltaic Drivers in both switching and signal processing applications remain underexplored. This paper presents a detailed characterization of a Photovoltaic Driver, focusing on its performance under resistive and capacitive loads. Additionally, it delineates the device’s constraints when employed in signal processing. Through the analysis of switching losses across various power switches (Silicon and Silicon Carbide) in both series and parallel driver configurations, this study assesses the driver’s efficacy in operating Junction Field-Effect Transistors (JFETs). Findings suggest that Photovoltaic Drivers offer a low-cost, compact solution for specific applications, such as high-voltage, low-bandwidth measurements, and low-speed turn-on with fast turn-off power switching scenarios, including solid-state switches and hot-swap circuits. Moreover, they present a straightforward, cost-effective method for driving JFETs, simplifying the circuit design and eliminating the need for an additional negative power source. Full article

(This article belongs to the Special Issue Power Semiconductor Devices and Applications, 2nd Edition)

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12 pages, 3850 KiB

Open AccessArticle

A Novel Deep-Trench Super-Junction SiC MOSFET with Improved Specific On-Resistance

by Rongyao Ma, Ruoyu Wang, Hao Fang, Ping Li, Longjie Zhao, Hao Wu, Zhiyong Huang, Jingyu Tao and Shengdong Hu

Micromachines 2024, 15(6), 684; https://doi.org/10.3390/mi15060684 - 23 May 2024

Viewed by 1670

Abstract

In this paper, a novel 4H-SiC deep-trench super-junction MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) with a split-gate is proposed and theoretically verified by Sentaurus TCAD simulations. A deep trench filled with P-poly-Si combined with the P-SiC region leads to a charge balance effect. Instead of [...] Read more.

In this paper, a novel 4H-SiC deep-trench super-junction MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) with a split-gate is proposed and theoretically verified by Sentaurus TCAD simulations. A deep trench filled with P-poly-Si combined with the P-SiC region leads to a charge balance effect. Instead of a full-SiC P region in conventional super-junction MOSFET, this new structure reduces the P region in a super-junction MOSFET, thus helping to lower the specific on-resistance. As a result, the figure of merit (FoM, BV²/R_on,sp) of the proposed new structure is 642% and 39.65% higher than the C-MOS and the SJ-MOS, respectively. Full article

(This article belongs to the Special Issue Power Semiconductor Devices and Applications, 2nd Edition)

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12 pages, 6658 KiB

Open AccessArticle

A Novel Asymmetric Trench SiC Metal–Oxide–Semiconductor Field-Effect Transistor with a Poly-Si/SiC Heterojunction Diode for Optimizing Reverse Conduction Performance

by Yiren Yu, Zijun Cheng, Yi Hu, Ruiyi Lv and Shengdong Hu

Micromachines 2024, 15(4), 461; https://doi.org/10.3390/mi15040461 - 29 Mar 2024

Cited by 1 | Viewed by 1599

Abstract

In this paper, a novel asymmetric trench SiC MOSFET with a Poly-Si/SiC heterojunction diode (HJD-ATMOS) is designed to improve its reverse conduction characteristics and switching performance. This structure features an integrated heterojunction diode, which improves body diode characteristics without affecting device static characteristics. [...] Read more.

In this paper, a novel asymmetric trench SiC MOSFET with a Poly-Si/SiC heterojunction diode (HJD-ATMOS) is designed to improve its reverse conduction characteristics and switching performance. This structure features an integrated heterojunction diode, which improves body diode characteristics without affecting device static characteristics. The heterojunction diode acts as a freewheeling diode during reverse conduction, reducing the cut-in voltage (V_cut-in) to a lower level than conventional asymmetric trench SiC MOSFET (C-ATMOS), while maintaining a similar breakdown voltage. Meanwhile, the split gate structure reduces gate-to-drain charge (Q_gd). Through TCAD simulation, the HJD-ATMOS decreases V_cut-in by 53.04% compared to the C-ATMOS. Both Q_gd and switching loss are reduced, with a decrease of 31.91% in Q_gd and 40.29% in switching loss. Full article

(This article belongs to the Special Issue Power Semiconductor Devices and Applications, 2nd Edition)

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12 pages, 3372 KiB

Open AccessArticle

Machine Learning-Based Figure of Merit Model of SIPOS Modulated Drift Region for U-MOSFET

by Zhen Cao, Qi Sun, Chuanfeng Ma, Biao Hou and Licheng Jiao

Micromachines 2024, 15(3), 411; https://doi.org/10.3390/mi15030411 - 19 Mar 2024

Viewed by 1050

Abstract

This paper presents a machine learning-based figure of merit model for superjunction (SJ) U-MOSFET (SSJ-UMOS) with a modulated drift region utilizing semi-insulating poly-crystalline silicon (SIPOS) pillars. This SJ drift region modulation is achieved through SIPOS pillars beneath the trench gate, focusing on optimizing [...] Read more.

This paper presents a machine learning-based figure of merit model for superjunction (SJ) U-MOSFET (SSJ-UMOS) with a modulated drift region utilizing semi-insulating poly-crystalline silicon (SIPOS) pillars. This SJ drift region modulation is achieved through SIPOS pillars beneath the trench gate, focusing on optimizing the tradeoff between breakdown voltage (BV) and specific ON-resistance (R_ON_,sp). This analytical model considers the effects of electric field modulation, charge-coupling, and majority carrier accumulation due to additional SIPOS pillars. Gaussian process regression is employed for the figure of merit (FOM = BV²/R_ON_,sp) prediction and hyperparameter optimization, ensuring a reasonable and accurate model. A methodology is devised to determine the optimal BV-R_ON_,sp tradeoff, surpassing the SJ silicon limit. The paper also delves into a discussion of optimal structural parameters for drift region, oxide thickness, and electric field modulation coefficients within the analytical model. The validity of the proposed model is robustly confirmed through comprehensive verification against TCAD simulation results. Full article

(This article belongs to the Special Issue Power Semiconductor Devices and Applications, 2nd Edition)

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16 pages, 3231 KiB

Open AccessArticle

Analysis and Verification of Heat Dissipation Structures Embedded in Substrates in Power Chips Based on Square Frustums Thermal through Silicon Vias

by Fengjie Guo, Kui Ma, Jingyang Ran and Fashun Yang

Micromachines 2024, 15(3), 323; https://doi.org/10.3390/mi15030323 - 26 Feb 2024

Cited by 1 | Viewed by 1267

Abstract

A novel heat dissipation structure composed of square frustums thermal through silicon via array and embedded in P-type (100) silicon substrate is proposed to improve the heat dissipation capacity of power chips while reducing process difficulty. Based on theoretical analysis, the heat transfer [...] Read more.

A novel heat dissipation structure composed of square frustums thermal through silicon via array and embedded in P-type (100) silicon substrate is proposed to improve the heat dissipation capacity of power chips while reducing process difficulty. Based on theoretical analysis, the heat transfer model and thermo-electric coupling reliability model of a power chip with the proposed heat dissipation structure are established. A comparative study of simulation indicates that the proposed heat dissipation structure, which can avoid problems such as softness, poor rigidity, fragility and easy fracture caused by thinning chips has better heat dissipation capability than thinning the substrate of power chips. Full article

(This article belongs to the Special Issue Power Semiconductor Devices and Applications, 2nd Edition)

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11 pages, 1450 KiB

Open AccessCommunication

Investigation and Modeling of the Behavior of Temperature Characteristics of 0.3–1.1 GHz Complementary Metal Oxide Semiconductor Class-A Broadband Power Amplifiers

by Ruiliang Li, Shaohua Zhou, Cheng Yang and Jian Wang

Micromachines 2024, 15(2), 246; https://doi.org/10.3390/mi15020246 - 6 Feb 2024

Viewed by 1155

Abstract

A power amplifier (PA) stands as a central module within the electronic information system (EIS), and any variation in a PA’s specifications has a direct impact on the EIS’s performance, especially in the face of temperature fluctuations. In examining the influence of PA [...] Read more.

A power amplifier (PA) stands as a central module within the electronic information system (EIS), and any variation in a PA’s specifications has a direct impact on the EIS’s performance, especially in the face of temperature fluctuations. In examining the influence of PA specification changes on the EIS, we employed support vector machine (SVM) to model the behavior of the temperature characteristics of 0.3–1.1 GHz complementary metal oxide semiconductor (CMOS) class-A broadband PAs. The results show that the parameters of S₁₁, S₁₂, S₂₁, and S₂₂ can be effectively modeled. SVM outperforms Elman and GRNN in terms of combined modeling time and modeling accuracy. This research can be extended to modeling the behavior of other types of power amplifiers or devices and circuits. Full article

(This article belongs to the Special Issue Power Semiconductor Devices and Applications, 2nd Edition)

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13 pages, 6969 KiB

Open AccessArticle

A Highly Integrated C-Band Feedback Resistor Transceiver Front-End Based on Inductive Resonance and Bandwidth Expansion Techniques

by Boyang Shan, Haipeng Fu and Jian Wang

Micromachines 2024, 15(2), 169; https://doi.org/10.3390/mi15020169 - 23 Jan 2024

Cited by 1 | Viewed by 1113

Abstract

This paper presents a highly integrated C-band RF transceiver front-end design consisting of two Single Pole Double Throw (SPDT) transmit/receive (T/R) switches, a Low Noise Amplifier (LNA), and a Power Amplifier (PA) for Ultra-Wideband (UWB) positioning system applications. When fabricated using a 0.25 [...] Read more.

This paper presents a highly integrated C-band RF transceiver front-end design consisting of two Single Pole Double Throw (SPDT) transmit/receive (T/R) switches, a Low Noise Amplifier (LNA), and a Power Amplifier (PA) for Ultra-Wideband (UWB) positioning system applications. When fabricated using a 0.25 μm GaAs pseudomorphic high electron mobility transistor (pHEMT) process, the switch is optimized for system isolation and stability using inductive resonance techniques. The transceiver front-end achieves overall bandwidth expansion as well as the flat noise in receive mode using the bandwidth expansion technique. The results show that the front-end modules (FEM) have a typical gain of 22 dB in transmit mode, 18 dB in receive mode, and 2 dB noise in the 4.5–8 GHz band, with a chip area of 1.56 × 1.46 mm². Based on the available literature, it is known that the proposed circuit is the most highly integrated C-band RF transceiver front-end design for UWB applications in the same process. Full article

(This article belongs to the Special Issue Power Semiconductor Devices and Applications, 2nd Edition)

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10 pages, 4841 KiB

Open AccessArticle

A 2.8 kV Breakdown Voltage α-Ga₂O₃ MOSFET with Hybrid Schottky Drain Contact

by Seung Yoon Oh, Yeong Je Jeong, Inho Kang, Ji-Hyeon Park, Min Jae Yeom, Dae-Woo Jeon and Geonwook Yoo

Micromachines 2024, 15(1), 133; https://doi.org/10.3390/mi15010133 - 14 Jan 2024

Cited by 2 | Viewed by 2143

Abstract

Among various polymorphic phases of gallium oxide (Ga₂O₃), α-phase Ga₂O₃ has clear advantages such as its heteroepitaxial growth as well as wide bandgap, which is promising for use in power devices. In this work, we demonstrate [...] Read more.

Among various polymorphic phases of gallium oxide (Ga₂O₃), α-phase Ga₂O₃ has clear advantages such as its heteroepitaxial growth as well as wide bandgap, which is promising for use in power devices. In this work, we demonstrate α-Ga₂O₃ MOSFETs with hybrid Schottky drain (HSD) contact, comprising both Ohmic and Schottky electrode regions. In comparison with conventional Ohmic drain (OD) contact, a lower on-resistance (R_on) of 2.1 kΩ mm is achieved for variable channel lengths. Physics-based TCAD simulation is performed to validate the turn-on characteristics of the Schottky electrode region and the improved R_on. Electric-field analysis in the off-state is conducted for both the OD and HSD devices. Furthermore, a record breakdown voltage (BV) of 2.8 kV is achieved, which is superior to the 1.7 kV of the compared OD device. Our results show that the proposed HSD contact with a further optimized design can be a promising drain electrode scheme for α-Ga₂O₃ power MOSFETs. Full article

(This article belongs to the Special Issue Power Semiconductor Devices and Applications, 2nd Edition)

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16 pages, 6556 KiB

Open AccessArticle

Analysis of the Operation Mechanism of Superjunction in RC-IGBT and a Novel Snapback-Free Partial Schottky Collector Superjunction RC-IGBT

by Song Yuan, Yichong Li, Min Hou, Xi Jiang, Xiaowu Gong and Yue Hao

Micromachines 2024, 15(1), 73; https://doi.org/10.3390/mi15010073 - 29 Dec 2023

Cited by 1 | Viewed by 1458

Abstract

This paper explores the operation mechanism of the superjunction structure in RC-IGBTs based on carrier distribution and analyzes the advantages and challenges associated with its application in RC-IGBTs for the first time. A Partial Schottky Collector Superjunction Reverse Conduction IGBT (PSC-SJ-RC-IGBT) is proposed [...] Read more.

This paper explores the operation mechanism of the superjunction structure in RC-IGBTs based on carrier distribution and analyzes the advantages and challenges associated with its application in RC-IGBTs for the first time. A Partial Schottky Collector Superjunction Reverse Conduction IGBT (PSC-SJ-RC-IGBT) is proposed to address these issues. The new structure eliminates the snapback phenomenon. Furthermore, by leveraging the unipolar conduction of the Schottky diode and its fast turn-off characteristics, the proposed device significantly reduces the turn-off power consumption and reverse recovery charge. With medium pillar doping concentration, the turn-off loss of the PSC-SJ-RC-IGBT decreases by 54.1% compared to conventional superjunction RC-IGBT, while the reverse recovery charge is reduced by 52.6%. Full article

(This article belongs to the Special Issue Power Semiconductor Devices and Applications, 2nd Edition)

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12 pages, 3210 KiB

Open AccessArticle

A Two-Dimensional Computer-Aided Design Study of Unclamped Inductive Switching in an Improved 4H-SiC VDMOSFET

by Xinfeng Nie, Ying Wang, Chenghao Yu, Xinxing Fei, Jianqun Yang and Xingji Li

Micromachines 2024, 15(1), 35; https://doi.org/10.3390/mi15010035 - 23 Dec 2023

Viewed by 1210

Abstract

Due to its high thermal conductivity, high critical breakdown electric field, and high power, the silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) has been generally used in industry. In industrial applications, a common reliability problem in SiC MOSFET is avalanche failure. For applications [...] Read more.

Due to its high thermal conductivity, high critical breakdown electric field, and high power, the silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) has been generally used in industry. In industrial applications, a common reliability problem in SiC MOSFET is avalanche failure. For applications in an avalanche environment, an improved, vertical, double-diffused MOSFET (VDMOSFET) device has been proposed. In this article, an unclamped inductive switching (UIS) test circuit has been built using the Mixed-Mode simulator in the TCAD simulation software, and the simulation results for UIS are introduced for a proposed SiC-power VDMOSFET by using Sentaurus TCAD simulation software. The simulation results imply that the improved VDMOSFET has realized a better UIS performance compared with the conventional VDMOSFET with a buffer layer (B-VDMOSFET) in the same conditions. Meanwhile, at room temperature, the modified VDMOSFET has a smaller on-resistance (R_on,sp) than B-VDMOSFET. This study can provide a reference for SiC VDMOSFET in scenarios which have high avalanche reliability requirements. Full article

(This article belongs to the Special Issue Power Semiconductor Devices and Applications, 2nd Edition)

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22 pages, 11882 KiB

Open AccessArticle

Design and Implementation of an Online Efficiency-Optimized Multi-Functional Compensator for Wind Turbine Generators

by Chao-Tsung Ma and Feng-Wei Zhou

Micromachines 2023, 14(10), 1958; https://doi.org/10.3390/mi14101958 - 20 Oct 2023

Cited by 1 | Viewed by 1111

Abstract

In recent years, the penetration of wind power generation has been growing steadily to adapt to the modern trend of boosting renewable energy (RE)-based power generation. However, the dynamic power flow of wind turbine generators (WTGs) is unpredictable and can have a negative [...] Read more.

In recent years, the penetration of wind power generation has been growing steadily to adapt to the modern trend of boosting renewable energy (RE)-based power generation. However, the dynamic power flow of wind turbine generators (WTGs) is unpredictable and can have a negative impact on existing power grids. To solve this problem efficiently, this paper presents a multifunctional WTG intelligent compensator (WTGIC) for the advanced power management and compensation of power systems embedded with WTGs. The proposed WTGIC consists of a power semiconductor device (PSD)-based bidirectional three-phase inverter module and an energy storage unit (ESU). In order to reduce system costs and improve reliability, efficiency, and flexibility, various control functions and algorithms are integrated via a modularized all-digital control scheme. In this paper, the configuration of the proposed WTGIC is first introduced, and then the operating modes and related compensation and control functions are addressed. An online efficiency optimization algorithm is proposed, and the required controllers are designed and implemented. The designed functions of the proposed WTGIC include high-efficiency charging/discharging of the ESU, real-time power quality (PQ) compensation, and high-efficiency power smoothing of the WTGs. The feasibility and effectiveness of the proposed WTGIC are verified using case studies with simulations in the Powersim (PSIM) environment and the implementation of a small-scale hardware experimental system with TI’s digital signal processor (DSP) TI28335 as the main controller. Full article

(This article belongs to the Special Issue Power Semiconductor Devices and Applications, 2nd Edition)

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19 pages, 5995 KiB

Open AccessArticle

CS-GA-XGBoost-Based Model for a Radio-Frequency Power Amplifier under Different Temperatures

by Jiayi Wang and Shaohua Zhou

Micromachines 2023, 14(9), 1673; https://doi.org/10.3390/mi14091673 - 27 Aug 2023

Cited by 1 | Viewed by 1319

Abstract

Machine learning methods, such as support vector regression (SVR) and gradient boosting, have been introduced into the modeling of power amplifiers and achieved good results. Among various machine learning algorithms, XGBoost has been proven to obtain high-precision models faster with specific parameters. Hyperparameters [...] Read more.

Machine learning methods, such as support vector regression (SVR) and gradient boosting, have been introduced into the modeling of power amplifiers and achieved good results. Among various machine learning algorithms, XGBoost has been proven to obtain high-precision models faster with specific parameters. Hyperparameters have a significant impact on the model performance. A traditional grid search for hyperparameters is time-consuming and labor-intensive and may not find the optimal parameters. To solve the problem of parameter searching, improve modeling accuracy, and accelerate modeling speed, this paper proposes a PA modeling method based on CS-GA-XGBoost. The cuckoo search (CS)-genetic algorithm (GA) integrates GA’s crossover operator into CS, making full use of the strong global search ability of CS and the fast rate of convergence of GA so that the improved CS-GA can expand the size of the bird nest population and reduce the scope of the search, with a better optimization ability and faster rate of convergence. This paper validates the effectiveness of the proposed modeling method by using measured input and output data of 2.5-GHz-GaN class-E PA under different temperatures (−40 °C, 25 °C, and 125 °C) as examples. The experimental results show that compared to XGBoost, GA-XGBoost, and CS-XGBoost, the proposed CS-GA-XGBoost can improve the modeling accuracy by one order of magnitude or more and shorten the modeling time by one order of magnitude or more. In addition, compared with classic machine learning algorithms, including gradient boosting, random forest, and SVR, the proposed CS-GA-XGBoost can improve modeling accuracy by three orders of magnitude or more and shorten modeling time by two orders of magnitude, demonstrating the superiority of the algorithm in terms of modeling accuracy and speed. The CS-GA-XGBoost modeling method is expected to be introduced into the modeling of other devices/circuits in the radio-frequency/microwave field and achieve good results. Full article

(This article belongs to the Special Issue Power Semiconductor Devices and Applications, 2nd Edition)

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