Advanced Dielectric Resonator Antenna Technology for 5G and 6G Applications
Abstract
:1. Introduction
- Section 2 provides a comprehensive overview of compact off-chip DRAs and their applications in array configurations.
- Section 3 introduces the concept of on-chip DRAs, which serve as gain directors in high mmW bands.
- Section 4 reviews the state-of-the-art beam-steerable DRAs designed to operate mostly in mmW bands.
- Section 5 reviews the dual-band DRAs in shared aperture designs up to mmW bands.
2. Compact Off-Chip DRA and Array Designs toward Millimeter-Wave Frequencies
2.1. Co-Fabricated and In-Template DRAs
2.2. Compact Substrate-Integrated DRAs
3. mmW On-Chip DRAs
3.1. On-Chip Spherical Self-Aligning DRAs
3.2. On-Chip DRAs on BEOL
4. Beam-Steerable DRA Arrays
4.1. Wide-Beam DRAs
4.2. Pattern-Reconfigurable DRAs
5. Dual-Band DRAs up to the mmW Band
6. Discussion and Conclusions
Author Contributions
Funding
Conflicts of Interest
References
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DRA Type | Feed and Polarization | Technology | of DRA | and BW (GHz, %) | Volume of DRA () | Gain (dBi) | Rad. Eff. 7 (%) | Array and Spacing () | |
---|---|---|---|---|---|---|---|---|---|
[14] | R. DRA 1 | SIW 4, LP, CP 5 | 1-layer PCB | 6.15 | 30, 1 | 0.25 × 0.27 × 0.20 | 13.6 arr,M | N/A | 1 × 4 and 2 × 2, 0.85 |
[15] | R. DRA, | cavity backed, LP 6 | LTCC | 5.9 | 32.5, 47.1 | 0.37 × 0.45 × 0.17 | 11.4 arr,M | 70–85 t | 1 × 4, 0.4 |
[16] | R. DRA, | SIW, LP | 1-layer PCB | 3.55 | 28, 10 | 0.49 × 2.1 × 0.15 | 13.1 arr | ≥70 t | 1 × 8, 0.48 |
[17] | R. DRA rings, connected | slot, LP | glued on PCB | 20.8 | 26.8, 20 | 0.30 × 0.44 × 0.07 | ∼9.8 arr,M | 91 ele | 1 × 4, 0.64 |
[19] | R. DRA rings, connected | slot, LP | glued on PCB | 10.2 | 60, 13 | 0.99 × 1.1 × 0.25 | ∼21 arr,M | 88 arr | 4 × 4, 0.99, 1.1 |
[18] | C. DRA 2, connected | slot, LP | assemble 2 PCBs | 10.2 | 60, 24 | 0.30 × 0.3 × 0.127 | 16.5 arr,M | ≥71% | 4 × 4, 0.58 |
[32] | R. DRA stacked | SIW, LP | in-template, PCB | 10.2 + 2.2 | 67, 16.4 | 0.40 × 0.40 × 0.18 | 17.2 arr,M | 72.3 | 4 × 4, 0.67 |
[22] | R. DRA | slot, LP | in-template, lithography | 10 | 60, 12 | 0.24 × 0.24 × 0.12 | 10.5 arr,M | ≥90 | 2 × 2 |
[21] | R. DRA + artificial grid | SIW, LP | in-template, lithography | 22.4 eq | 60, 8 | 0.20 × 0.18 × 0.10 | 15.2/19.4 arr,M | 73 arr,M | 4 × 4/8 × 8 |
[23] | R. SIDRA + air vias + dielectric vias | slot, dual LP | multilayer PCB | 10.2 | 5.5, 35 | 0.61 × 0.61 × 0.09 | 6.84 M | 77 | |
[24] | R. SIDRA + air vias + dielectric vias | slot, LP | multilayer PCB | 10.2 | 9, 33 | 1.25 × 1.21 × 0.11 | 6–8.7 | ∼92 | |
[25] | R. SIDRA + air vias + dielectric vias | slot, CP | multilayer PCB | 10.2 | 6.8, 25.4 | 0.69 × 0.69 × 0.09 | 3.45–4.75 | ≥60 | |
[26] | R. SIDRA+ air vias + metal vias | slot, dual LP | multilayer PCB | 10.2 | 21.7, 24 | 0.60 × 0.60 × 0.10 | 6–8 | N/A | |
[27] | C. SIDRA + air vias and cavity + metal vias | slot, CP | multilayer PCB | 13.3 | 24, 35 | 1.05 × 1.05 × 0.12 | 6–8.15 M | ||
[28] | C. SIDRA + air vias + metal vias + strips | slot, LP | multilayer PCB | 13.3 | 28, 5 | 0.76 × 0.76 × 0.11 | ∼12.2 arr,M | 67 t | 2 × 2 |
[29] | C. SIDRA + air vias + metal vias | slot, CP | multilayer PCB | 10.2 | 60, 12 | 0.68 × 0.68 × / e | 9–12 arr,M | 70 M,arr | 2 × 2 |
R. SIDRA + SIGW 3 cavity | microstrip line, LP | multilayer PCB | 10.2 | 31, 12 | 0.29 × 0.48 × 0.09 | 6–7.85 | N/A | ||
[31] | R. SIDRA + SIGW 3 cavity | microstrip line, LP | multilayer PCB | 6.15 | 28, 13.8 | 0.38 × 0.19 × 0.112 | 13.94 arr | N/A | 1 × 8, 0.56 |
Year | DRA Design Feature and Feed Structure | Chip Technology | f0 (GHz) and FBW (%) | DRA Size () | Gain (dBi) | Rad. Eff. (%) | ||
---|---|---|---|---|---|---|---|---|
[44] | 2018 | spherical alumina DRA, self-aligns on cutout on BEOL | 10.1 | silicon-based | 105, 8 | D = 0.28 1 | 7–8.5 M | 60–80 |
[45] | 2020 | 10.7 | / | 180, 11 | D = 0.6 1 | 7.9 M | 80 | |
[46] | 2019 | spherical DRA + partially reflective superstructure (PRS) | 9.8 | / | 72, 5.6 | DRA D = 0.38, superstrate D = 3.68 1 | 7.9/17.8 wo/w,M | 70 |
10.1 | / | 103, 9.1 | 7.6/18.4 wo/w,M | 70–80 | ||||
[47] | 2012 | 3 stacked RDRAs, coupled meandered slot | 10, 2.4, 10 | 0.18 μm CMOS | 130, 11 | 0.8 × 0.9 × 0.66 | 4.7 M | 43 |
[48] | 2014 | RDRA in , mode, coupled slot | 10 | 0.18 μm CMOS | 135, 7 | 0.27 × 0.27 × 0.6–1 | 6.2–7.5 M | 46–42 |
RDRA in half mode | 10 | 0.18 μm CMOS | 135, 13 | 0.27 × 0.27 × 0.1 | 3.7 M | 62 | ||
[49] | 2017 | RDRA in mode, coupled slot | 10 | 0.18 μm CMOS | 135, 10 | 0.27 × 0.27 × 0.1 | 6.3/7 M,arr | / |
RDRA in mode, coupled slot | 10 | 0.18 μm CMOS | 135, 10 | 0.3 × 0.17 × 0.6 | 7/8.2 M,arr | / | ||
[50] | 2018 | RDRA, patch feed | / | 0.1 μm GaAs pHEMT | 270, 17 | 0.19 × 0.22 × 0.54 | 6.4 | 75 |
[51] | 2017 | silicon RDRA in mode, patch feed | 11.9 | 0.18 μm CMOS technology | 340, 7.3 | 0.22 × 0.22 × 0.55 | ∼7.9 | 74 |
[42] | 2015 | stacked alumina RDRA, patch feed | 9.8, 2.1 | 0.13 μm SiGe BiCMOS | 340, 12 | 0.6 × 0.6 × 0.46 | 8–10 M | 65–80 M |
[43] | 2022 | AMC backed quartz RDRA + diamond layer + lens, patch feed | 5.68, 3.75 | 1:35 nm mHEMT | 400, 25.6 | 0.67 × 0.67 × 0.6 wo | 27 M/7.8, D,wo/w | 50–66 |
DRA Type | Feed and Polarization | Beam Steer Method | of DRA | and BW (GHz, %) | Volume of DRA () | Array Broadside Gain (dBi) and Rad. Eff. (%) | Array and Spacing () | E, H, or D Plane Scan Range (±,°) | |
---|---|---|---|---|---|---|---|---|---|
[56] | CDRA + hemispherical DRA + metal cavity | LP | electro. scan. | 9.5 | 28, 10 | 0.44 × 0.44 × 0.09 | 22 arr,e, 80 | 8 × 8, 0.44 | 60, 60, 60 |
[57] | RDRA + parasitic strip walls | LP | electro. scan. | 9.5 | 5.5, 5.5 | 0.22 × 0.22 × 0.44 | 12.5 2, / | 1 × 8 and 8 × 8, 0.4 | 80, 75, / 3 |
[58] | RDRA + metasurface | LP | electro. scan. | 9.1 | 3.55, 12.8 | 0.33 × 0.22 × 0.09 | 9 4,M, 81 | 1 × 5 and 4 × 4, 0.4 | 60, 45, / |
[59] | CDRA stacked + outer ring | slot fed, LP | electro. scan. | 10, 3, and 3.4 | 10.7, 14.9 M | 0.23 × 0.23 × 0.41 | 13.9 arr,M, / | 1 × 9, 0.45 | /, 72, / |
[60] | RDRA + parasitic DR strips | LP/CP | electro. scan. | 45 and 69 | 10, 17 | 0.35 × 0.35 × 0.11 | 12.4 arr, / | 1 × 5, 0.5 | /, 45, / |
[61] | Ring RDRA + strip | LP | electro. scan. | 20.8 | 26.9, 19.5 | 0.3 × 0.46 × 0.09 | ≥9.3 arr,M, 89.6 | 1 × 4, 0.5 | /, 40, / |
[36] | CDRA + air vias + metal vias | DUAL LP | electro. scan. | 10.8 | 27.5, 15 | 0.2 × 0.2 × 0.09 | 12.6 Mobi, 95 | 2 × 1 × 4 Mobi, 0.5 | /, 28–138, / |
[16] | R. DRA + metasurface | LP | electro. scan. | 3.55 | 28, 10 | 0.49 × 2.1 × 0.15 | 13.1 arr, ≥70 t | 1 × 8, 0.48 | 0, 55, / |
[15] | SIW DRA | LP | electro. scan. | 5.9 | 32.5, 47.1 | 0.37 × 0.45 × 0.17 | 6–11.4 arr,M, 70–85 t | 1 × 4, 0.43 | /, 45, / |
[62] | RDRA + metasurface | LP | pattern-reconfig. 1 | 9.4 | 3.65, 14.1 | 0.28 × 0.28 × 0.11 | 10.5 M, 78.4 M | 1 × 5, 0.5 | /, 70, / M |
[63] | CDRA + metasurface | LP | pattern-reconfig. | 9.4 | 3.5, 12.8 | 0.33 × 0.33 × 0.09 | 14.8 arr,M, 77 M | 4 × 4, 0.46 | 60, 60, 75 M |
[64] | RDRA + ring-shape DRA | LP | pattern-reconfig. | 9.8 | 4.9, 16.8 M | 0.5 × 0.51 × 0.28 | 13 e, / | 1 × 4, 0.95 | 15–60, /, / |
[65] | RDRA + air gap | probe fed, LP | pattern-reconfig. | / | 3, 3.3 | 0.38 × 0.38 × / | 7.22 arr,M, / | 1 × 4, 0.5 | 0–81, /, / |
[70] | RDRA | ring and probe fed, LP | pattern-reconfig. | 9.8 | 7, 14 | 0.2 × 0.2 × / | 16.53 arr, 96 | 1 × 14, 0.46 | 80, /, / |
[66] | CDRA + diagonal strip | patch fed, LP | pattern-reconfig. | 6.45 | 28, 11 | 0.56 × 0.56 × / | 20.1 arr, 70 t | 8 × 4, 0.7, 0.56 | 20–30, 70, / |
Topology | Feed and Polarization | Technology | and BW | of DRA | DR Modes | Volume () | Gain (dBi) | Scan Angle | |
---|---|---|---|---|---|---|---|---|---|
[73] | DRA + patch | Shared slot, LP | SIDRA | 24, 3 | 10.2 | 6.32 | |||
Printed patch | 5.2, 2 | 0.36 × 0.36 × 0.027 | 3.93 | ||||||
[74] | DRA + printed strip | Shared slot, dual LP | DR in PCB template | 39, 12.56 | 45 | , | 6.4 | ±40° | |
Printed strip, stub | 28, 14.11 | 3.54 | 0.34 × 0.36 × 0.1 | 6.8 | ±50° | ||||
[75] | Multimode RDRA | Shared slot, LP | PCB + via | 38, 9.7 | 3.55 | 14.2 1 | |||
16, 35.3 | 0.32 × 0.32 × 0.2 | 10.6 1 | |||||||
[76] | Encapsulated DRA | Slots, LP | 3D printing | 30.5, 27 | 9 | 18 2 | ±32° | ||
3.6, 33 | 4 | 0.87 × 0.87 × 0.35 | 7.2 |
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Zhang, Y.; Ogurtsov, S.; Vasilev, V.; Kishk, A.A.; Caratelli, D. Advanced Dielectric Resonator Antenna Technology for 5G and 6G Applications. Sensors 2024, 24, 1413. https://doi.org/10.3390/s24051413
Zhang Y, Ogurtsov S, Vasilev V, Kishk AA, Caratelli D. Advanced Dielectric Resonator Antenna Technology for 5G and 6G Applications. Sensors. 2024; 24(5):1413. https://doi.org/10.3390/s24051413
Chicago/Turabian StyleZhang, Yingqi, Stanislav Ogurtsov, Vasilii Vasilev, Ahmed A. Kishk, and Diego Caratelli. 2024. "Advanced Dielectric Resonator Antenna Technology for 5G and 6G Applications" Sensors 24, no. 5: 1413. https://doi.org/10.3390/s24051413
APA StyleZhang, Y., Ogurtsov, S., Vasilev, V., Kishk, A. A., & Caratelli, D. (2024). Advanced Dielectric Resonator Antenna Technology for 5G and 6G Applications. Sensors, 24(5), 1413. https://doi.org/10.3390/s24051413