3.2. Weak AC-Grid Interface
As the ac-system impedance increases, the voltage magnitude at the connecting PCC in general will become more sensitive to power variations of the connected generation source. Furthermore, the injected power to the grid is expected to be significantly decreased. In our case, the SCR index is defined as:
where
is the short-circuit power capacity of the ac grid and
is the nominal power offered by the VSI.
Keeping in mind that
represents the total magnitude of a three-phase short circuit to the ground at the PCC, its value can only be theoretically assumed. In fact, the grid has to be modeled as a Thevenin-equivalent voltage source in order to obtain the value of
as:
where
is the voltage magnitude at the PCC and
is the Thevenin impedance, which in turn depends on the grid inductance
. Obviously, the inclusion of a long line between the PCC and the actual ac system further increases
, which has an apparent effect on decreasing the SCR value. In particular,
Figure 1 depicts the connection of a DER through a VSI interface to a PCC which is connected to the grid via a long line with resistance
and inductance
in series.
Completing, therefore, the dynamic model in the
d-
q reference frame at the ac-side by taking into account the line configuration, we obtain:
where
and
, and
and
represent the
d- and
q-axis components of the connecting line flowing currents and the infinite bus voltages respectively, while
stands for a parallel resistive local load set at the PCC, and
represents the capacitance at the same point, respectively.
It is worth noting that the system model given by Equations (1)–(3) and (8)–(11) represents a single DER connected at the PCC through a long line to a node with constant voltage. Nevertheless, it becomes apparent that the case of multiple DERs can be handled in a similar manner for each of them, if every DER is connected radially at the PCC and therefore the assumption of a single DER is adequate. Certainly, the case of more complex distribution networks with several DERs connected in arbitrary positions needs a more specific modeling, but in general, the PLL-driven scheme and the local controllers’ design can follow the same guidelines of analysis as that proposed in the next sections.
3.3. The Proposed Control and PLL Design
For the complete proposed design, the decentralized cascaded-mode control is adopted, which involves fast inner-loop current controllers, driven by slower outer-loop regulators. The proposed control scheme for the grid-tied inverter is included in
Figure 1.
The aim of two proposed cascaded controllers applied on the d- and q-duty-ratio input respectively, is twofold:
1. Firstly, to regulate the ac grid-side voltage magnitude at the desired level by introducing the following ac-voltage outer-loop PI regulator:
with the magnitude of the ac-bus voltage calculated as
.
To implement the cascaded-mode control structure, the following
d-axis inner-loop current controller is proposed:
where the command input is taken as
and it is determined by the output of the aforementioned outer-loop voltage controller, whereas
state is given by:
Obviously, Equation (14) represents the integrator term of the PI controller (Equation (13)), where now an additional damping term
has been inserted. As shown in
Section 3.5, the addition of the damping term is crucial to guarantee stable system performance. On the other hand, this modification does not affect the cascaded controller performance and it constitutes a very light change since it is implemented locally by feeding-back the inner-loop state
. This is a significantly simpler solution compared to the standard decoupling methods [
6], where the inserted feedback and feedforward terms are strongly dependent from the specific system structure, operating conditions and parameters.
All the
d-
q voltage and current components are provided by aligning the synchronously rotating
d-
q reference frame by a locally implemented PLL, as depicted in
Figure 1. Normally, in a strong ac-bus, the PLL mechanism eliminates the frequency difference between the grid’s actual angular frequency
and the angular frequency provided by the PLL circuit
, which is noted as:
and synchronizes its operation with the phase of the bus ac-voltages by zeroing-out one of the
d- or
q-axis voltage components (in our case the
d-axis voltage component). Therefore, the dynamics of the system with the PLL control in state-space is given as in reference [
26]:
with
where in steady-state conditions, the angular frequency of the PLL is equal to the one of the utility
after a transient period starting at an arbitrary
.
As one can easily see, in Equations (16) and (17), instead of using the varying original
, a virtual
has been used. As shown in
Figure 1, this is implemented by measuring the original bus voltage magnitude and amplifying it by
, in order to relax the voltage magnitude from its variations. As in steady-state,
equals to
, due to the outer-loop voltage regulator (Equation (12)), the PLL achieves to be aligned with the original
voltage component.
In
Figure 2, the PLL operation is explained. In the process of aligning the
q-axis reference voltage, it is initially observed that a small angle,
, appears between the
q-axis reference voltage and the
q-axis voltage at the PCC. Obviously, after a transient, both the
q-axis bus voltages will be aligned, while a
angle exists between the
q-axis voltage at the PCC and the
q-axis voltage at the infinite bus. Therefore, the grid voltage components become:
where
is the voltage magnitude of the infinite bus.
In this way, i.e., by using a constant virtual voltage magnitude, namely the
q-axis reference voltage, and simultaneously considering the original ac voltage angle, we can guarantee that the controlled system performance is not affected by the synchronizing process of the PLL without inserting any steady-state phase angle error, since we can follow the proof provided in Reference [
26].
2. Secondly, to regulate the dc-side voltage, we adopt a dc-voltage outer-loop controller also of a PI type. Specifically, the relevant voltage regulator is considered as:
The output
of Equation (21) is applied as a reference command input for the inner-loop current controller to provide the inverter switching duty-ratio
component, as:
with command input
and where:
Obviously, Equation (23) represents the integrator term of the PI controller (Equation (22)), where now the damping term has been inserted in a common way, as described in Equation (14).
It is noted that all the considered gains in all the above cases have been selected to be positive scalars. It is also mentioned that since the main control tasks, i.e., the ac- and dc-voltage regulation are executed by the outer-loop PI controllers, these are not affected by the added damping terms in the inner-loop controllers.
3.4. The Closed-Loop System
In this subsection, the dynamic model of the previously presented system is extended to include the fast inner-loop current controllers. This approach ensures that the dynamic behavior of the extended system can be properly examined in the sequel of the analysis, since the fast response of the current controllers have a significant impact on the overall performance of the system. On the other hand, the slower outer-loop voltage controllers do not necessarily have to be included in the analysis, given the fact that the time-scale separation principle has been considered for their design [
11]. In particular, by combining the open-loop system dynamic model as described by Equations (1)–(3) and (8)–(11) with the PI current controllers taken into account, the closed-loop system model takes the form of the following equations:
with state vector given as
, where it is defined:
, with
, as adopted in Reference [
27], an arbitrary constant with the gains
given as:
.
As mentioned in the previous subsection, and as is proven in reference [
26], the PLL dynamics are independent from the system states since after an initial error, the PLL output is locked very fast on the desired frequency
and therefore,
can be considered constant while the
θ dynamics do not need to be included in the analysis. Nevertheless, in a weak ac grid, significant frequency oscillations may appear. Then, it is important to quantify the maximum frequency disturbance that the PLL control can withstand without loss of synchronization. According to reference [
28], the angle
must be less than
during a disturbance, otherwise the operating point enters negative damping zones and loss of synchronization is very likely to occur. In order to evaluate an approximate maximum permitted deviation in frequency, we integrate Equation (15) by considering the maximum
:
. Then, after some simple manipulations, a conservative result can be expressed by the following inequality:
, where
is the frequency disturbance and
is the sufficiently small enough time that the PLL control takes to respond. As one can observe, the faster the PLL can respond, i.e., small
, the larger the disturbance it can withstand. For example, tuning the PLL in order to obtain a reasonable response time in the range of
, then it can withstand a maximum frequency disturbance lying in between
.
Coming back to system (24), one can observe in the first two equations, the terms
into the
equation and
into the
equation respectively, still exist, a fact that results in a fully independent scheme of the inner-loop current controllers from the system parameters. This is an alternative design in contrary to the standard ones proposed in Reference [
29], that include the decoupling terms
and
along with the PI part fed back in each voltage input
and
, respectively. The conventional scheme, except from the controller dependence from these terms, also results in nonlinear duty-ratio controls
and
since a division by
is needed. However, division by a state (in the present case by the
) is not an ideal option since, during transients, the varying values of
are transferred to the duty-ratio and may result even in very large input disturbances. The benefit of using the standard technique with the decoupling terms, that provides the possibility of a design based on the linearized system [
29] is clearly negated in view of these drawbacks.
In our case, the proposed controllers are fully independent from the system parameters, since no decoupling terms as those used in the standard technique, are considered to exist anymore in both the proposed inner-loop controllers. Furthermore, as shown by Equations (13) and (22), the inner-loop current controllers are of the familiar to the industrial engineers PI-linear type (plus a linear damping term), directly providing their output as the duty-ratio input signal of d- or q-component. Hence, a significant novelty of the controllers’ design has been introduced with the cost of a cumbersome nonlinear analysis, since nonlinear terms are involved into the first three equations of (24). Additionally, as explained in detail in the following stability analysis, the only constraint in our design is simply all the controllers’ gains to take positive values. As any positive gain value is adequate to render stability, it is evident that a kind of robustness is ensured.
3.5. Stability Analysis
In this subsection, the complete closed-loop model, as given by Equation (24), is considered, with a main objective to prove that the system is input-to-state stable (ISS) and sequentially, to establish system-state convergence to equilibrium.
The ISS concept [
30] has become a powerful tool for investigating nonlinear systems that operate under persistent external inputs. Hence, for the general system:
where
is piecewise continuous in
t and locally Lipschitz in
x and
u and the input
is a continuous, bounded function of
t for all
, the following Lemma can ensure that the ISS property holds true.
Lemma 1. [31] Suppose system (25) is continuously differentiable and globally Lipschitz in , uniformly in t. If the unforced system has a globally exponentially stable equilibrium point at the origin , then system is ISS. As Lemma 1 clearly suggests, the ISS property can be easily established by examining the unforced system for its exponential stability. To this end, by considering the closed-loop model of the system, the following Theorem is recalled from Reference [
31]:
Theorem 1. Let x = 0 be an equilibrium point for the unforced system (26) and there exist a continuously differentiable function V and non-decreasing functions , , , such that for all , , with time derivative, , then the origin x = 0 is globally exponentially stable (GES).
Proceeding with our analysis, for the closed-loop system, as given in Equation (24), the following positive definite Lyapunov function is proposed: .
The time derivative of
V is calculated as:
with matrix
R being a positive definite matrix of the following diagonal form:
, and
being the closed-loop system external input vector.
It is noticed that since the unforced system is an autonomous system of the form condition yields the current source to be neglected, i.e., and = 0, with .
Also, the selected Lyapunov function satisfies:
with:
Obviously, Equations (28) and (29) indicate that for all , conditions of Theorem 1 are satisfied (for w = 2). Thus, according to Theorem 1, the origin of the unforced closed-loop system is proven to be GES. Consequently, as implied by Lemma 1, the ISS property is directly established for the complete forced system. Since the ISS property is in fact equivalent to the bounded-input-bounded-state (BIBS) property, then for any bounded external input acting on the system, its states remain bounded, establishing, in this sense, a kind of robustness.
Now, in order to further proceed with the convergence to the nonzero equilibrium of the system, it is considered that the external inputs tend to piecewise constant values, and therefore, at any of their constant values, a desired equilibrium can be determined [
32]. Then, we recall Theorem 6 from Reference [
33], presented here as Theorem 2:
Theorem 2. For system , if the origin of the unforced system is exponentially stable and the function is continuously differentiable and globally Lipschitz in and , then and bounded, the trajectories of the enforced system converge to equilibrium: for a as , for some constant, where is the largest invariant set of , i.e., .
In general, by this result, it becomes clear that when multi equilibria exist, the convergence is guaranteed to the set involving all the equilibria. However, in our case, the valid equilibrium is ultimately a unique one, no matter how many equilibria the nonlinear system naturally has. The uniqueness of this stable equilibrium point is due to the action of the external ac- and dc-voltage controllers, which do not allow system states to reach any other steady-state equilibrium except for the one defined by the external command references. This constitutes one of the main advantages of applying cascaded control schemes. Particularly, in a dual-loop (cascaded) control scheme (inner- and outer-loop), the outer-loop controllers are responsible to execute the main control goals (in our case to regulate the ac and dc voltages in both sides of the converter). To that end, the proposed pure PI outer-loop controllers are certainly adequate to eliminate the error between the reference and the measured value of the dc and the ac voltage.
On the other hand, the inner-loop controllers act by feeding back the current states (the
d- or
q- component, respectively) that are directly influenced by the manipulated input. This causal relationship allows faster responses for the inner-loop controllers, enables to implement controllers even for the case where the system is non-minimum phase with respect to the controlled variables and keeps the impact on the outer-loop controller response relatively small [
23]. Therefore, the main requirement for the fast inner-loop controllers is to guarantee closed-loop stability, a fact fully satisfied by the proposed design.
Also, as indicated by the aforementioned analysis, any positive gain value can be used for both the inner-loop and outer-loop controllers’ gains, and this provides an excellent possibility of applying the best technique for the gain selection among many found in the literature [
34]. The significance of suitably tuning the controllers’ gains has been pointed out by many authors and other methods such as linear matrix inequalities (LMIs) or Fuzzy-based techniques [
35,
36] have been effectively proposed to synthesize the particular controllers. Specifically, since the damping terms of the inner-loop controllers are selected with small gain values, both the inner- and outer-loop controllers can be tuned as pure PI controllers. Keeping in mind that the inner-loop controllers should be much faster than the outer-loop ones, the following technique is adopted [
23]: Firstly, the inner-loop controller is tuned with the outer-loop controller in manual mode. Secondly, the outer-loop controller is tuned with the inner-loop controller in automatic mode. Thus, at each stage, any well-defined method for PI tuning can be used. In our case, since our system model is nonlinear while the PI controllers are linear, a combination of the Ziegler–Nichols (Z-N) method [
34] and the Good-Gain (G-G) method (which is actually a modification of the Ultimate-Gain method) is applied [
37]. As explained in detail in Reference [
23], the gain tuning based on the G-G method can be obtained working on the simulated system response or on the experimental one (as the Z-N method also does). It involves a sequence of steps wherein, firstly, the P-gain is tuned, and after the I-term gain, a correction design loop for the gains is performed, which in our case is combined with the conventional Z-N results. In the next section, the results obtained are based on this tuning method.
3.6. System Parameters and Experimental Setup
The complete system that includes the proposed control scheme is examined through extensive simulations. The simulated system parameters were set to , , , . The capacitance of the bank at the PCC is , while the resistance is chosen to be . The resistance and inductance of the ac line between the PCC and the ac grid were chosen to be and , respectively. The controller gains are selected as and . Also, it is chosen that , while the outer-loop controllers gains are selected to be: , and , . Finally, the dc and ac voltage reference values are set at and , respectively.
In order to further evaluate the performance of the system under the action of the deployed closed-loop control scheme, an experimental procedure is also established based on the complete system of
Figure 1. In particular, the experimental setup comprises a dc/dc boost converter representing a DER current source feeding a three-phase VSI. The VSI is connected through an RL filter to the PCC, which in turn is connected to the grid via an RL line. The setup as developed in the laboratory environment is illustrated in
Figure 3.
The proposed control scheme is implemented using a dSPACE DS1104 platform [
38], which is an ideal solution for fast and accurate prototyping of control designs. This particular system is based on a processor board, featuring a PowerPc 603e floating-point processor running at 250 MHz, slave-DSP system, several I/O ports, along with A/D and D/A channels. Furthermore, the real-time interface (RTI) [
39] for dSPACE systems provides the capability of directly linking MATLAB-Simulink control models to the DS1104 hardware, by generating and compiling real-time code. All the required analog measurements, i.e., voltages and currents, are provided to the A/D converter ports of the dSPACE board by using LV-25V voltage and LEM LTS 25-NP current sensors. The controller then suitably generates both a pulse-width-modulated signal of 5 kHz and a sinusoidal-pulse-width-modulated signal of 10 kHz, which are provided to the driving circuits of the dc/dc boost converter and the three-phase VSI, respectively.
The experimental setup parameters are listed in
Table 1. The controller gains are selected as
and
. Also, it is chosen
, while the outer-loop controllers gains are selected to be:
,
and
,
. The dc and ac voltage reference values are set at
and
, respectively.