Enhanced Boost Factor for Three-Level Quasi-Switched Boost T-Type Inverter

Abstract

A new modulation strategy has been introduced in this paper in order to enhance the boost factor for the three-level quasi-switched boost T-type inverter (3L-qSBT²I). Under this approach, the component rating of power devices is significantly decreased. Moreover, the use of a larger boost factor produces a smaller shoot-through current. This benefit leads to reducing the conduction loss significantly. Furthermore, the neutral voltage unbalance is also considered. The duty cycle of two active switches of a quasi-switched boost (qSB) network is redetermined based on actual capacitor voltages to recovery balance condition. Noted that the boost factor will not be affected by the proposed capacitor voltage balance strategy. The proposed method is taken into account to be compared with other previous studies. The operation principle and overall control strategy for this configuration are also detailed. The simulation and experiment are implemented with the help of PSIM software and laboratory prototype to demonstrate the accuracy of this strategy.

1. Introduction

Currently, a conventional three-level T-type inverter (3L-T²I) is applied for low voltage applications due to its advantages of low conduction loss due to not using extra diodes compared to neutral point clamped inverter (NPCI) configuration or producing better output quality compared to two-level inverter [1,2]. This topology is recently adopted for many applications, especially photovoltaic (PV) systems and motor drives, etc. [3,4,5]. Nevertheless, the traditional 3L-T²I produces a low value of AC output voltage in comparison to the input voltage of the inverter. Moreover, the conventional 3L-T²I cannot accept the shoot-through (ST) state during operation because of leading to a short circuit at the DC input source.

Nowadays, impedance-source inverters have been considered as a solution to deal with the drawbacks of conventional inverters [6,7,8]. By using some passive components such as diodes, capacitors, and inductors in Z-source (ZS) circuit, the ZS inverter (ZSI) can behave as a buck-boost inverter with ST immunity. During operation, the ST state is utilized to belong to traditional vectors of the inverter to enhance the output voltage. The result is that the reliability is significantly improved. According to these advantages, several applications based on ZSI were discussed for the motor drive system, micro-grid connection, and PV applications [9,10]. Many traditional multilevel inverter topologies were considered to incorporate with the ZS network, such as NPCI and 3L-T²I [11,12,13,14]. The works in [15,16] introduced a topology combining a single ZS network and 3L-T²I. To ensure a three-level voltage operation, this combination uses a split DC input source. The neutral point of this source is utilized to belong to of ZS circuit to feed to the three-level inverter circuit. This configuration must use one extra diode to guarantee the symmetry of the impedance network. Instead of using full-ST (FST) state, this method used upper-ST (UST) and lower-ST(LST) states to conform to the buck-boost characteristic, which is added within small vectors. In this strategy, the boost factor is equal to the traditional strategy in [8]. The work in [16] further proposed the neutral voltage balance strategy. However, this strategy required more dwell-time calculations and caused the boost factor effect.

To produce less component voltage rating and draw continuous input current, the quasi-Z-source (qZS) inverter (qZSI) has been presented in [17,18,19,20,21,22]. These topologies use the same components compared to ZSI, but these components were connected in another way. Like the ZS network, this type of impedance-source structure was considered to incorporate with the three-level inverter to provide multilevel characteristics [17,18,19,20,21,22]. In these approaches, two qZS circuits are connected to guarantee three-level operation at the output. However, the use of a large number of inductors and capacitors leads to increase volume and decrease power density of the inverter. Furthermore, buck-boost characteristics of the ZS/qZS inverters are only ensured by the ST duty ratio of the inverter branch, which decreases the flexibility of boost factor regulation. The literature [20] introduced the space-vector-modulation (SVM) method and the third harmonic injection scheme, which ensure the buck-boost operation by applying the UST and LST states. Similar to ZSI, these schemes required a split DC source to conduct UST and LST insertions. In [21,22], a novel SVM strategy was proposed to reduce the amplitude and the slew rate dv/dt of common-mode voltage (CMV). In this work, the neutral voltage unbalance problem was handled by adding one more extra small vector into the traditional switching sequence. However, the drew-time of additional small vectors is hardly determined. It produces the complexity of the calculation.

The quasi-switched boost (qSB) inverter (qSBI) was considered as an emerging topology that saves plenty of inductors and capacitors [23,24,25,26,27,28,29,30]. By installing one more active switch in the intermediate circuit, the boost factor of qSBI is so flexible to be controlled [16]. In this configuration, some advantages can be listed as high boost factor and voltage gain and good inductor current profile. These advantages lead to reducing voltage stresses on power devices and less capacitance requirement for passive components such as inductors and capacitors. The works of literature in [25,26,27,28,29,30] proposed the incorporation between qSB network and the multilevel inverter. In [25,26], the three-level NPCI was combined with two separated qSB networks. The 3L-T²I was considered to combine with this type of impedance-source network in [27,28,29,30]. In [27,28,29,30], the qSB network utilized only one inductor and one DC input source, which saves one inductor and a split DC source compared to [25]. These works also proposed a new pulse-width modulation (PWM) strategy based on the phase shift carrier method to provide some benefits such as high voltage gain [21,27], common-mode voltage elimination [28], the capability of operating in normal and open-circuit faults [29], and small component rating. Similar to other types of single-stage buck-boost inverter, this configuration also utilizes the FST state to obtain buck-boost voltage capability, which is inserted within a zero vector to not affect the other voltage vectors. The closed-loop control is employed for capacitor voltage balance, which requires a larger time interval for neutral voltage recovery. The work in [30] adopted a corresponding small vector to balance the neutral voltage. However, this way introduced more CMV amplitude, which is generated by small vectors.

In this paper, a new PWM method is introduced, which improves the boost factor as well as voltage gain of this configuration. The neutral voltage balance is also considered in this paper. Unlike the methods in [16,22,30], where the neutral-voltage balance is ensured by corresponding small vectors of the inverter side, the active switches of the impedance-source network are utilized to balance neutral voltage. The duty cycle difference of these switches is determined based on actual capacitor voltages. This method brings benefits of reducing balancing recovery time and calculation complexity compared to [16,22,27]. The duty cycle of these switches and modulation index are considered to adjust the output voltage of the impedance-source circuit and AC output voltage. The operation modes, as well as the mathematical analysis, will be presented in this paper. Some simulation and experiment setups are used to confirm the accuracy of the proposed modulation method. The rest of this paper consists of four sections as follows. Section 2 introduces the operation of the inverter and proposed PWM strategy. Section 3 presents a neutral voltage balancing scheme. In Section 4, a comparison study has been conducted to highlight the contribution of this scheme. In Section 5, the simulation and experimental results have been presented to confirm the accuracy of the introduced method. Section 6 presents a conclusion.

2. Proposed PWM Scheme for 3L-qSBT²I

The 3L-qSBT²I is established by an impedance-source network and a 3L-T²I, as observed in Figure 1. The impedance-source network is constructed by two switches S₁ and S_2, four diodes D₁, D₂, D₃, and D₄, two capacitors C₁ and C₂, and one inductor L_B. The outputs of the intermediate circuit are “P”, “O”, and “N”, which are used to ensure the three-level operation of the inverter. The three-phase resistive load is adopted to confirm the operation of the inverter with the proposed scheme, which is fed through a three-phase LC filter to guarantee the sinusoidal waveform of output load voltage with a low THD value, as depicted in Figure 1. The control scheme of this configuration is detailed in the rest of this section. The operating modes, steady-state analysis, and parameter selection are also presented.

2.1. PWM Signal Generation

The control method for the 3L-qSBT²I is based on a phase-shift sinusoidal PWM scheme. The PWM control signal generation is divided into two cases: (1) inverter side PWM generation and (2) impedance-source switch PWM generation. For the inverter side, the six reference sinusoidal signals (±v_a, ±v_b, and ±v_c) are compared with a high-frequency triangle signal (V_tri1) to generate control signals for the inverter switches. Figure 2 shows the control signal generation for switches of phase A. In detail, switch S_1A is turned on when −v_a < V_tri1 < +v_a, switch S_3A is triggered on when +v_a < V_tri1 < −v_a, and switch S_2A is turned on when switches S_1A and S_3A are off. Signals V_ST and −V_ST are used to create the ST signal denoted by yellow highlight in Figure 2. This ST state is generated by turned on all switches on the inverter side. In order not to affect the output voltage, the V_ST must not be smaller than the peak value of reference signals.

For the impedance source side, the triangle signal (V_tri2) is used, which is shifted 90 degrees compared to V_tri1 to create the control signals for the active switches of the impedance-source network [27]. Signals V_ST and −V_ST are also used with V_tri2 to generate the ST signal of the intermediate network, which is denoted by green highlight, as shown in Figure 2. Furthermore, two control signals, V_con1 and V_con2, are further used to enhance the duty ratio of S₁ and S₂, as illustrated in Figure 2.

2.2. Operating Modes

Based on the PWM strategy presented in Figure 2, the inverter can be operated under two modes which are ST and non-ST (NST) modes. These modes are divided into five modes, which are ST mode, NST mode 1, NST mode 2, NST mode 3, and NST mode 4, as observed in Figure 3. To simplify, in non-ST modes, the inverter side is considered a current source, i_O. The on switches and forwarded diodes are shown in

Table 1. On/Off states of 3L-qSBT²I switches and diodes (X = A, B, C).

Mode	ON Switches	ON Diodes	VXO
NST mode 1	S1	D2, D3, D4	+VPN/2, 0 or −VPN/2
NST mode 2	S2	D1, D2, D3	+VPN/2, 0 or −VPN/2
NST mode 3	S1, S2	D2, D3	+VPN/2, 0 or −VPN/2
NST mode 4	S1X	D1, D2, D3, D4	+VPN/2
	S2X		0
	S3X		−VPN/2
ST mode	S1, S2, S1X, S2X, S3X		0

.

In ST mode, both switches S₁ and S₂ of the qSB circuit and all switches of inverter side are turned on at the same time. The result is that input inductor L_B is stored energy from the input source and C₁ and C₂ capacitors, as shown in Figure 3a. Conversely, methods in [27,30] only turned on all switches of inverter side, which decrease energy stored in the inductor and boost factor. The voltage across inductor L_B and current across two capacitors are expressed as

$$\{\begin{array}{l}{L}_B\frac{d{i}_{LB}}{dt}=V_g+V_{C1}+V_{C2}\\ C_1\frac{d{v}_{C1}}{dt}=C_2\frac{d{v}_{C2}}{dt}=-i_{LB}\end{array}$$

(1)

In NST mode 1 and NST mode 2, as shown in Figure 3b,c, capacitors C₁ and C₂ are respectively charged from the DC input source and the energy of inductor L_B. The following equations are obtained as

$$\{\begin{array}{l}{L}_B\frac{d{i}_{LB}}{dt}=V_g-V_{C2}\\ C_1\frac{d{v}_{C1}}{dt}=-i_O, C_2\frac{d{v}_{C2}}{dt}=i_{LB}-i_O\end{array}$$

(2)

$$\{\begin{array}{l}{L}_B\frac{d{i}_{LB}}{dt}=V_g-V_{C1}\\ C_1\frac{d{v}_{C1}}{dt}=i_{LB}-i_O, C_2\frac{d{v}_{C2}}{dt}=-i_O\end{array}$$

(3)

where i_O is the equivalent output current.

In NST mode 3, as illustrated in Figure 3d, the inductor L_B is stored energy from the DC input power supply, whereas two capacitors, C₁ and C₂, transfer energy to the load. The inductor voltage and capacitor currents are expressed as

$$\{\begin{array}{l}{L}_B\frac{d{i}_{LB}}{dt}=V_g\\ C_1\frac{d{v}_{C1}}{dt}=C_2\frac{d{v}_{C2}}{dt}=-i_O\end{array}$$

(4)

NST mode 4 is shown in Figure 3e, the lower capacitor and upper capacitor are further stored energy in NST modes 1 and 2. In these modes, the voltage across the input inductor and capacitor currents are calculated as

$$\{\begin{array}{l}{L}_B\frac{d{i}_{LB}}{dt}=V_g-V_{C1}-V_{C2}\\ C_1\frac{d{v}_{C1}}{dt}=C_2\frac{d{v}_{C2}}{dt}=i_{LB}-i_O\end{array}$$

(5)

2.3. Steady-State Analysis

The key waveform of inductor current i_LB and capacitor voltages V_C1 and V_C2 are depicted in Figure 4. Considering one switching period, the time intervals of ST state is D_ST.T. The time interval of NST mode 3 is also D_ST.T. The total time interval of NST mode 1 and NST mode 2 is (D₀ − D_ST)T. The rest time of switching period is (1 − D₀ − D_ST)T, which is the time interval of NST mode 4. The average values of inductor voltage (${\overline{V}}_{LB}$) and capacitor currents (${\overline{I}}_{C1}$, ${\overline{I}}_{C2}$) are calculated as in Equation (6). Noted that the following equations are achieved by considering V_C1 = V_C2.

$$\{\begin{array}{l}{\overline{V}}_L=[\left(V_g+2V_{C1}\right)D_{ST}T+\left(V_g-V_{C1}\right)\left(D_0-D_{ST}\right)T\\ +V_g{D}_{ST}T+\left(V_g-2V_{C1}\right)\left(1-D_0-D_{ST}\right)T]/T\\ {\overline{I}}_{C1}={\overline{I}}_{C2}=[-i_{LB}{D}_{ST}T-i_O\left(D_0-D_{ST}\right)T/2+\left(i_{LB}-i_O\right)\left(D_0-D_{ST}\right)T/2\\ -i_O{D}_{ST}T+\left(i_{LB}-i_O\right)\left(1-D_0-D_{ST}\right)T]/T\end{array}$$

(6)

In steady-state, these average values are equal to zero, thus the capacitor voltages and average value of inductor current can be expressed as:

$$\{\begin{array}{l}{V}_{C1}=V_{C2}=\frac{V_g}{2-5D_{ST}-D_0}\\ I_{LB}=2i_O\frac{1-D_{ST}}{2-5D_{ST}-D_0}\end{array}$$

(7)

The max value of V_PN voltage is identified by summing of two capacitor voltages and expressed as

$$V_{PN}=V_{C1}+V_{C2}=\frac{2V_g}{2-5D_{ST}-D_0}$$

(8)

The boost factor is defined as

$$B=\frac{V_{PN}}{V_g}=\frac{2}{2-5D_{ST}-D_0}$$

(9)

The first-order of output load voltage is identified as

$$V_{x,peak}=1.15M{V}_{PN}/2=\frac{1.15M{V}_g}{2-5D_{ST}-D_0}$$

(10)

The voltage gain, G, is calculated as

$$G=\frac{V_{x,peak}}{V_g/2}=\frac{2·1.15M}{2-5D_{ST}-D_0}$$

(11)

The relationship between two coefficients, D_ST and D₀, is defined as

$$D_{ST}\le D_0\le 1-D_{ST}$$

(12)

From Equation (12), by adopting D_ST and 1 − D_ST for the coefficient D₀, the minimum and maximum voltage gain is identified by the following equation, noting that the value (1 − M) is employed for D_ST

$$\{\begin{array}{l}{G}_{\min }=1.15M/(3M-2)\\ G_{\max }=2·1.15M/(6M-5)\end{array}$$

(13)

2.4. Parameter Selection

The inductor current ripple (∆i_LB), illustrated in Figure 4, is calculated with the help of Equation (1) as

$$\Delta i_{LB}=\frac{1}{2L_B{f}_s}{V}_g{D}_{ST}\left(1+\frac{2}{2-5D_{ST}-D_0}\right)$$

(14)

where f_s is the switching frequency.

Inductance, L_B, is selected in term of ∆i_LB/i_LB ≤ %x as

$$L_B\ge \frac{\mu }{2P_O\%x{f}_s}{V}_g^2{D}_{ST}\left(1+\frac{2}{2-5D_{ST}-D_0}\right)$$

(15)

where %x, µ, and P_O are the maximum percentage of inductor current ripple, the inverter efficiency, and the output power.

The peak-to-peak value of capacitor voltages, V_C1 and V_C2, illustrated in Figure 4, is calculated as

$$\Delta v_{C1}=\Delta v_{C2}=\frac{1}{2C{f}_s}{D}_0{i}_O$$

(16)

The selection of capacitors, C₁ and C₂, is conducted in terms of ∆v_C/V_C ≤ %y as follows

$$C_1=C_2\ge \frac{1}{4\%y{f}_s}{D}_0\frac{P_O{(2-5D_{ST}-D_0)}^2}{\mu V_g^2(1-D_{ST})}$$

(17)

where %y is the maximum percentage of capacitor voltage ripple.

The voltage stresses of impedance switches and diodes are the same as capacitor voltage. The max currents of switches and diodes of the qSB circuit are equal to the max value of the current across the inductor (i_LB,peak), which is calculated as

$$i_{LB,peak}=\frac{\mu P_O}{V_g}+\frac{1}{4L_B{f}_s}{V}_g{D}_{ST}\left(1+\frac{2}{2-5D_{ST}-D_0}\right)$$

(18)

The current stresses of 3L-T²I switches are selected as

$$\{\begin{array}{lll}{I}_{Sxy}=i_O,& \mathrm{when}& 13D_{ST}+3D_0\le 4\\ I_{Sxy}=i_{LB}/3,& \mathrm{when}& 13D_{ST}+3D_0>4\end{array}$$

(19)

where S_xy (x = 1, 2, 3; y = A, B, C) is the inverter side switch. The voltage across S_1X and S_3X is the same as the DC-link voltage, whereas it is half of the capacitor voltage for bidirectional switches.

3. Proposed Capacitor Voltage Balance Scheme and DC-Link Voltage Control

As illustrated in Figure 3b, in NST mode 1, the capacitor C₁ is discharged, whereas the capacitor C₂ is stored energy from the input DC source and the input inductor L_B. Therefore, in this mode, the voltage across C₁ is reduced, while C₂ voltage is raised. As opposed to NST mode 1, the C₁ voltage is raised, while the C₂ voltage is reduced, in NST mode 2, as illustrated in Figure 3c. Noted that these modes generate the same inductor voltage, V_LB = V_g − V_C, in terms of achieving a small difference between two capacitor voltages. Therefore, the boost factor is not much affected when replacing the NST mode 1 to NST mode 2, and vice versa.

To achieve a balancing condition, the proposed method replaces the NST mode 2 with NST mode 1 when V_C1 > V_C2. Conversely, NST mode 2 is utilized instead of NST mode 1 when V_C2 > V_C1, as presented in Figure 5. The S₁ and S₂ pulses are responsible for doing this work, which is detailed as follows. First, the traditional pulses of S₁ and S₂ are generated by using the V_tri2, ±V_ST, and ±V_con, as shown in Figure 5. Then, V_C1 and V_C2 are considered to generate the final pulses of S₁ and S₂. Accordingly, the duty ratio of S₂ is enhanced when V_C1 > V_C2. In contrast, the pulse of switch S₁ is enhanced when V_C2 > V_C1.

In order to detail this strategy, the difference between the two capacitor voltages is defined as

$$v_{dif}=V_{C1}-V_{C2}$$

(20)

where:

v_dif—the difference voltage between V_C1 and V_C2.

The total time offset, which is used to replace the NST mode 1 with NST mode 2 and vice versa, is identified as

$$\Delta t=\alpha t_{NST1}=\alpha t_{NST2}=\alpha (D_0-D_{ST})T/2$$

(21)

where:

∆t—the time offset between NST mode 1 and NST mode 2 in one switching period;

t_NST1 and t_NST2—the traditional time intervals of the NST mode 1 and NST mode 2, respectively:

α—is the offset duty ratio (0 < α ≤ 1).

The capacitor voltage balance strategy is analyzed in two cases that depend on the sign of v_dif.

In case 1, the sign of v_dif is positive. To achieve capacitor voltage balance, in each switching period, the total time of the NST1 and NST2 can be redefined as

$$\{\begin{array}{l}{t^{\prime }}_{NST1}=t_{NST1}+\Delta t=(1+\alpha )(D_0-D_{ST})T/2\\ {t^{\prime }}_{NST2}=t_{NST2}-\Delta t=(1-\alpha )(D_0-D_{ST})T/2\end{array}$$

(22)

where ${t^{\prime }}_{NST1}$ and ${t^{\prime }}_{NST2}$ are the redefined time interval of NST mode 1 and NST mode 2 in one switching period.

In case 2, the sign of v_dif is negative. To obtain capacitor voltage balance, in each switching period, the total time of NST mode 1 and NST mode 2 can be redefined as

$$\{\begin{array}{l}{t^{\prime }}_{NST1}=t_{NST1}-\Delta t=(1-\alpha )(D_0-D_{ST})T/2\\ {t^{\prime }}_{NST2}=t_{NST2}+\Delta t=(1+\alpha )(D_0-D_{ST})T/2\end{array}$$

(23)

Noted that the larger value of α leads to the faster neutral voltage balance speed. Moreover, having a fixed difference time ∆t between on-times of switches S₁ and S₂ makes this scheme easier to be employed than the method in [27]. As mentioned above, in this method, the operation of the inverter side is maintained, and the replacement of NST modes 1 and 2 produces the same voltage across the boost inductor. Therefore, this work does not affect the boost factor and voltage gain.

The control block diagram for the inverter is presented in Figure 6. In this figure, the controller consists of two separated parts, the DC-link voltage and AC output voltage regulations. From Equation (8), V_PN can be regulated through two coefficients, D_ST and D₀. Like [27], this scheme also fixes the value D_ST based on the DC source range. The result is that V_PN is controlled through coefficient D₀. Based on Equation (10), the AC output voltage control is achieved by adjusting capacitor voltage and modulation index M. However, when V_PN regulation is obtained, the capacitor voltage is fixed at half of DC-link voltage V_PN/2. Therefore, the AC voltage regulation is obtained by selecting the corresponding value of M.

For the DC-link voltage regulation, the actual value of V_PN is obtained by totaling V_C1 and V_C2. The difference between V_PN and the desired DC-link voltage, V_PN,ref, is minimized by applying the PI controller. The coefficient D₀ is reached by limiting the output of the PI controller by (12).

For the AC output voltage regulation, the actual output voltages (v_A, v_B, v_C) are utilized to calculate the actual V_x,peak. The abc/αβ transformation is used to obtain this work, as shown in Figure 6. In this scenario, the PI controller is also considered to generate the modulation index M, noted that modulation index M is limited as (1 − D_ST).

After calculating three coefficients M, D_ST, and D₀, the proposed scheme can generate the control signals of inverter switches similar to the conventional scheme. Noted that the time intervals of NST mode 1 and NST mode 2 have been adjusted, as mentioned above, to obtain neutral voltage balance.

4. Comparative Study

In Section 4, the superior of the proposed method is demonstrated by comparing it to other single-stage inverters and schemes. The PWM strategies of 3L-qSBI in [27,30] are considered to make the comparison with the proposed method. The overview of boost factor, voltage gain, etc., comparison can be observed in

Table 2. Overall comparison study of the proposed method and strategies in [27,30] for 3L-qSBT²I.

	Strategy in [27]	Strategy in [30]	Proposed Method
Max ST duty ratio, DST	1 − M	2(1 − M)	1 − M
Boost factor, B	2/(3 − 2DST − D0)	2/(3 − 2DST − D0)	2/(3 − 5DST − D0)
Voltage gain, G	1.15·MB	1.15·MB	1.15·MB
Capacitor voltage rating, Vc/Vdc	1/(3 − 2DST − D0)	1/(3 − 2DST − D0)	1/(3 − 5DST − D0)
Diode voltage rating, VD/Vdc	1/(3 − 2DST − D0)	1/(3 − 2DST − D0)	1/(3 − 5DST − D0)
Switch voltage rating, VS/Vdc	1/(3 – 2DST – D0)	1/(3 – 2DST – D0)	1/(3 − 5DST − D0)

and Figure 7. In literature [27,30], the comparison between the qSBI, ZSI, and qZSI has been already conducted. It proved that the PWM method in [27,30] provides the highest boost factor and lowest component rating over other single-stage inverters. To simplify, only the PWM method in [27,30] is considered in comparison to the proposed method. It should be noted that the method in [27] is implemented with a third harmonic injection scheme instead of the sinusoidal scheme. This change increases the voltage gain of the method [27] to 1.15 times and does not affect the operation of the inverter. To achieve the highest performance, the D_ST is set to (1 − M) for the proposed method and the method in [27]. For the method in [30], the D_ST is set to 2(1 − M). In these methods, both the maximum boost and minimum boost schemes are investigated. The max boost control is achieved by setting D₀ to (1 − D_ST), and the min boost control is obtained by applying D_ST to D₀.

As shown in Figure 7a, when applying the same ST duty ratio, the boost factors, B, of the methods in [27,30] are the same, whereas the proposed method provides the largest boost factor. In voltage gain comparison, the proposed method and the method in [30] are the same, which is larger than that of the method in [27], for the same modulation index, M, as observed in Figure 7b. Due to having a larger boost factor, the proposed method needs a smaller D_ST than that of the methods in [27,30] for the same voltage gain. For example, when applying max boost control, if the proposed method needs the value k for D_ST to produce voltage G, the value of D_ST for the methods in [27,30] must be (1 + 2k)/(3k) and 2k, respectively. Noted that the most conduction loss of the single-stage inverter is mostly produced in ST mode, thus having smaller D_ST makes the proposed method produce less conduction loss than [27,30].

The capacitor voltage rating comparison is illustrated in Figure 7c. It proves that the proposed scheme has smaller voltage stress on the capacitor compared to the method in [27]. As mentioned in Section 4, the voltage stress on impedance-source switches and diodes are the same as capacitor voltage, while voltage stresses of upper and lower switches of inverter side S_1X, S_3X (X = A, B, C) are twice the capacitor voltage and that is half of the capacitor voltage for bidirectional switches. Therefore, the reduction of capacitor voltage stress causes a reduction of component rating of switches, as presented in Figure 7d.

In summary, the proposed method has produced the largest boost factor and voltage gain over other single-stage three-level buck-boost inverters such as ZSI and qSBIs. These advantages can cause capacitor voltage rating and semiconductor voltage rating reduction. Moreover, the largest boost factor can lead to reducing the conduction loss, which increases the overall efficiency of the inverter.

5. Simulation and Experimental Verifications

5.1. Simulation Results

With the help of PSIM simulation software, the simulation is conducted to validate the operation of the inverter under the proposed method. The simulation parameters are listed in

Table 3. Simulation and experiment parameters.

Parameter/Components		Values
Input voltage	Vg	70 V ÷ 200 V
Output load voltage	Vx,RMS	110 VRMS
Output frequency	fo	50 Hz
Switching frequency	fs	10 kHz
Extra duty ratio	D0	0.15 ÷ 0.85
ST duty ratio	DST	0.15
Modulation index	M	0.76
Boost inductors	LB	3 mH/20 A
Capacitors	C1 = C2	2200 μF/400 V
LC filter	Lf and Cf	3 mH and 10 μF
Resistor load	R	56 Ω

. Both maximum and minimum boost factor control methods are validated with DC input range from 70 V to 200 V. In both cases, M and D_ST are set as 0.76 and 0.15, respectively. The extra duty ratio, D₀, of switches S₁ and S₂ is set to 0.15 and 0.85 to achieve the min and max boost factors, respectively. With these control parameters, the AC output load voltage is maintained at 110 V_RMS. The simulation results for both cases are shown in Figure 8 and Figure 9.

In both cases, the voltages on capacitors C₁ and C₂ are boosted to 180 V, as illustrated in Figure 8a and Figure 9a. These capacitor voltages are also the voltage stresses of switches S₁ and S₂, as shown in Figure 8b and Figure 9b. The peak value of V_PN is 360 V, as illustrated in Figure 8b and Figure 9b. The maximum value inductor current ripple is approximately 1.5 A and 1 A for the cases of 200 V input voltage and 70 V input voltage, respectively. These values are obtained in ST mode, which is represented by the zero value of DC-link voltage, as presented in Figure 8b and Figure 9b. The inductor current, I_LB, is also increased in NST 3, where S₁ and S₂ are turned on simultaneously. However, it is not increased faster than that of ST mode. The average inductor current is 3.4 A and 9 A for min boost and max boost control schemes, respectively. The waveform of V_AB is varied from −360 V and 360 V, as shown in Figure 8a and Figure 9a. The THD value of V_AB is 66%. The output load current is measured as 1.95 A_RMS, and its THD value is 0.56% for both cases.

The comparison of CMV, V_GO, between the proposed scheme and strategies in [27] and [30] is shown in Figure 10. The max boost control of methods in [27,30] is applied in the simulation. The method in [30] has the largest peak-to-peak CMV value of 200 V. It can be explained by using small vectors that generate a large value of CMV in [30]. The peak-to-peak CMV values of the scheme in [27] and the proposed PWM strategy are 130 V and 120 V, respectively. The RMS CMV values of the proposed method and methods in [27,30] are 34.8 V_RMS, 36.5 V_RMS, and 56.9 V_RMS, respectively. It is proved that the proposed PWM strategy produces the smallest CMV.

5.2. Experimental Results

The effectiveness of the proposed PWM strategy is also validated by experiments that are obtained through a laboratory prototype, as observed in Figure 11. The parameters used for experimental verification are also the same as simulation. The IGBTs FGL40N150 are used for the S_1X and S_3X of the inverter leg as well as the active switches of the intermediate network (S₁ and S₂). The isolated voltage sensors based on LEM LV20-P sensor are used to detect the capacitor and output load voltages. The experimental results are presented in Figure 12 and Figure 13.

For the case of a 200 V DC input source, as shown in Figure 12, the V_C1 and V_C2 are measured as 163 V and 170 V, respectively, as illustrated in Figure 12a. These capacitor voltages are also the voltage stresses of switches S₁ and S₂, which are 163 V and 170 V, respectively, as presented in Figure 12b. Furthermore, the max value of V_PN is determined as 333 V, as shown in Figure 12b. The NST mode 3 can be determined by observing the value zero of both switch S₁ and S₂ voltages, while the ST mode can be identified by observing the value zero of DC-link voltage. The inductor current is increased in both NST mode 3 and ST mode, as shown in Figure 12b. However, in ST mode, the inductor current increment is faster than that of NST mode 3 because the voltage across the inductor is larger than that in NST mode 3, as demonstrated in Equations (1) and (4). Inductor current ripple is measured around 1.5 A. The average value of i_LB is measured as 3.5 A, as presented in Figure 12a. The variation of V_AB is from −V_PN to +V_PN, as illustrated in Figure 12c. The output load current is measured as 1.85 A_RMS, and its waveform is sinusoidal. The FFT analysis for V_AB can be seen in Figure 12c. The first-order harmonic is also the maximum value, which is 190 V. The THD values of V_AB and output load current I_A are 80.5% and 2.51%.

When applying 70 V DC input source, the capacitor C₁ and C₂ voltages are 153 V and 159 V, when the coefficient D₀ is 0.85. These voltages generate 312 V of DC-link voltage, as illustrated in Figure 13b. The inductor current ripple is approximately 1.1 A, as shown in Figure 13b, and its average value is 10.4 A, as shown in Figure 13a. The output load current is 1.71 A_RMS. Figure 13c presents the FFT spectrum of V_AB, where the peak-to-peak value is 180 V at the first-order harmonic. The THD values of V_AB and I_A are 82.6% and 2.55%, respectively.

The capacitor voltage balance scheme and the closed-loop control implementation for the proposed method have been conducted. The results are shown in Figure 14 and Figure 15. The neutral voltage control is implemented in two cases: (1) the difference voltage between these capacitors v_dif is positive, and (2) the difference voltage between these capacitors v_dif is negative. In both cases, the neutral voltage balance condition is recovered after approximately 20 ms, as shown in Figure 14a,b. These results are conducted with the coefficient α of 0.3.

The input voltage is regulated to increase from 120 V to 160 V and decrease from 160 V to 120 V to validate the closed-loop control. In both cases, the V_PN is maintained at 360 V, which can be seen from Figure 15a,b. The output load voltage is kept at 110 V_RMS without DC input voltage variation, as presented in Figure 15c,d. In this work, the ST duty ratio D_ST is kept at 0.15. The modulation index is used to regulate the output load voltage and is limited to 0.85. The coefficient D₀ is utilized to control DC-link voltage, and its range is from 0.15 to 0.85.

6. Conclusions

This paper has introduced a PWM method for the 3L-qSBT²I based on a third harmonic injection scheme. By applying this method, many benefits have been obtained, such as high boost factor, high voltage gain, and less voltage rating on impedance-source network devices. These advantages have been validated through some investigations, which were conducted belonging to previous publications. The details of relevant equations and designed parameter selection have been presented. Furthermore, this paper also considered the capacitor voltage unbalance problem. The time interval of NST mode, which is generated by triggering only one switch of the qSB network, has been recalculated based on the actual capacitor voltages to provide neutral voltage balance characteristics. The output voltage and DC-link voltage have been controlled by using PI controllers. The extra duty cycle of two active switches of the qSB network was adopted to regulate DC-link voltage, whereas the modulation index has been utilized to regulate the AC output voltage. The accuracy of this scheme has been validated by simulation and experimental results. With some benefits listed, such as buck-boost operation, reduced conduction loss, the low voltage stress on devices, and an easy capacitor voltage balance scheme, the 3L-qSBT²I under the proposed method is suitable for PV applications where a low DC input voltage needs to be converted to a high AC output voltage with high efficiency and output quality.