Comparisons on Different Innovative Cascode GaN HEMT E-Mode Power Modules and Their Efficiencies on the Flyback Converter

Abstract

The conventional cascode structure for driving depletion-mode (D-mode) gallium nitride (GaN) high electron mobility transistors (HEMTs) raises reliability concerns. This is because of the possibility of the gate to source voltage of the GaN HEMT surging to a negative voltage during the turn off transition. The existing solutions for this problem in the literature produce additional drawbacks such as reducing the switching frequency or introducing many additional components. These drawbacks may outweigh the advantages of using a GaN HEMT over its silicon (Si) alternative. This paper proposes two innovative gate drive circuits for D-mode GaN HEMTs—namely the GaN-switching based cascode GaN HEMT and the modified GaN-switching based cascode GaN HEMT. In these schemes, the Si MOSFET in series with the D-mode GaN HEMT is always turned on during regular operation. The GaN HEMT is then switched on and off by using a charge pump based circuit and a conventional gate driver. Since the GaN HEMT is driven independently, the highly negative gate-to-source voltage surge during turn off is avoided, and in addition, high switching frequency operation is made possible. Only two diodes and one capacitor are used in each of the schemes. The application of the proposed circuits is experimentally demonstrated in a high voltage flyback converter, where more than 96% efficiency is obtained for 60 W output load.

1. Introduction

Gallium nitride (GaN) high electron mobility transistors (HEMT) are a new disruptive technology that has the potential to change the power electronics industry drastically. GaN devices offer superior converter performance due to their ability to switch at higher frequencies than conventional Silicon (Si) devices [1,2,3,4,5,6,7]. Enhancement-mode (E-mode) GaN HEMTs are gaining popularity in switching power supplies because they are inherently normally off devices [8,9,10]. However, these devices have stringent gate driving voltage limits (–10 to 7 V) and often require additional protection circuits [11]. Conversely, depletion-mode (D-mode) GaN HEMTs are normally on devices, which have a wider gate voltage range (–30 to 8 V) [12]. Moreover, D-mode GaN HEMTs usually offer lower on-resistance and smaller junction capacitances than similarly rated E-mode devices [13].

Conventionally, a Si MOSFET is used in series with a D-mode GaN HEMT to simplify the driving requirements. Here, the source of the MOSFET is connected to the gate terminal of the D-mode GaN HEMT. This configuration, known as the cascode structure, makes the device normally off and makes it compatible with conventional power electronic circuits, where normally off devices are preferred due to safety reasons [14]. Usually, low-voltage laterally diffused MOSFETs (LDMOS) are used in the cascode structure [15]. However, owing to the high cost of LDMOS, conventional N-channel MOSFETS (NMOS) are gradually replacing them in the cascode structure.

During the turn off transition, the voltage distribution between the D-mode GaN HEMT and the NMOS depends on the device junction capacitances. Because of the significant variation in the input capacitance of D-mode GaN HEMT between turn-on and turn-off transitions, a large portion of the drain–source voltage may fall on the NMOS during its turn-off time. In certain cases, this voltage may exceed the rating of the NMOS and lead to an avalanche of the NMOS causing additional losses and reliability concerns. Moreover, since the source of the NMOS is connected to the gate of the GaN HEMT, this voltage may also permanently damage the GaN HEMT since its gate–source voltage can surge to a negative value, which exceeds the limit of the GaN HEMT’s gate structure.

Few solutions to this inherent problem of the cascode structure are discussed in the literature. The circuit proposed in [13] uses an additional capacitor in parallel with the drain–source terminal of the NMOS in the cascode structure. While this simple solution is able to reduce the voltage appearing across the gate–source terminal of the GaN HEMT, it can potentially reduce the switching frequency of the device. This is because the additional capacitor increases the input capacitance of the GaN-HEMT. Moreover, the additional parasitic inductances introduced with this discrete capacitor can also lead to an excessive ringing of the switch node in the hard-switching mode of operation [16].

The direct-drive configuration, where the series-connected NMOS is always kept on during regular operation and the D-mode GaN HEMT is directly controlled, is another solution to the above-mentioned problem. However, existing implementations of this approach require two separate voltage supplies a positive supply keeping the NMOS on and a negative supply for controlling the D-mode GaN HEMT [17]. Although bootstrap-based circuits are proposed in [18] for a single supply operation, many additional components add to the cost.

This paper proposes two innovative direct drive circuits, namely the GaN-switching based cascode GaN HEMT and the modified GaN-switching based cascode GaN HEMT. Only two diodes and one capacitor are used in these driving circuits. This capacitor is used to provide a negative voltage to the D-mode GaN HEMT during the device turn off. The diodes are used to prevent the discharging of the gate to source capacitance of the NMOS during regular operation. Both of these circuits reduce the gate to source voltage stress on the GaN HEMT while retaining all the advantages of a normally off GaN device with a high switching frequency. The application of the proposed circuits is demonstrated in a 60 W flyback converter and compared with an existing solution. Figure 1 summarizes the advantage of the proposed scheme over existing gate driving schemes of D-mode GaN HEMTs.

The operating principles of the proposed circuits are explained in Section 2, followed by operating principles of the flyback converter in Section 3. The experimental results and comparison are presented in Section 4. A discussion on the advantages and disadvantages of proposed circuits is provided in Section 5. The main conclusions of this work are summarized in Section 6.

2. Cascode GaN HEMT Power Module

2.1. D-Mode GaN HEMT

The D-mode GaN HEMT made in NCTU is a depletion mode, normally on device. After device fabrication, Si substrate back side grinding, polishing, and back side metal deposition were formatted, after chip dicing, all the GaN devices were packaged in TO220 case package. Keysight B1500A semiconductor parameter analyzer was used to detect the multi-frequency parasitic capacitance measurements of 500 kHz and 1 MHz switching of D-mode GaN HEMT. The capacitances of 1 MHz are only slightly higher than that of 500 kHz, however significant capacitance changes between 1 kHz and 800 kHz and between 1 and 5 MHz are presented in [19,20], respectively. The measurement result is shown in Figure 2 and

Table 1. Characteristics summary of the D-mode GaN HEMT under 1 MHz switching.

Symbol	Unit	Description	Value	vDS
				0 V	200 V	800 V
vGS,ON vGS,OFF	V	Turn-on voltage (All)	−7
CDS	pF	Parasitic capacitance		40	33	30
CGD	pF	Parasitic capacitance		220	26	20
CGS	pF	Parasitic capacitance		100	112	115
VGS,max	V	Maximum gate–source voltage	8
VGS,min	V	Minimum gate–source voltage	−30
VDS,BD	V	Drain–source breakdown voltage	800

. The parasitic capacitance C_ISS = C_GD + C_GS is 50% smaller when the transistor is turning off than that of turning on. The parasitic capacitance C_OSS = C_GD + C_DS of turn-on is five times as high as turn-off. The small variation on the turn-on and turn-off parasitic capacitance merits the use of the GaN HEMT on fast switching since it reduces the nonlinearity of the displacement current i = C(dv_c/dt) during switching.

From Figure 2, it is found that there is no modification of the parasite capacitance after the value of 200 V up to 800 V, the dynamic response of the high v_DS voltage DCM will encounter no additional problem as compared to that of the low voltage CCM.

2.2. MOS-Switching Cascode GaN HEMT

The normally on characteristics of D-mode GaN HEMT is likely the JFET. A device that is normally on with zero gate voltage and which requires a negative value to be off is inconvenient in certain applications such as in the switching power supply. When a cascade GaN HEMT is combined with a low voltage NMOS as in Figure 3, it becomes a cascade, and the advantage shows. In this arrangement, with a positive gate voltage, the NMOS is on, pulling the GaN HEMT source to the ground setting it on with its gate at the ground. When the NMOS gate is nearly 0 V, its drain rises in voltage, reverse biasing the GaN HEMT gate–source turning it off. The NMOS can be a low voltage type, such as a low voltage LDMOS, and only rises to around 10 V with low on-resistance, insignificantly compared with the GaN HEMT. We then have a normally off device with a commonly used gate drive, high voltage and temperature rating. With a bonus on the Miller capacitance is effectively absent due to the low drain–source voltage, the switching frequency may be high. Aside from the high breakdown voltage from the GaN, the merits of Cascode GaN HEMT power module are summarized as follows.

• Normally off; most of switching power supplies, such as flyback converter require this feature;
• Low Miller effect versus MOSFET; high switching frequency;
• Current limiting: the saturation current is constant with drain voltage because GaN has a negative temperature coefficient; the current decreases due to decreased electron mobility.

However, the laterally diffused MOS is much more expansive than the regular MOS today due to its complexity of the epitaxy process.

Instead of using a LDMOS, a normal NMOS is used in our evaluation. As shown in Figure 4, when the NMOS turns off, the voltage across the drain–source parasitic capacitance is given with the nominal values 140 pF and assuming that the GaN HEMT was also turned off simultaneously with its nominal drain–source parasitic capacitance 30 pF. The rest of the parasitic capacitances are also shown on Figure 4. The drain–source voltage across the NMOS is then derived as follows.

$$\frac{v_{DS,MOS}}{V_D}=\frac{c_{ds,GaN,off}}{\left(c_{iss,MOS,off}+c_{ds,MOS,off}+c_{gs,GaN,off}\right)+c_{ds,GaN,off}}$$

(1)

It is then according to the nominal values of the capacitances to derive the drain–source voltage of the NMOS during the turn-off time as follows.

$$\frac{v_{DS,MOS}}{V_D}=\frac{30}{150+30}=17\%$$

(2)

When $V_D=$ 153 V, the $v_{GS,GaN}=-v_{DS,MOS}=-26 \mathrm{V}$. With the GaN HEMT with the Schottky Barrier Diode (SBD), only the gate endures the reverse bias voltage 26 V. The idea of using a normal NMOS in cascode arrangement is negated when $V_D=$ 300 V since the SBD of the GaN will not suffer a reverse bias $v_{GS,GaN}=-52 \mathrm{V}.$

In order to reduce the high reverse bias problem during turn-off state, which can permanently damage the SBD, a remedy design [13], referred to as the Type 1B in this paper, is shown in Figure 5. Through adding a compensation capacitor $C_s$, Equation (1) can be written as follows.

$$\frac{v_{DS,MOS}}{V_D}=\frac{c_{ds,GaN,off}}{\left(c_{iss,MOS,off}+c_{ds,MOS,off}+c_{gs,GaN,off}\right)+c_{ds,GaN,off}+C_s}=\frac{30}{180+C_s}$$

(3)

For the application that $V_D=$ 800 V and $v_{GS,GaN}=v_{DS,MOS}\ge -30 \mathrm{V}$ during turn-off, it is calculated from Equation (3) that $C_s=790 \mathrm{pF}$. However, the capacitor added in between the gate and source of the GaN HEMT can potentially reduce the switching frequency due to the $C_{iss,GaN,off}=c_{GS,GaN,off}+c_{DS,GaN,off}$ of the GaN HEMT is increased by nearly five times from the parasitic value. According to Equation (3), the power module based this modified cascode GaN HEMT topology was assembled in this research with the element parameters, as shown in

Table 2. Parameters of the Type 1B power module.

Symbol	Unit	Description	Value
Cs	nF	Compensation capacitor of Type 1B	1
NMOS		E-mode N channel MOSFET	IRF610

.

2.3. GaN-Switching Cascode GaN HEMT Power Module

The alternative low-cost design using a normal NMOS without the use of compensation capacitor $C_s$ slows down the switching but can still hold for the three merits including normally off, low Miller effect, and current limiting. The idea was initiated from turning on the NMOS, and it stays turned on from when it turned on initially, and the GaN HEMT becomes the actual switch. The circuit is discussed in detail in the following sequels.

The GaN-switching cascode GaN HEMT power module, referred to as the Type 2A in this paper, shown in Figure 6, consists of three terminals which are the module drain, the module source, and the module gate. In front of the gate of E-mode NMOS, there is a diode that connects the module gate with the NMOS gate. The source of the power module is connected to the ground, therefore $v_S=0 \mathrm{V}$. A clamp circuit is inserted in front of the gate of the GaN HEMT. Both the NMOS and D-mode GaN HEMT turn off when the capacitor $C_c$ of the clamp circuit is not charged in the initial state. Therefore, it is a normally off power module when $v_G=0 \mathrm{V}$ initially. As shown in Figure 7, during the time when the $v_G=V_{G,High}$ all of the capacitor $C_c$, the parasitic gate–source capacitor of NMOS, i.e., $c_{gs,MOS}$, and the parasitic gate–source capacitor of GaN, i.e., $c_{gs,GaN}$, are charged to the high level, i.e., $V_{G,High}$, since NMOS will be turned on immediately. The voltage across $c_{gs,MOS}$ is only slightly discharged since the diode $D_2$ is in reverse bias afterward. Thus, the NMOS is consistently turned on as shown in Figure 7. After the capacitor $C_c$ of the clamp circuit is charged to the high level, it is not rapidly discharged since the diode $D_1$ is in reverse bias since being first turned on. When the module gate is switched to its low voltage level, the GaN is switched off due to the voltage being clamped down by the clamp capacitor $C_c$ providing $V_{G,High}>-V_{GaN,OFF}$ for the GaN to be turned off. The value of our D-mode GaN is $V_{GaN,OFF}=-7 \mathrm{V}$. As a result, in Figure 7, the $v_{DS}$ of the module is high in the initial time because the NMOS is off, which will be switched to either on to a low voltage output or off to a high voltage depending on the input voltage of $v_G$ that switches the GaN HEMT.

In case the NMOS is always on, the equivalent circuit of cascode GaN HEMT module shown in Figure 6 is then reduced, as shown in Figure 8. Subjected to the switching frequency is around 300 kHz, the impedance of $c_{ds,MOS}$ can be dominant only on the instances of either switch-on or switch-off. During any other time, the $c_{ds,MOS}$, in the order of nF, results in a 100 Ω impedance and is ignored from the parallel connection. The on-resistance of the NMOS is a current feedback for the GaN HEMT. The decreasing current flowing on the resistance $r_{d,on,MOS}$ during the GaN HEMT turn-off time can actually impose a Miller effect similar to a time delay. Similar to the effect on the turn-on time, the increasing current flow on the resistor delays the turn-on process. Thus, the on-resistance of the NMOS is preferred to be as small as possible. On the contrary, at the sharp time during both turn-on and turn-off, the parasitic capacitance $C_{ds,MOS}$ in series with the parastic capacitances of GaN flow in- and flow-out current are in the direction to help shorten the transient time of the switching and thus the Miller effect of GaN HEMT is reduced.

The current feedback from $r_{d,on,MOS}$ may not degrade the switching frequency as stated in the previous section, which still imposes a problem on the clamp capacitor $C_c$. As shown in Figure 8, an amount of the charge from the charge pump leaks through $c_{gs,GaN}$, $r_{d,on,MOS}$, and then to the ground in the turn-off state since the NMOS is always on. The amount of the charge loss during the turn-off time is refilled during the turn-on stage when $v_G$ becomes positive again.

The source terminal of the power module is connected to the ground and $v_S=0 \mathrm{V}$. Without concerning the current feedback, let the charge on the clamp capacitor $C_c$ be denoted by $Q_c$, the clamp capacitor $C_c$ is charged with $Q_c$ when $v_G=0$ to make the voltage across the parasitic capacitance $C_{gs,GaN}$ be lower than $V_{GS, GaN,OFF}$ and to have GaN HEMT be turned off. The voltage $v_{g,GaN,1}$ is the voltage $v_{g,GaN}$ as indicated in Figure 8 at the beginning of $v_G=0$.

$$v_{g,GaN,1}=-v_{G,High}=-v_{cc}=\frac{Q_c}{C_c}$$

(4)

The charge on the parasitic gate–drain capacitor denoted by $Q_{gd,GaN}$ when $v_{DS}\gg v_{G,High}$ may be expressed as follows.

$$v_{DS}=V_{DS,off}=\frac{Q_{gd,GaN}}{c_{gd,GaN}}$$

(5)

The charge conservation law, without concerning the charge loss from $c_{gs,GaN}$, holds a relation as follows during the turn-off process. The voltage $v_{g,GaN,2}$ is the voltage $v_{g,GaN}$ as shown in Figure 8 at the end of $v_G=0$. The difference between $v_{g,GaN,1}$ and $v_{g,GaN,2}$ is shown in the last row of Figure 7.

$$v_{g,GaN,2}=\frac{Q_c-c_{gd,GaN}{V}_{DS,off}}{C_c}=\frac{-C_c{v}_{G,High}-c_{gd,GaN}{V}_{DS,off}}{C_c}$$

(6)

To ensure the GaN HEMT is turned off properly, it is required $v_{g,GaN,2}\le V_{GS,GaN,off}$ so that

$$C_c\ge \frac{V_{DS,off}}{v_{G,High}+V_{GS,GaN,OFF}}{c}_{gd,GaN}$$

(7)

In the case that $v_{G,High}=12 \mathrm{V}$ and $V_{GS,GaN,OFF}=-7 \mathrm{V}$, $V_{DS,off}=800 \mathrm{V}$, and $c_{gd,GaN}=30 \mathrm{pF}$, the $C_c$ followed the above equation shall be no less than 4.8 nF. Conversely, when the said current feedback is concerned, we will need to add the current leakage, which is formulated as follows.

$$i_r=\frac{v_{g,GaN}-v_{gs,GaN}}{r_{d,on,MOS}}$$

(8)

The $v_{gs,GaN}$ is 0 at the beginning time of $v_G=0$. The maximum current of $i_r$ following Equation (8) during the switching is derived by taking the average of $v_{g,GaN,1}$ and $v_{g,GaN,2}$ as follows.

$$i_{r,max}=\left(\frac{v_{g,GaN,1}+v_{g,GaN,2}}{2}-0\right)\frac{1}{r_{d,on,MOS}}.$$

(9)

The total charge loss may be estimated by multiplying the $i_{r,max}$ with the time constant $\left(C_c+c_{gd,GaN}+c_{gs,GaN}\right)r_{d,on,MOS}$ from the high pass filter, which is then

$$∆Q=-i_{r,max}\left(C_c+c_{gd,GaN}+c_{gs,GaN}\right)r_{d,on,MOS}=-\left(C_c+c_{gd,GaN}+c_{gs,GaN}\right)\frac{v_{g,GaN,1}+v_{g,GaN,2}}{2}$$

(10)

Equation (10) concerning the charge loss from $c_{gs,GaN}$ becomes as follows during the turn-off process.

$$v_{g,GaN,2}=\frac{-C_c{v}_{G,High}-c_{gd,GaN}{V}_{D,off}-∆Q}{C_c}$$

(11)

When $C_c>>c_{gs,GaN}, c_{gd,GaN}$, the $C_c$ is derived as follows.

$$C_c\ge \frac{2V_{DS,off}}{v_{G,High}+V_{GS,GaN,OFF}}{c}_{gd,GaN}$$

(12)

The $C_c$ following the above equation shall be no less than 9.6 nF to ensure the turn-off process to be performed absolutely. According to Equation (12), the power module based on this GaN-Switching cascode GaN HEMT topology was assembled in this research with the element parameters as shown in

Table 3. Parameters of the Type 2x power modules.

Symbol	Unit	Description	Value
Cc	nF	Charge pump capacitor of Type 2x	10
NMOS		E-mode N channel MOSFET	IRF610
cgs,NMOS	pF	Parasitic gate–source capacitance of NMOS	200
D1		Low Leakage diode	BAV170
D2		General purpose diode	1N4007

. When the input V_DD is disconnected, it will mostly need 10 s, known as the replugging time, to drain out the charge in the parasitic gate–source capacitor through the reverse saturation current from D₂ in the power module as shown in Figure 6. The reverse current for the diode BAV170 is 1 uA. For the parasitic gate–source capacitor with capacitance 200 pF and 10 V, the charges stored are 2 nC. However, the route for gate–source capacitor to discharge must go through the charge pump capacitor C_c, the charge pump is with capacitance 10 nF and 10 V. The time required to discharge the charge storage in the charge pump is 0.1 s. Thus, the time interval required for the power module be reset into E-mode is suggested to be 1 s when considering the diode resistance of D₁ and the time constant. Low leakage is the key feature of the diode D₁ used in the charge pump to prevent the charge pump leaks during turn-off time. Low zero bias junction capacitance is the key feature of the diode D₂ used on NMOS side to expedite the charge process of C_GS of NMOS. The charge pump capacitor C_c must be as large as 20 times of the C_oss of the GaN HEMT to stabilize the voltage of charge pump tank because the C_oss of the GaN HEMT varies five times between turn-on and turn-off. Conversely, large charge pump capacitor Cc will increase the size of the gate driver.

2.4. Alternative GaN-Switching Cascode GaN HEMT Power Module

The alternative GaN-switching cascode GaN HEMT power module as shown in Figure 9, is referred to as Type 2B in this paper, in which we interchanged the GaN HEMT and NMOS sequence on the cascode topology. In order to avoid the current feedback effect during the turn-off state, as stated previously, the source of the GaN HEMT is connected to the ground. As shown in Figure 8, during the time when the $v_G=V_{G,High}$ all of the capacitor $C_c$, the parasitic gate–source capacitor of NMOS, i.e., $c_{gs,MOS}$, and the parasitic gate–source capacitor of GaN, i.e., $c_{gs,GaN}$ are charged. Unlike the original version of GaN-switching cascode GaN HEMT power module, the voltage on the parasitic gate–source capacitor of NMOS, i.e., $v_{gs,MOS},$ reaches $V_{G,High}$ due to it cascodes the $c_{oss,GaN}=c_{ds,GaN}+c_{gd,GaN}$ of the GaN, which is derived as follows.

$$v_{gs,MOS}=\frac{c_{oss,GaN}}{c_{oss,GaN}+c_{gs,MOS}}{V}_{G,High}$$

(13)

Due to the parasitic capacitances of $c_{oss,GaN}$ during the turn-on time is five times as higher as it is during the turn-off time. The voltage $v_{gs,MOS}$ is as low as one-quarter of $V_{G,High}$ since during the time GaN turns off $c_{oss,GaN}$ is small, such as 60 pF, subjected to a larger capacitance $c_{gs,MOS}$, such as 200 pF. The NMOS may not be always on during the switching process. The corresponding signals are shown in Figure 10.

In such case, we will need to increase $V_{G,High}$ in order to first turn on the NMOS, and then turn on the GaN. This process will repeat each cycle of switching and increase the delay time during switching. However, it can still be preferred by the GaN device, which can be used as a simple switch without considering the current feedback effect from the NMOS. The result of using the alternative GaN-switching cascode GaN HEMT power module will be shown in the later results and comparisons section. The power module based on this alternative GaN-Switching cascode GaN HEMT topology was assembled in this research with the element parameters the same as shown in Table 3.

3. Flyback Converter

The flyback converter as shown in Figure 11 is frequently used in the fast charger power supply applications. In the PWM and gate driver of Figure 11, the charge pump circuit as a main focus in this paper is driven by a simple Si MOSFET gate driver LM5114. The gate driver LM5114 is connected to the charge pump using two non-zero resistances R_G,p and R_G,n [21] are used to reduce the drain current rings during turn on and off. However, when R_G,p is too high, it causes a negative voltage surge due to the rapid retraction of negative charges through C_GD and C_C to R_G,p. The negative voltage can potentially surge down to lower than −V_GS,max and cause the gate source to break down. The snubber circuit is important on the wave form of both the voltage $v_{DS}$ and the current on the secondary winding $i_S$, and furthermore, it determines the maximum voltage for $v_{DS}$ and the maximum current for $i_S$. The permanent breakdown of the power module can be caused by the ringing effect on $v_{DS,max}$. The power loss on the diode D_S can dramatically increase due to high $i_S$. In the following steady state analysis, we first assume the snubber circuit does not affect much of the power conversion efficiency. In addition, the discontinuous current mode (DCM) is assumed in the following derivations. The flyback converter was assembled in this research with the element parameters as shown in

Table 4. Parameters of the flyback converter.

Symbol	Unit	Description	Value
LP	uH	primary inductance of transformer	400
LS	uH	secondary inductance of transformer	10.27
a		turn ratio of transformer	6.24
k		coupling coefficient of transformer	98.7%
CB	nF	capacitance of the snubber	1
R2	Ω	series resistance of the snubber	33
R1	kΩ	parallel resistance of the snubber	100
CS	uF	capacitor on secondary side	2200
Cjo	pF	capacitance of the diodes	10

. $i_1$ is the current flowing through the power module, which equals to $i_P$ when the snubber circuit is ignored.

When the transistor turns on in the duty $\delta$ of a period time $T$, the primary winding current $i_P$ rises from $i_{P,min}$ to $i_{P,max}$

$$∆i_P=i_{P,max}-i_{P,min}=\frac{V_{DD}\delta T}{L_P}$$

(14)

When the transistor turns off, assuming the ideal diode is used in the secondary and the secondary capacitor is in the steady state with the nominal voltage $V_o$, the secondary winding current $i_S$ falls from $i_{S,max}$ to $i_{S,min}$.

It is commonly agreed that the flyback converter with low output current is suitable for discontinuous current mode (DCM) operation and continuous current mode (CCM) operation is suitable for large output current. With the other observation on the switch breakdown voltage capability, low-voltage work is preferably applying the CCM mode and high-voltage work is advantageous in using the DCM mode. The discontinuous current mode was analyzed in detail in [22]. The important derivation results that we included in this paper are used to compare different cascode arrangement. The switch-off time t_r of the power module when it turns off is shown as follows.

$$t_r=\frac{\pi \sqrt{L_1(C_{oss,GaN}+C_{j0})}}{5}$$

(15)

$C_{j0}$ is the diode capacitance. The output parasitic capacitance of the power module can be estimated by the equation as follows.

$$C_{oss,GaN}=\frac{25t_r{}^2}{{\pi }^2{L}_P}-C_{j0}$$

(16)

Continuous Current Mode (CCM) Analysis

According to Equation (14), the inductance of the primary inductance of the transformer and the input voltage determines the current ripple of the input. Due to the energy conservation in the magnetic field,

$$\frac{1}{2}{L}_P{i}_{P,max}{}^2=\frac{1}{2}{L}_S{i}_{S,max}{}^2$$

(17)

The transformer is assumed activated during the time the power module is switching from either on to off or off to on providing that the coupling coefficient is assumed 100%.

$$N_P{i}_{P,max}=N_S{i}_{S,max} \mathrm{and} N_P{i}_{P,min}=N_S{i}_{S,min}$$

(18)

Substituting the above equation into Equation (4), we have the current range in terms of the turn ratio $a=N_P/N_S$ as follows.

$$i_{P,max}=a\left(\frac{V_{DD}\delta T}{L_P}+i_{P,min}\right)$$

(19)

The magnetic energy is shuffled to the capacitor during the transistor turn-off time, which is

$$\frac{1}{2}{L}_P\left(i_{P,max}{}^2-i_{P,min}{}^2\right)=\frac{1}{2}{C}_S\left(v_{o,max}{}^2-v_{o,min}{}^2\right)$$

(20)

The capacitor energy gain will supply constantly, when the converter is in its continuous current mode, to the output load

$$\frac{1}{2}{C}_S\left(v_{o,max}{}^2-v_{o,min}{}^2\right)=\frac{V_o{}^2}{T{R}_o}$$

(21)

It is then derived that

$$a\frac{V_{DD}\delta T}{L_P}=i_{S,max}-i_{S,min}=\frac{V_o\left(1-\delta \right)T}{L_S}$$

(22)

Thus, the input and output voltage are equated as follows.

$$V_o=\frac{\delta }{a\left(1-\delta \right)}{V}_{DD}$$

(23)

Since

$$V_o=\frac{v_{o,max}+v_{o,min}}{2}$$

(24)

let

$$v_{o,max}-v_{o,min}=V_{o,ripple}$$

(25)

From Equation (25), when $v_{o,min}\gg V_{o,ripple}$ we obtain that

$$V_{o,ripple}=\frac{T}{R_o{C}_S}{V}_o$$

(26)

From Equation (26), it is found that $V_{o,ripple}$ must be no less than $2V_o$ and the condition for CCM is $T<2R_o{C}_S$. The steady state drain–source voltage in terms of the turn ratio a and the measured output voltage value V_o during the transistor turns off is obtained as follows.

$$v_{ds,ss}=V_{DD}+a{V}_o$$

(27)

According to the above equation, we will prefer a large turn ratio $a$ in order to reduce a large current surge $i_{P,min}$ from zero when the transistor turns off. Substituting Equation (23) into Equation (27), we derive the theoretical maximum drain–source voltage in terms of the function of duty cycle $\delta$ as follows.

$$v_{ds,max}=\chi v_{ds,ss}=\chi \frac{V_{DD}}{1-\delta }$$

(28)

The ratio $\chi$ denotes the ringing factor on the drain–source voltage during the transistor turns off, which is no less than 1. From the energy conservation between the input and output assuming that the power loss is negligible, we derive the average current on the transistor during its turn-on as follows.

$$I_P=\frac{i_{P,max}+i_{P,min}}{2}=\frac{I_o{V}_o}{\delta V_{DD}}=\frac{I_o}{\left(1-\delta \right)a}=\frac{V_o}{a\left(1-\delta \right)R_o}$$

(29)

From the transistor current point of view, in order to minimize the on-resistance loss we need a small duty cycle $\delta$.

$$i_{P,min}=I_P-\frac{∆i_P}{2}=\delta V_{DD}\left(\frac{1}{a^2{\left(1-\delta \right)}^2{R}_o}-\frac{T}{2L_P}\right)\ge 0$$

(30)

It can be observed from the above equation that the boundary resistance $R_{oB}$ between continuous current mode and the discontinuous current mode is derived as follows, and the CCM is resulted by a smaller resistance than $R_{oB}$.

$$R_{oB}=\frac{2f_s{L}_P}{a^2{\left(1-\delta \right)}^2}=\frac{2f_s{L}_S}{{\left(1-\delta \right)}^2}$$

(31)

The power loss consists of three parts (1) the diode loss, (2) the transistor on-resistance loss, and (3) the switching loss of the transistor.

$$\begin{gathered} P_{L, diode}=I_S{V}_{diode,S}=\frac{1}{1-\delta }\frac{V_{diode,S}}{V_o}{P}_o \\ {P}_{L, on}=I_P{}^2{r}_{on,T}=\frac{1}{{\left(1-\delta \right)}^2}\frac{r_{on,T}}{a^2{R}_S}{P}_o \end{gathered}$$

(32)

$V_{diode,S}$ is the voltage drop on the secondary side. The switching loss is a function of the current and the voltage during each switching, which can be simplified as follows.

$$P_{L, switching}=\alpha f_s{I}_P{V}_{DS,max}=\alpha f_s\frac{V_o}{a\left(1-\delta \right)R_o}\frac{V_{DD}}{1-\delta }=\frac{\alpha f_s}{\delta \left(1-\delta \right)}{P}_o$$

(33)

When the flyback converter is designed as a step-down converter and $a\gg 1$, the transistor on-resistance loss is ignorable, the total power loss is

$$P_L=P_{L, diode}+P_{L, switching}=\frac{1}{1-\delta }\left(\frac{V_{diode,S}}{V_o}+\frac{\alpha f_s}{\delta }\right)P_o$$

(34)

The power efficiency $\eta$ is derived as follows.

$$\eta =\frac{P_o}{P_o+P_L}=\frac{1}{1+\frac{1}{1-\delta }\left(\frac{V_{diode,S}}{V_o}+\frac{\alpha f_s}{\delta }\right)}\approx 1-\frac{1}{1-\delta }\left(\frac{V_{diode,S}}{V_o}+\frac{\alpha f_s}{\delta }\right)$$

(35)

Therefore, in order to increase the efficiency of the flyback converter, we need to (1) use the AMR (active MOSFET rectifier) or ideal diode and (2) to reduce switching loss by using lower switching frequency or duty cycle at $\delta =0.5$.

4. Results and Comparisons

Figure 12 demonstrates the result of V_DD = 300 V, switching frequency $f_s$ = 280 kHz. and $\delta =0.48$, $R_o=50 \mathsf{\Omega }$. We substitute the secondary inductance $L_2$ = 10.27 uH into Equation (31) to find $R_{oB}=22 \mathsf{\Omega }$. Since $R_o$ is greater than $R_{oB}$, the result in Figure 12 has to be in the DCM operation. The switching result for different cascode arrangements are compared. In the figure, the light blue line depicts the gate–source voltage. Since the switch control of Type 1B is MOSFET, the drain–source voltage of the MOSFET is the source–gate voltage of the GaN as stated in Equation (11). It is observed that the ratio between the drain–source voltage of the GaN is 40 times as the drain–source voltage of the MOSFET. The gate–source voltage of the GaN during turn-off is negative 20 volt which is in the safety region of the minimum gate–source voltage of the GaN. The green line is the output current in mA. Type 1B shows a larger ringing when it turns on. Observed from the waveforms, it oscillates stronger in high frequency of GHz range, which is more than Type 2A and Type 2B, and may need larger EMI filter. Type 2B shows the least Miller plateau effect among all types when it turns off.

The dark blue lines in Figure 12 depicts drain–source voltage of different cascode power modules, the maximum drain–source voltage can reach the breakdown voltage and permanently damage the GaN HEMT. According to Equation (28), the maximum v_ds,max is 600 V in CCM when the ringing factor $\chi =1$.

The switch-off time in Equation (15) is compared and shown in

Table 5. Output parasitic capacitance estimation.

Symbol	Unit	Description	Type 1B	Type 2A	Type 2B
tr	ns	switch-off time	164	170	188
vds,max	V	Max. drain–source voltage	720	735	770
Coss	pF	Estimated output parasitic capacitance using Equation (16)	170	183	233

. It is observed that Type 2B yields the highest drain–source voltage among the three types. That is because the output parasitic capacitance of Type 2B is higher than others. It is also found that Type 2A yields the best smooth drain–source voltage response, which can help the zero current switching of the CCM operation.

Subjected to the same input voltage at V_DD = 150 V, the response of different power modules in various of cascode arrangements are compared in Figure 13. They are all in the state of zero voltage as well as zero current when they were turned on. It is again seen that the output of Type 1B yields GHz frequency oscillation larger than other types do. The dark blue line indicates the v_ds. The lower current output ones are subjected to higher output resistances. The results show that the lower the output current, the smaller and duty cycle is and the higher the v_ds,max is as well. The purple lines are the output current on the secondary sides, which became more triangular when the output current is larger. The blue lines are v_ds,NMOS of Type 1B and v_ds of Type 2A and 2B. The green lines are the input current on the primary sides, which are in the same slope; thus, the larger the duty cycle δ (%), the higher the maximum currents are. The corresponding switching frequency of the zero current switching is monotonically decreasing with the increasing output current due to the time required to charge the primary winding, as given in Equation (17). The power conversion efficiency decreases with the increasing switching frequency. According to Equation (35), when we are using the same diode on the secondary side with increasing output voltage V_o, i.e., a larger output current on larger output resistance, the power efficiency $\eta$ drops mainly because of the increasing switching loss on higher switching frequency.

In order to be independent of the switching loss, we fixed the switching frequency and duty to compare the power efficiency on DCM operation of different cascode arrangements in Figure 14. The experiments were subjected to switching frequency $f_s$ = 280 kHz, $\delta =0.48$, and $R_o=50 \mathsf{\Omega }$, which show that Type 2A and Type 2B yield better power conversion efficiencies than Type 1B. The power conversion efficiencies of Type 2A and Type 2B depend on the input voltage V_DD. Type 2A yields better efficiency in high input voltage V_DD while Type 2B is better in the low input voltage V_DD. It is also found that Type 2A had dynamic characteristics similar to Type 1B subjected to low input voltage, and which becomes similar to Type 2A subjected to high input voltage.

Figure 15 depicts the power loss of Type 2B power module; it can be seen that when the gate–source voltage v_gs is lower than –7 V, GaN turns off, and then the NMOS is turned off, which causes a reverse recovery current to surge. The power loss calculated based on the integration of multiplication of the input current with the drain–source voltage of the power module shows 45% of the total power loss is during the time when transistor turns off and only 10% loss is due to the turn-on. It seems that the power conversion merits the use of Type 2B cascode; however, it often shows the bistable result, i.e., there are multiple traces of the switching results because of the $c_{gs,MOS}$ of the IRF610 NMOS is as high as 200 pF, the gate–source voltage according to Equation (13) will decrease to low voltage when GaN HEMT turns off. The assumption that the NMOS is always on is not available. A particular example of bistable occurrence is demonstrated in Figure 16 in which the green line is the input current on the primary winding side, the dark blue lines are the drain–source voltage of GaN HEMT, the light blue lines are the gate voltage on the GaN HEMT, and the purple lines are the diode current i_S on the secondary side.

The continuous current mode (CCM) operation is commonly used for the high power application. Subjected to the AC input voltage 110 V, which yields the 155 VDC, Type 2A was used for the comparison study. Figure 17a shows the experiment results for V_DD = 150 V and Ro = 5 Ω applications. The power conversion efficiency for 60 W output under the CCM is 95.1%, which is lower than the DCM result 96.3% depicted in Figure 14a. The differences through comparing Figure 12b and Figure 17b are shown in

Table 6. Comparison of DCM and CCM at 60 W output when turn ratio a = 6.24.

Mode	Efficiency (%)	Pout (W)	Duty (%)	VDD (V)	Ro Ω	vds,max (V)	vds,ss *	Io,max (A)	Vo (V)
DCM	96.3	59.62	48	300	50	735	641	6.9	54.6
CCM	95.1	59.17	43	150	5	423	257	35.4	17.2

* derived from Equation (26).

. According to Equation (35), it is obtained that in order to reduce the switching power loss, the duty cycle is preferable to be 50%. In addition, a high duty cycle will increase the transistor resistance and diode loss. Thus, the comparisons in Table 6 are purposely maintaining the duty cycle to be around 50%. In the DCM operation, the input voltage V_DD = 300 V is corresponding to 220 VAC. In the CCM operation, the input voltage V_DD = 150 V is corresponding to 110 VAC. It is observed from Table 6 that when the CCM operation with neither ZCS nor ZVS control possible, the voltage ringing v_ds,max is 160% of the steady state voltage of $V_{ds.ss}=V_{DD}+a{V}_o=257 \mathrm{V}$ according to Equation (27). The DCM with the assistance of ZVS and ZCS control presenting the voltage ringing v_ds,max is only 115%. Hence, DCM is good for the high input voltage and/or high output voltage applications. In the CCM operation, the remaining current in the secondary winding will map back to the primary side, the sudden current change can cause the gate drive to ring and increase the power loss when the power module turns on. According to Equation (30), they are evaluated and compared in

Table 7. Comparison of CCM current.

Io	δ (%)	i1,min		∆i1
		Equation (29)	Experiment	Equation (14)	Experiment
33.44	43	0.35	0.34	1.34	1.26
4.1	48	0.62	0.6	1.5	1.4
4.74	53	1.02	0.88	1.66	1.52

. The experimental values are calculated based on visualized estimation, which are lower than the value obtained from Equation (30), however, in similar range.

In particular interests of the Vo = 20 V application, we have chosen to fix V_DD = 150 V, Vo = 20 V, Duty 48%, and Ro = 5 Ω. Type 2A cascode arrangement is used in this CCM study. We varied the switching frequency and obtained the results as shown in Figure 18. The result is again consistent with Equation (35), that the higher the switching frequency, the lower the power efficiency becomes. The power output fluctuation is in the similar trend of the power efficiency. The photo of the circuit in the experiment is shown in Figure 19.

5. Discussion

The conventional cascode GaN HEMT, namely Type 1A, usually requires to co-work with a low voltage LDMOS in order to avoid a large portion of the drain–source voltage falling on the MOSFET during its turn-off time and permanently damaging the GaN HEMT on the gate structure. Type 1A with compensation capacitor $C_s$ placed side-by-side with the low cost MOS (Type 1B), in this study we adopted IRF610, which can reduce the drain–source voltage during the turn-off time. As shown in Figure 12a, the v_ds is stabilized to a low voltage without any voltage surge due to the reverse recovery current. The drawback of Type 1B is the extra compensation capacitor $C_s$ added to the drain–source side of the NMOS, which will increase the capacitive load when switching the D-mode GaN HEMT off. The power conversion performance is then downgraded in the high voltage applications as shown in Figure 14a. It is also observed from comparing the waveforms to the different cascode GaN HEMT; Type 1B presents larger oscillation in GHz high frequency as shown in Figure 12a.

Type 2A cascode GaN HEMT relies on the NMOS to switch off the power module when the input voltage is disconnected. The E-mode characteristic is granted by the NMOS initially and NMOS stays turned on since it is turned on. The D-mode GaN bore almost all drain–source voltage during the turn-on state, which is a high breakdown voltage device. It will mostly need 1 s, known as the replugging time, to drain out the charge in the parasitic gate–source capacitor through the reverse saturation current from D₂ in the power module as shown in Figure 6. Type 2A cascode is good in both DCM and CCM operations in the flyback converter applications. For the specific flyback converter, we used to compare different cascode GaN HEMT arrangements, Type 2A is extraordinary not only in the CCM operation with low voltage input and low power output as shown in Figure 14a, but also for typical applications with 110/220 VAC, which transform into 150/300 VDC, Type 2A was prominent among the others. Especially for the high power output DCM operations, the switching loss is less than 10% of the total loss as shown in Figure 17b. For now, Type 2A combines the low cost, high stability, and good power conversion efficiency, which may be the best choice among all cascode GaN HEMTs.

Type 2B cascode GaN HEMT, similar to Type 2A, relies on the NMOS to switch off the power module when the input voltage is disconnected. It will also need the replugging time of 1 s to drain out the charge in the parasitic gate–source capacitor through the reverse saturation current from D₂ in the power module, as shown in Figure 9. Type 2B cascode is good in the CCM operation, with low voltage input and low power output as shown in Figure 14a. However, Type 2B, unlike Type 2A which the NMOS stays on after NMOS turned on the first time, suffers from the instability of the switching since the NMOS may turn off at a certain time when D-mode GaN is turning off. This instability of the switching process discouraged the use of the Type 2B in the DCM operation since it can ring a high voltage higher than Type 2A, as shown in Figure 17b, when the power module is turning off.

6. Conclusions

Three different cascode GaN HEMT E-mode power modules are introduced in this paper. The power conversion capability on the flyback converter was compared. It is found that the use of innovative GaN-switching based cascode GaN HEMT can lead to the high efficiency for the DC/DC conversion of this form. Similar to the conventional cascode GaN HEMT, all the cascode topologies transform the normally on D-mode GaN HEMT into the normally off E-mode power module. The D-mode GaN HEMT is capable of 800 V breakdown voltage, which is proper for flyback converter application with 220 VAC and up to 50 VDC output voltage. Nevertheless, the innovative GaN-switching-based cascode GaN HEMT is a low cost power module which employs low cost MOSFET and diodes. However, the GaN-switching based cascode GaN HEMT still suffers from the replugging time to drain out the charges stored in the gate–source capacitor of the MOSFET. The replugging time can also be reduced by selecting diodes with suitable reverse saturation current. Certain circuit designs to reset the MOSFET may be necessary when the AC power source is unplugged frequently. For now, the 3C compliance or the data storage server array applications are not with considerable problem since the MOSFET in series with the GaN HEMT still performed as the current limiter, and the D-mode GaN HEMT with negative temperature coefficient on the current output will help the current limiting. For better power efficiency as well to reduce the replugging time, we have to minimize the parasitic capacitances as well as inductances. The power module has to be miniaturized. In the future, we will work on the circuit parameter optimization of Type 2A and reduce the size into a SiP (system in package) form, in which the gate drive may also be included.