Factorisation Path Based Refactorisation for High-Performance LU Decomposition in Real-Time Power System Simulation
Abstract
:1. Introduction
1.1. Motivation
1.2. Related Work
1.3. Contribution and Outline
2. Fundamentals
2.1. Real-Time Simulation Solution Procedure
- Time-varying matrix entries, e.g., time-varying conductance entries that correspond to a high-order nonlinear voltage-behind-reactance (VBR) synchronous machine model [25];
2.2. LU Decomposition Methods
- Preprocessing: Preprocessing involves steps for the scaling and ordering of the matrix. This improves the numerical properties of the matrix and the performance of the LU decomposition by reducing the fill-in (i.e., additional nonzero entries arising during the factorisation).
- Factorisation: The factorisation step performs the actual decomposition of the original matrix into its corresponding and matrices.
- Refactorisation: Refactorisation implies the simplification of the factorisation procedure if subsequent LU decompositions are computed. Optionally, it may involve the use of a partial refactorisation approach.
- Solution: The computation of the solution vector is commonly based on a forward/backward substitution approach that makes use of the decomposed matrix.
- Preprocessing: Optionally, SuperLU can determine diagonal scaling matrices for stability. It then proceeds to calculate the column ordering of the input matrix, which is determined to preserve sparsity (fill-in reduction).
- Factorisation: To compute a numeric factorisation with partial pivoting, the method aims to exploit the supernodal structure of the input matrices and calculates the LU decomposition using the scaling (optionally) and fill-in ordering matrices.
- Solution: To solve for the RHS, SuperLU uses forward/backward substitution.
- Preprocessing: KLU utilises the block triangular form (BTF) transformation, which ensures a zero-free diagonal and orders the matrix to a form in which the resulting matrix has smaller block matrices on its diagonal and zero entries below it. Then, the Approximate Minimum Degree Ordering Algorithm (AMD) is performed for fill-in reduction on each of these blocks.
- Factorisation: In the numerical procedure, KLU factorises each block independently with partial pivoting using the Gilbert–Peierls algorithm [28].
- Refactorisation: If one needs another factorisation of a matrix with different numerical values but the same symbolic pattern, KLU can perform factorisation without recomputing the fill-in reduction or partial pivoting.
- Solution: KLU successively solves for the unknown vector using forward/backward substitution starting at the lowest block.
- Preprocessing: NICSLU performs MC64 scaling, which places large values on the diagonal and enhances numerical stability. As opposed to KLU, AMD is then used on the entire matrix. As a final preprocessing step, static symbolic factorisation is performed to determine parallelisability. The decision of whether to use parallelisation is up to the user.
- Factorisation: In contrast to KLU, factorisation is performed on the entire matrix. The factorisation consists of two main steps: first, a symbolic factorisation to determine the resulting column structure; second, a numeric factorisation with partial pivoting using the Gilbert–Peierls algorithm.
- Refactorisation: Numeric factorisation of the whole matrix without partial pivoting reusing the scaling, permutation and pivoting choices can be conducted for different numerical values, but only for the same symbolic pattern.
- Solution: The RHS is solved using forward/backward substitution on the entire matrix.
3. High-Performance LU Decomposition
3.1. Partial Refactorisation Concept
3.2. Implementation
3.2.1. Partial Refactorisation in NICSLU
3.2.2. Integration into DPsim Real-Time Simulator
- The preprocessing step using the analyzePattern routine,
- the factorisation step using the factorize routine and
- the solution step using the _solve_impl routine.
4. Evaluation via Use Cases
4.1. Factorisation in Real-Time Simulation
4.2. Refactorisation in Real-Time Simulation
4.3. Refactorisation of Large-Scale Matrices
5. Conclusions and Outlook
Author Contributions
Funding
Institutional Review Board Statement
Informed Consent Statement
Data Availability Statement
Conflicts of Interest
Abbreviations
AMD | Approximate Minimum Degree Ordering Algorithm |
BTF | Block triangular form |
CSR | Compressed sparse row |
DAE | Differential-algebraic system of equations |
DCIM | Delayed-current injection method |
EMT | Electromagnetic transient |
HiL | Hardware-in-the-loop |
LES | Linear equation system |
MNA | Modified nodal analysis |
NR | Newton–Raphson |
ODE | Ordinary differential equation |
RHS | Right-hand side |
SFA | Shifted frequency analysis |
VBR | Voltage-behind-reactance |
References
- Zhang, P.; Marti, J.R.; Dommel, H.W. Shifted-Frequency Analysis for EMTP Simulation of Power-System Dynamics. IEEE Trans. Circuits Syst. I Regul. Pap. 2010, 57, 2564–2574. [Google Scholar] [CrossRef] [Green Version]
- Dinkelbach, J.; Nakti, G.; Mirz, M.; Monti, A. Simulation of Low Inertia Power Systems Based on Shifted Frequency Analysis. Energies 2021, 14, 1860. [Google Scholar] [CrossRef]
- Razik, L.; Schumacher, L.; Monti, A.; Guironnet, A.; Bureau, G. A comparative analysis of LU decomposition methods for power system simulations. In Proceedings of the 2019 IEEE Milan PowerTech, Milan, Italy, 23–27 June 2019; pp. 1–6. [Google Scholar]
- PEGASE Consortium. D4.1 Algorithmic requirements for simulation of large network extreme scenarios. 2011. [Google Scholar]
- Razik, L. High-Performance Computing Methods in Large-Scale Power System Simulation. Ph.D. Thesis, RWTH Aachen University, Aachen, Germany, 2020. [Google Scholar]
- Guironnet, A.; Saugier, M.; Petitrenaud, S.; Xavier, F.; Panciatici, P. Towards an Open-Source Solution using Modelica for Time-Domain Simulation of Power Systems. In Proceedings of the 2018 IEEE PES Innovative Smart Grid Technologies Conference Europe (ISGT-Europe), Sarajevo, Bosnia and Herzegovina, 21–25 October 2018. [Google Scholar] [CrossRef]
- Hindmarsh, A.C.; Brown, P.N.; Grant, K.E.; Lee, S.L.; Serban, R.; Shumaker, D.E.; Woodward, C.S. SUNDIALS: Suite of Nonlinear and Differential/Algebraic Equation Solvers. ACM Trans. Math. Softw. 2005, 31, 363–396. [Google Scholar] [CrossRef]
- Tostado-Véliz, M.; Kamel, S.; Jurado, F. Comparison of various robust and efficient load-flow techniques based on Runge–Kutta formulas. Electr. Power Syst. Res. 2019, 174, 105881. [Google Scholar] [CrossRef]
- Tostado-Véliz, M.; Kamel, S.; Jurado, F. Two Efficient and Reliable Power-Flow Methods with Seventh Order of Convergence. IEEE Syst. J. 2021, 15, 1026–1035. [Google Scholar] [CrossRef]
- Quintana-Ortí, E.S.; Van De Geijn, R.A. Updating an LU Factorization with Pivoting. ACM Trans. Math. Softw. 2008, 35. [Google Scholar] [CrossRef] [Green Version]
- Abusalah, A.; Saad, O.; Mahseredjian, J.; Karaagac, U.; Kocar, I. Accelerated Sparse Matrix-Based Computation of Electromagnetic Transients. IEEE Open Access J. Power Energy 2020, 7, 13–21. [Google Scholar] [CrossRef]
- Chan, S.M.; Brandwajn, V. Partial Matrix Refactorization. IEEE Trans. Power Syst. 1986, 1, 193–199. [Google Scholar] [CrossRef]
- Tinney, W.F.; Brandwajn, V.; Chan, S.M. Sparse Vector Methods. IEEE Trans. Power Appar. Syst. 1985, PAS-104, 295–301. [Google Scholar] [CrossRef]
- Chen, X.; Wang, Y.; Yang, H. NICSLU: An Adaptive Sparse Matrix Solver for Parallel Circuit Simulation. Comput.-Aided Des. Integr. Circuits Syst. IEEE Trans. 2013, 32, 261–274. [Google Scholar] [CrossRef]
- Demmel, J.W.; Eisenstat, S.C.; Gilbert, J.R.; Li, X.S.; Liu, J.W.H. A Supernodal Approach to Sparse Partial Pivoting. SIAM J. Matrix Anal. Appl. 1999, 20, 720–755. [Google Scholar] [CrossRef]
- Davis, T.A.; Natarajan, E.P. Algorithm 907: KLU, A Direct Sparse Solver for Circuit Simulation Problems. ACM Trans. Math. Softw. 2010, 37, 1–17. [Google Scholar] [CrossRef]
- Eigen Developers. Eigen. Available online: https://eigen.tuxfamily.org/ (accessed on 15 October 2021).
- Mirz, M.; Dinkelbach, J.; Monti, A. DPsim—Advancements in Power Electronics Modelling Using Shifted Frequency Analysis and in Real-Time Simulation Capability by Parallelization. Energies 2020, 13, 3879. [Google Scholar] [CrossRef]
- Dufour, C.; Jalili-Marandi, V.; Bélanger, J. Real-Time Simulation Using Transient Stability, ElectroMagnetic Transient and FPGA-Based High-Resolution Solvers. In Proceedings of the 2012 SC Companion: High Performance Computing, Networking Storage and Analysis, Salt Lake City, UT, USA, 10–16 November 2012; pp. 283–288. [Google Scholar] [CrossRef]
- Ho, C.W.; Ruehli, A.; Brennan, P. The modified nodal approach to network analysis. IEEE Trans. Circuits Syst. 1975, 22, 504–509. [Google Scholar] [CrossRef] [Green Version]
- Dommel, H.W. Digital Computer Solution of Electromagnetic Transients in Single-and Multiphase Networks. IEEE Trans. Power Appar. Syst. 1969, PAS-88, 388–399. [Google Scholar] [CrossRef]
- Kundur, P.; Balu, N.J.; Lauby, M.G. Power System Stability and Control; McGraw-Hill: New York, NY, USA, 1994. [Google Scholar]
- Dufour, C. Highly Stable Rotating Machine Models Using the State-Space-Nodal Real-Time Solver. In Proceedings of the 2018 IEEE Workshop on Complexity in Engineering (COMPENG), Florence, Italy, 10–12 October 2018; pp. 1–10. [Google Scholar] [CrossRef]
- Dommel, H.W. EMTP Theory Book; B.P.A: Portland, OR, USA, 1986. [Google Scholar]
- Wang, L.; Jatskevich, J. A Voltage-Behind-Reactance Synchronous Machine Model for the EMTP-Type Solution. IEEE Trans. Power Syst. 2006, 21, 1539–1549. [Google Scholar] [CrossRef]
- Chua, L.O. Computer-Aided Analysis of Electronic Circuits: Algorithms and Computational Techniques, 1st ed.; Prentice Hall: Englewood Cliffs, NJ, USA, 1975. [Google Scholar]
- Li, X.S.; Demmel, J.W.; Gilbert, J.R.; Grigori, L.; Shao, M.; Yamazaki, I. SuperLU User’ Guide; Lawrence Berkeley National Laboratory: Berkeley, CA, USA, 2011.
- Gilbert, J.R.; Peierls, T. Sparse Partial Pivoting in Time Proportional to Arithmetic Operations. SIAM J. Sci. Stat. Comput. 1988, 9, 862–874. [Google Scholar] [CrossRef] [Green Version]
- Chen, X.; Wang, Y.; Yang, H. An adaptive LU factorization algorithm for parallel circuit simulation. In Proceedings of the 17th Asia and South Pacific Design Automation Conference, Sydney, NSW, Australia, 30 January–2 February 2012; pp. 359–364. [Google Scholar]
- NICSLU Developers. NICSLU—Parallel Sparse Solver for Circuit Simulation. Available online: https://github.com/chenxm1986/nicslu (accessed on 15 November 2021).
- DPsim Developers. DPsim: A Real-Time Power System Simulator. Available online: https://dpsim.fein-aachen.org (accessed on 15 October 2021).
- Li, X.S. An overview of SuperLU: Algorithms, implementation, and user interface. ACM Trans. Math. Softw. 2005, 31, 302–325. [Google Scholar] [CrossRef]
- Dynaωo Developers. Dynaωo. Available online: https://dynawo.github.io (accessed on 12 November 2021).
No. | Power Grid | K | N | NNZ | d [%] |
---|---|---|---|---|---|
(1) | Regional EHV/HV with SL | 1000 | 11,003 | 44,623 | 0.036 |
(2) | French EHV with SL | 2000 | 26,432 | 92,718 | 0.013 |
(3) | French EHV/Regional HV with SL | 4000 | 56,564 | 183,278 | 0.0057 |
(4) | French EHV with VDL | 2000 | 60,236 | 188,666 | 0.0051 |
(5) | F. + one neighbour EHV, SL | 3000 | 47,900 | 20,5663 | 0.0089 |
(6) | F. + one neighbour EHV, VDL | 3000 | 75,300 | 266,958 | 0.0047 |
(7) | F. + neighb. countries EHV, SL | 7500 | 70,434 | 267,116 | 0.0054 |
(8) | F. EHV + regional HV, SL | 4000 | 90,940 | 316,280 | 0.0038 |
(9) | F. EHV + regional HV, VDL | 4000 | 197,288 | 586,745 | 0.0015 |
(10) | F. + neighb. countries EHV, VDL | 7500 | 220,828 | 693,442 | 0.0014 |
Publisher’s Note: MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations. |
© 2021 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https://creativecommons.org/licenses/by/4.0/).
Share and Cite
Dinkelbach, J.; Schumacher, L.; Razik, L.; Benigni, A.; Monti, A. Factorisation Path Based Refactorisation for High-Performance LU Decomposition in Real-Time Power System Simulation. Energies 2021, 14, 7989. https://doi.org/10.3390/en14237989
Dinkelbach J, Schumacher L, Razik L, Benigni A, Monti A. Factorisation Path Based Refactorisation for High-Performance LU Decomposition in Real-Time Power System Simulation. Energies. 2021; 14(23):7989. https://doi.org/10.3390/en14237989
Chicago/Turabian StyleDinkelbach, Jan, Lennart Schumacher, Lukas Razik, Andrea Benigni, and Antonello Monti. 2021. "Factorisation Path Based Refactorisation for High-Performance LU Decomposition in Real-Time Power System Simulation" Energies 14, no. 23: 7989. https://doi.org/10.3390/en14237989
APA StyleDinkelbach, J., Schumacher, L., Razik, L., Benigni, A., & Monti, A. (2021). Factorisation Path Based Refactorisation for High-Performance LU Decomposition in Real-Time Power System Simulation. Energies, 14(23), 7989. https://doi.org/10.3390/en14237989