An Efficient Non-Inverting Buck-Boost Converter with Improved Step Up/Down Ability

Abstract

In this article, a new non-inverting buck-boost converter with superior characteristics in both bucking and boosting is presented. The proposed converter has some distinct features, such as high step-up/-down ability and low voltage/current stress on its switching devices. The voltage gain of the proposed converter is double the reported value for the traditional buck-boost converter. Although it has three switches, the three switches operate simultaneously, hence no dead-time is required. Two out of the three switches are under voltage stress equal to half of the output voltage. The overall efficiency of the system is promising because of the ability to select devices with low voltage drops. Converter analysis and steady-state performance in both continuous conduction mode (CCM) and discontinuous conduction mode (DCM) are presented in detail. A 1 kW hardware prototype of the converter was implemented in the laboratory; with a step-up ratio of 3.5 and 1 kW power, the measured efficiency is above 95.4%, and with step-up ratio 8, it is around 91.5%.

1. Introduction

Traditional buck-boost converters, CUK and SEPIC, are able to buck or boost input voltage; however, their bucking or boosting abilities are limited, and they have high stress on their switching devices, hence their efficiency and applications are limited [1,2,3,4,5,6]. In order to improve step-up/-down abilities, a group of power converters have been developed in the literature [7,8,9,10,11,12,13,14,15,16,17]. The topology proposed in [7] is a modification of the traditional buck-boost converter with improved voltage gain, but it has an inverted output and two of the switching devices are under high voltage stress. A high gain with continuous input current buck-boost converter has been proposed in [7,8], but the converter is inverted and includes many storage devices. In [9], a novel buck-boost converter is proposed with lower component stresses and less storage devices, However, the converter has limited voltage gain; high ripple; and the converter switches operate in a complementary manner, which increases dead-time and switching protection issues.

The quadratic voltage gain buck-boost converters developed in [10,11,12] provide good performance in step-up mode, but their step-down ability is very limited.

In [13,14], semi-quadratic buck-boost converters are proposed. Despite their improved performance in both bucking and boosting modes, there is no common ground and the input current is discontinuous. A quasi-Y source-based buck-boost dc–dc converter is introduced in [15,16]. This converter achieved a very high voltage gain using two inductors. Nevertheless, the severe slope of the voltage gain ratio makes controlling the converter very difficult.

In order to achieve higher voltage and gain and sustain higher efficiency at a wide range of input voltage change, this paper presents a new high-gain non-inverting buck-boost converter. The structure proposed has different merits, such as non-inverting, high voltage gain, reduced components’ stresses, and the ability to sustain better efficiency at wide voltage and load ranges.

The rest of the paper is organized as follows: Section 2 discusses the principle of operation and analysis of the proposed converter; Section 3 presents the experimental results of the converter; and finally, Section 4 presents the conclusions.

2. Proposed Buck-Boost Dc–Dc Converter

The configuration of the proposed buck-boost dc–dc converter is illustrated in Figure 1 [17]. The structure is implemented using three power switches (S₁, S₂, S₃), two diodes (D₁, D_o), two inductors (L₁, L₂), and an output capacitor (C_o). The three switches are triggered on and off simultaneously, and the diodes operate as freewheeling diodes. The two inductors charge in parallel and discharge in series.

The converter is able to operate in continuous conduction mode (CCM) and discontinuous conduction mode (DCM). Both modes of operation will be considered in the following sections.

2.1. Continuous Conduction Mode

In order to simplify the analysis of the CCM mode, two assumptions are considered in the forthcoming analysis:

✓ 

Capacitor voltage ripple is very small compared with the voltage itself, thus it could be neglected.

✓ 

Inductor current ripple is negligible because of its very small value.

✓ 

All semiconductor devices are ideal.

The converter power switches are triggered ON and OFF simultaneously, hence the converter will have two operating modes; see Figure 2a,b. Typical waveforms of the converter in CCM are shown in Figure 3.

Mode I [0-DT_S]: In this time period, switches (S₁, S₂, S₃) are turned ON, while diodes (D₁, D_o) are turned OFF. This mode is illustrated in Figure 2a. As can be seen from the figure, the two inductors charge in parallel from the source. Applying Kirchhoff voltage law (KVL) and Kirchhoff current law (KCL) to Figure 2a, the following equations are deduced:

$$v_{L1}=v_{L2}=V_{dc}$$

(1)

$$i_c=-\frac{V_o}{R}$$

(2)

$$i_d=0$$

(3)

Mode II [DT_S-T_S]: In this time period, switches (S₁, S₂, S₃) are turned OFF and, consequently, diodes (D₁, D_o) are turned ON to provide a freewheeling path for the current. This mode is illustrated in Figure 2b. As can be investigated from the figure, the two inductors discharge their energies to the load in series. Applying Kirchhoff voltage law (KVL) and Kirchhoff current law (KCL) to Figure 2b, the following equations are deduced:

$$v_L=v_{L1}=v_{L2}$$

(4)

$$2v_L=-V_o$$

(5)

$$i_C=I_L-\frac{V_o}{R}$$

(6)

$$i_d=I_L$$

(7)

The steady-state voltage gain of the proposed converter could be deduced from the analysis of the two modes of operation by applying voltage second balance, and the voltage gain of the proposed converter is as follows:

$$\frac{V_o}{V_{dc}}=M=\frac{2D}{\left(1-D\right)}$$

(8)

where $v_{L1}$, $v_{L2}$, $V_{dc}$, $V_o$, $I_L$, $i_C$, $i_d$, $M$, and $D$ are inductor L₁ voltage, inductor L₂ voltage, input voltage, output voltage, inductor current, capacitor current, diode current, voltage gain, and duty cycle, respectively.

2.2. Discontinuous Conduction Mode

The discontinuous conduction mode typically occurs with large inductor current ripple in a converter operating at light load and containing current unidirectional switches. However, some converters are purposely designed to operate in DCM. The proposed converter will have three modes of operation while operating in DCM; see Figure 2a–c. The typical converter waveform while operating in DCM is illustrated in Figure 4.

Mode I and Mode II, which were discussed in the previous section, are similar to CCM analysis.

Mode III: In this interval, both the power switches and diodes are turned off. The inductors’ currents are zero, as illustrated in Figure 2c.

$$v_L=0$$

(9)

$$i_C=\frac{V_o}{R}$$

(10)

$$i_d=0$$

(11)

Applying inductor volt-second balance in Equations (1), (5), and (9), the relation between input and output voltage is obtained:

$$D_1\ast v_{dc}=D_2\ast v_o$$

(12)

The duty cycle D₂ is an unknown, so a second equation is needed to eliminate D₂. Capacitor charge-balance is used to obtain the second equation. The average of the diode current is equal to the output current:

$$\langle i_d\rangle =\frac{V_o}{R}$$

(13)

A sketch of the inductor and diode currents in DCM is illustrated in Figure 5a,b. The dc component of the diode current is given by

$$\langle i_d\rangle =\frac{1}{T_S}{{\displaystyle \int }}_0^{T_S}{i}_d\left(t\right)dt$$

(14)

The peak diode current could be obtained from the graph as

$$i_{pk}=\frac{V_o}{2L}\ast D_1\ast T_S$$

(15)

Solving Equations (13)–(15), the second required equation is obtained as

$$\langle i_d\rangle =\frac{1}{2}\ast D_2\ast T_S\ast \frac{V_o}{2L}\ast D_1=\frac{V_o}{R}$$

(16)

Let

$$k=\frac{2L}{R{T}_S}$$

(17)

Then

$$D_2=2\ast k/D_1$$

(18)

Finally, the converter voltage gain in DCM operation is given as

$$\frac{V_o}{V_{dc}}=M=\raisebox{1ex}{$D_1^2$}\!\left/ \!\raisebox{-1ex}{$\left(2\ast K\right)$}\right.$$

(19)

where $D_1$, $D_2$, $T_S$, and R₀ are periods when the switches are conducting, periods when the diode is conducting, switching time, and load resistance, respectively.

The boundary for CCM and DC operation can be obtained by relating inductor current and inductor ripple

$$I_L>\Delta i_L\hspace{1em}\mathrm{For}\mathrm{CCM}$$

(20)

$$I_L<\Delta i_L\hspace{1em}\mathrm{For}\mathrm{DCM}$$

(21)

Substituting CCM solutions for $I_L$ and $\Delta i_L$ in (20)

$$\frac{V_{dc}}{R}\ast {\left(\frac{2D}{1-D}\right)}^2>\frac{V_{dc}}{2L}\ast D{T}_S$$

(22)

Equation (22) could be rearranged to

$$\frac{2L}{R{T}_S}=K>D\ast {\left(\frac{2D}{1-D}\right)}^2$$

(23)

Hence

$$K_{cri}=D\ast {\left(\frac{2D}{1-D}\right)}^2$$

(24)

where $K_{cri}$ is the critical boundary between CCM and DCM.

According to the above analysis, the converter can operate on CCM or DCM based on the operating conditions; in order to avoid such conditions, accurate design of the converter must be considered. Figure 6 represents the boundary condition between CCM and DCM at different duty cycles and different power while the output voltage is fixed at 350 V.

2.3. Switches’ and Diodes’ Voltage Stresses

Voltage and current stress are important parameters in designing and selecting circuit parameters, and the proposed converter switching elements’ stress is discussed below.

Switches S₁, S₂, and S₃ are triggered in a simultaneous manner, but their ratings are different. The voltage stress of switch S₁ is equal to

$$V_{dsS1}=V_{dc}$$

(25)

The current stress of switch S₁ is given by

$$I_{S1}=2\ast I_L$$

(26)

Switches S₂ and S₃ face similar voltage and current stress, as follows:

$$V_{dsS2}=V_{dsS3}=\raisebox{1ex}{$V_o$}\!\left/ \!\raisebox{-1ex}{$2$}\right.$$

(27)

$$I_{S2}=I_{S3}=I_L$$

(28)

Diodes D₁ and D_o work as freewheeling diodes and are activated in complementary manners to the switches. The voltage and current stress of both diodes are given by

$$V_{d1}=V_{dc}$$

(29)

$$I_{d1}=I_L$$

(30)

$$V_{do}=V_{dc}+V_o$$

(31)

$$I_{S2}=I_L$$

(32)

A depiction of the devices’ normalized voltage stresses with different voltage gain is illustrated in Figure 7. In Figure 7, the voltage stress is normalized to the input voltage.

2.4. Components’ Design

The design of the circuit parameters, inductors, and capacitor is obtained from the steady-state analysis performed in the previous sections. Utilizing inductor volt-second balance and capacitor charge, the designs of parameters are as follows:

2.4.1. Inductors’ Design

Inductors’ selection is based on the required ripple of its current. The inductor current ripple in CCM is drawn in Figure 8a and is given by

$$\Delta i_L=\Delta i_L^{on}=\Delta i_L^{off}=\frac{V_{dc}D{T}_S}{L}=\frac{V_o(1-D)T_S}{2L}$$

(33)

This equation is valid in both CCM and DCM. By defining the required amount of ripple, the inductor value could be defined as follows:

$$L=\raisebox{1ex}{$\left(V_o\ast \left(1-D\right)\right)\ast T_S$}\!\left/ \!\raisebox{-1ex}{$\left(2\ast \Delta i_L\right)$}\right.$$

(34)

Based on Equation (29), there is a dependency between inductance L and duty cycle D. In order to avoid any misoperation of the converter, we design the inductance based on the extreme condition that the current ripple at the extreme scenario does not exceed the required ripple and when duty cycle below the ripple will be below the required level.

Let us assume the required ripple $\Delta i_L$ is 10%, then we can calculate L at the duty cycle around 0.82. Then, when the duty cycle is lower than 0.85, the ripple will be less than 10%.

2.4.2. Capacitors’ Design

The output capacitor value is selected based on the amount of voltage ripple acceptable in the output voltage. The output capacitor voltage waveform is illustrated in Figure 8b and the ripple equation is as follows:

$$\Delta v=\Delta v_c^{on}=\Delta v_o^{off}=\frac{(V_o-IL)\left(1-D\right)T_S}{RC}=\frac{V_{o}D{T}_S}{RC}$$

(35)

This equation is valid in both CCM and DCM. By defining the required amount of ripple, the capacitor value could be defined as follows:

$$C_o=\raisebox{1ex}{$\left(V_o\ast D\ast T_S\right)$}\!\left/ \!\raisebox{-1ex}{$\left(\Delta v\ast R\right)$}\right.$$

(36)

where $\Delta i_L$, $\Delta i_L^{on}$, $\Delta i_L^{off}$, $L$, $\Delta v$, $\Delta {\mathrm{v}}_c^{on}$, $\Delta {\mathrm{v}}_o^{off}$, and $C$ are inductor current ripple, inductor ripple while the inductor is charging, inductor ripple while the inductor is discharging, inductor value, capacitor ripple, capacitor ripple while the capacitor is charging, capacitor ripple while the capacitor is discharging, and capacitor value, respectively.

Based on Equation (30), there is a dependency between capacitance C and duty cycle D. In order to avoid any misoperation of the converter, we design the capacitance based on the extreme condition that the voltage ripple at the extreme scenario does not exceed the required ripple and when duty cycle below the ripple will be below the required level

Let us assume the required ripple $\Delta v$ is 10%, then we can calculate C at the duty cycle around 0.82. Then, when the duty cycle is lower than 0.85, the ripple will be less than 10%.

2.4.3. Comparative Study

Converter performance mainly depends on the input voltage, input power, and step-up ratio. The converter voltage gain is affected by the loading profile and supply voltage. In Figure 9a, the input voltage is fixed at 150 V, while different loading profiles are applied; at light load, the converter conversion ability is higher than at heavy loading. The second case study is illustrated in Figure 9b, where load profile is fixed with different supply voltages; as the supply voltage increases, the step-up/-down ability increases.

However, in both case studies, the differences in the voltage gain do not have a very high ratio.

Converter efficiency depends on many factors such as the load profile, source voltage, and voltage gain. In the scenario illustrated in Figure 9c, the load profile is fixed while both voltage gain and source voltage are variable. In buck mode, as the source voltage increases and the bucking ratio is lowered, the converter demonstrates the highest efficiency, while with lower input voltage and a higher bucking ratio, the converter efficiency is low. During boosting mode, as source voltage increases, efficiency increases too.

Another case study is considered in Figure 10a, where input voltage is set to 150 V, while load profile is variable and efficiency is measured at different voltage gains. With heavy loading, the converter demonstrates lower efficiency than with a medium or moderate loading profile. A comparison between the proposed converter and different converters reported in the literature is illustrated in

Table 1. Voltage gain and component stress comparison.

Converter Topology	Gain M = Vo/Vin	Components’ Count				Switches’ and Diodes’ Voltage Stress	Switches’ and Diodes’ Current Stress
		Switch	Diode	L	C
Buck-Boost [18]	(D/(1-D))	1	1	1	1	S:Vo	IL
						D:(Vo+Vin)	IL
Non-Inverting [19]	(D/(1-D))	2	2	1	1	S1:Vin	IL
						S2:Vo	IL
						D1:Vin	IL
						Do:Vo	IL
Cuk [5]	(D/(1-D))	1	2	2	1	S1:Vin/(1-D)	IL
						D1:Vin	IL
						Do:Vo	IL
SEPIC [19]	(D/(1-D))	1	1	2	2	S1:Vo+Vin	2IL
						D1:Vo+Vin	IL
SIBBC [20]	2D/(1-D)	1	4	2	1	S1:Vo+Vin	2IL
						D1:Vin	IL
						D2:Vo/2	IL
						D3:Vo/2	IL
						Do:Vo+Vin	IL
Lakshmi [21]	(1+D1)/(1-D1-D2)	3	2	2	1	S1:(Vo+Vin)/2	IL
						S2:(Vo+Vin)/2	IL
						S3:Vo	IL
						D1:Vo	IL
						Do:Vo+Vin	IL
[22]	2D/(1-D)2	2	3	2	3	S1:1/(1-D)*Vin	IL
						S2:Vin *(1+D)/(1-D)2	IL
						D1:Vin/(1-D)	IL
						D2:Vin/(1-D)	IL
						Do:Vo+Vin/(1-D)	IL
[23]	D2/(1-D)2	2	2	2	2	S1:1/(1-D)*Vin	2IL
						S2:Vin *D/(1-D)2	IL
						D1:Vin/(1-D)	IL
						D2:Vin*D/(1-D)2	IL
Proposed	2D/(1-D)	3	2	2	1	S1:Vin	2IL
						S2:Vo/2	IL
						S3:Vo/2	IL
						D1:Vin	IL
						Do:Vo+Vin	IL

. In the voltage gain comparison illustrated in Figure 10b, both the proposed converter and switched inductor buck-boost converter have similar step-up/-down ability, but the proposed converter has higher efficiency; see Figure 10c.

3. Experimental Verification

This section provides the experimental results of the developed system, and the parameters used to build the prototype are illustrated in

Table 2. Hardware prototype specifications.

Parameter	Value
Input voltage range [V]	33–150
P [W]	700 W
Fs Switching Frequency	30 kHz
Switches S1, S2, S3	IMZ120R030M1HXKSA1
Diodes D1, Do	DPG10I300PA
Inductors L1 = L2	1 mH
Capacitor Co	320 µF

. A photo of the proposed system is shown in Figure 11.

A case study where the duty cycle is set to 0.6 with 30 V input voltage is illustrated in Figure 12. Three switches are operating in synchronous manner, hence the gate source pulses for the three switches are the same as illustrated in Figure 12a. Diodes D₁ and D_o are operating as freewheeling diodes. The cathode–anode voltages of the two diodes are illustrated in Figure 12b. The input current is the sum of the two inductors’ currents when the switches are on and zero when the switches are off, and the input capacitor smoothens the input current. The drain source voltages of the three switches are illustrated in Figure 12c. Switches S2 and S3 face the same voltage stress and carry the same current.

Figure 12d illustrates switch S₁ current, which is equal to the sum of the two inductors’ currents. Switch S₂ current is illustrated in Figure 12e, which is equal to the inductor current. The output diode current is illustrated in Figure 12f, where spikes are noted in the switches and diode currents because of a problem in the used probe; however, it does not exist in real current as there are no spikes in the measured voltages.

A boosting case study is considered in Figure 13, where the input voltage is 25 V and the output voltage generated is around 38 V, and a bucking case study is illustrated in Figure 14, where the input voltage is 23 V, output voltage is 9.25 V, duty cycle is 0.2244, and voltage gain is 0.4.

The converter voltage gain was measured experimentally, and the theoretical and measured voltage gains of the converter with varying duty cycles are illustrated in Figure 15. For comparison purposes, three prototypes were built in the laboratory for the traditional buck-boost, non-inverting buck-boost, and proposed converter. The three prototypes were built using the same parameters as in Table 2. In the first case study, which is illustrated in Figure 16, the input voltage is set to 100 V and the step ratio is fixed at 3.7. For such a step-up ratio, the proposed converter requires a duty cycle of 0.68, while the conventional and non-inverting buck-boost converters both require a duty cycle of 0.8.

In this case study, the non-inverting converter demonstrates the highest efficiency, while at high power, both the proposed and conventional converter have the same efficiency. In the second case study, which is illustrated in Figure 17, the input voltage is fixed at 30 V and the step-up ratio is 8. The efficiency of the proposed converter and the non-inverting converter is comparable, but with the increase in power (over 300 W), the proposed converter demonstrates the highest efficiency.

The last case study demonstrates step-down comparison. In Figure 18, the input voltage is fixed at 150 V and the step-down ratio is 3. The non-inverting converter demonstrates the lowest efficiency. The proposed converter and the conventional converter demonstrate comparable efficiency at low power, but with the increase in input power, the proposed converter demonstrates the highest efficiency.

4. Conclusions

In this paper, a new non-inverting high-gain buck-boost structure is developed with improved step-up/-down ability. The performance of the converter in both CCM and DCM is studied and analyzed. The design of the converter elements is investigated and described. The operating conditions and voltage/current stress of each device are studied. Based on the performed analysis, the proposed converter devices are under low voltage and current stress compared with other buck-boost converters. A 700 W prototype was built for the converter to investigate its performance experimentally. The efficiency of the proposed converter is measured at different voltage gains and compared with the traditional buck-boost converter.

The theoretical and measured voltage gain matched. While working in step-up, the converter demonstrated better performance at high power. The peak measured efficiency of the converter at a step-up ratio of 3.7 was 95.4%.