Capacitor Voltage Balancing of a Grid-Tied, Cascaded Multilevel Converter with Binary Asymmetric Voltage Levels Using an Optimal One-Step-Ahead Switching-State Combination Approach ^†

Abstract

This paper presents a novel capacitor voltage balancing control approach for cascaded multilevel inverters with an arbitrary number of series-connected H-Bridge modules (floating capacitor modules) with asymmetric voltages, tiered by a factor of two (binary asymmetric). Using a nearest-level reference waveform, the balancing approach uses a one-step-ahead approach to find the optimal switching-state combination among all redundant switching-state combinations to balance the capacitor voltages as quickly as possible. Moreover, using a Lyapunov function candidate and considering LaSalle’s invariance principle, it is shown that an offline calculated trajectory of optimal switching-state combinations for each discrete output voltage level can be used to operate (asymptotically stable) the inverter without measuring any of the capacitor voltages, achieving a novel sensorless control as well. To verify the stability of the one-step-ahead balancing approach and its sensorless variant, a demonstrator inverter with 33 levels is operated in grid-tied mode. For the chosen 33-level converter, the NPC main-stage and the individual H-bridge modules are operated with an individual switching frequency of about 1 kHz and 2 kHz, respectively. The sensorless approach slightly reduced the dynamic system response and, furthermore, the current THD for the chosen operating point was increased from $3.28$ to $4.58$ in comparison with that of using the capacitor voltage feedback.

1. Introduction

Multilevel converters (MLC) are commonly used for high voltage applications in power systems [1,2] or, sometimes, these are even suggested for large electric drives [3,4]. Lately, multilevel inverters are gaining in interest for low voltage applications ($V<1\mathrm{k}\mathrm{V}$) due to their advantages in comparison to two-level converters, such as fault-tolerant operation capability [5,6], reduced common mode noise emissions [7,8] and the application of cheap, energy efficient low-voltage MOSFETs [9,10,11].

In [12,13,14], the topology of a cascaded H-bridge or a hybrid MLC (NPC mainstage) is shown. The additional series-connected H-bridges should help to lower the amount of output voltage harmonics and, thus, to reduce the size of the passive components, such as the grid or EMI-filter, or to improve the output current quality. To properly operate an MLC with capacitor modules, the capacitor voltages must be balanced. Therefore, several balancing algorithms can be found for symmetric MLCs [15,16,17,18,19]. As for example described in [15], self-balancing is typically achieved when using phase-shifted PWM, which introduces additional differential mode harmonics, lowering the current THD. Using asymmetric DC link voltage levels for the series-connected H-bridges can increase the output waveform’s quality, whereas the possibility to balance the capacitor voltages is compromised [14,20,21]. As stated in [14,21], the charge balance control for an asymmetric inverter with a voltage ratio of three cannot be achieved. To overcome this problem, only isolated voltage sources, charged from the mains, such as described in [22], or supplied by additional DC converters, as shown in [23], could be used. This approach requires a rectifier stage or a DC converter for each H-bridge module, introducing additional system costs. The authors of [24] suggest to replace only a limited selection of capacitor modules by additional isolated voltage sources, acting as charge buffers. Similarly, in [14,25,26] it is suggested to combine a number of redundant high and low resolution cells, which help to maintain the capacitor charge balance, whereas the number of output levels is reduced.

In contrast, to maintain a high number of output levels and to properly balance the individual capacitor voltages, an asymmetric voltage grading by a factor of two (binary asymmetric) is suggested as a compromise in [12,27,28,29,30]. As described in [12,28], a predetermined switching scheme relative to the modulation index and the displacement power factor can be used to maintain the capacitor charge balance when using a voltage grading ratio of two. However, in [28] only one capacitor module is considered and a predetermined switching scheme, as in [12], requires a large memory for the lookup table. In [31,32,33] it is shown that a predetermined switching pattern can be even used to operate the inverter without measuring the capacitor voltages. Nonetheless, in [31,32,33] only a symmetric MLC is considered. In contrast, the authors of [29] suggest a self-balancing modulation scheme for binary asymmetric MLCs without measuring (sensorless) the floating capacitors’ voltages. The suggested modulation scheme in [29] alternatively utilizes redundant switching-sate combinations, referred to as cell-voltage combinations. When using the approach in [29] with nearest-level control, the capacitors’ charges are balanced over several electrical fundamental periods and, thus, according to [30], big capacitors are required. Therefore, in [29] the binary asymmetric inverter is operated with PWM and, thus, the provided solution actually resembles a generic self-balancing approach, typically achieved phase-shifted PWM [15].

Research Contribution and Scope

As an extended post-conference article of [34], the research contribution of this paper is two-fold. First, a novel balancing algorithm for the capacitor voltages of a binary asymmetric cascaded multilevel inverter is derived. The suggested algorithm uses an optimal, one-step-ahead switching-state combination approach to balance the capacitor voltages as quickly as possible. In comparison to that of the methods available in [14,15,16,17,18,24,28,29,30], the presented algorithm utilizes a low switching frequency (couple of $\mathrm{k}$$\mathrm{Hz}$) and it achieves a quick dynamic response without requiring any additional hardware. Moreover, it can be easily applied to higher level asymmetric MLCs operated with nearest-level control (NLC). Second, with the help of a Lyapunov function, based on the energy stored in the grid filter and the capacitor modules, and considering LaSalle’s invariance principle, it is shown that an offline calculated trajectory of optimal switching-state combinations for each discrete output voltage level can be used to operate (asymptotically stable) the inverter without measuring any of the capacitor voltages, achieving a novel self-balancing approach as well. In comparison to that of the sensorless approach in [29], the capacitance requirement according to [30] for NLC is reduced and only a small lookup table is required.

To experimentally verify the effectiveness of the optimal, one-step-head switching-state combination approach and its sensorless variant, a demonstrator inverter from Imperix Ltd. and a simple, inductive grid filter is used. The setup is operated in grid-tied operation feeding active power to the grid. Within the scope of this paper, the converter and the grid filter design is not considered, since the major focus lies on the voltage balancing algorithm.

2. Asymmetric Cascaded Multilevel Converter Basics

The topology of a grid-connected, asymmetric, hybrid multilevel converter based on an NPC main stage and n cascaded H-bridges, can be seen in Figure 1. Due to the voltage grading of adjacent converter modules, this topology is referred to as exponential modular multilevel converter (EMMC) in [27]. Using an NPC mainstage configuration, the depicted single-phase EMMC can be easily extended to a three-phase converter. The 800 $\mathrm{V}$ NPC mainstage could be replaced by a 400 $\mathrm{V}$ H-bridge stage. Then, the converter would resemble a generic cascaded H-bridge converter with asymmetric capacitor voltages. Therefore, the presented theory can be easily applied to different variants of cascaded or hybrid multilevel inverters.

For simplicity, a lossy L-filter with an inductance $L_{\mathrm{filter}}$ and a series resistance $R_{\mathrm{filter}}$ is chosen as a grid-filter within the scope of this paper’s analysis. Alternatively to a pure inductive filter, an LCL-filter could be chosen, as for example described in [35,36]. The DC link voltage $V_{\mathrm{DC}}$ must be larger than the peak value of the grid voltage ($V_{\mathrm{AC},\mathrm{pk}}=\sqrt{2}\times 230\mathrm{V}$) to control both the active and the reactive power flow. For example, for a sufficient control margin, it might be suitable to chose a DC link voltage of $V_{\mathrm{DC}}=350\mathrm{V}$. To charge up the capacitors to the their desired reference voltages, a charging resistor $R_{\mathrm{charging}}$ is initially used. During normal operation, the charging resistor $R_{\mathrm{charging}}$ is bypassed.

2.1. Switching-States

The semiconductor switches of the main stage (NPC module) are operated in pairs and only adjacent switches should be activated at the same time. If three switches in series are activated, as for example $S_{1,\mathrm{NPC}}$, $S_{2,\mathrm{NPC}}$ and $S_{3,\mathrm{NPC}}$, one DC source is short-circuited. Therefore, the switching-state of the NPC main stage relative to the individual switches’ states can be expressed as

$$S_{\mathrm{NPC}}=\{1,0,-1\}=S_{1,\mathrm{NPC}}{S}_{2,\mathrm{NPC}}-S_{3,\mathrm{NPC}}{S}_{4,\mathrm{NPC}}$$

(1)

and, thus, the output voltage of the NPC stage becomes

$$v_{\mathrm{NPC}}=V_{\mathrm{DC}}{S}_{\mathrm{NPC}}.$$

(2)

The nominal reference voltages of the series-connected H-bridges are tiered by a factor of two. Similar to the NPC module, the switches of each H-bridge are operated in pairs. If the two upper ($S_{1,{\mathrm{HB}}_{\mathrm{i}}}$ and $S_{3,{\mathrm{HB}}_{\mathrm{i}}}$) or the two lower switches ($S_{2,{\mathrm{HB}}_{\mathrm{i}}}$ and $S_{4,{\mathrm{HB}}_{\mathrm{i}}}$) are activated, the voltage source (capacitor module) is bypassed. If the switches are operated diagonally, the corresponding voltage source (capacitor module) is inserted in forward ($S_{2,{\mathrm{HB}}_{\mathrm{i}}}$ and $S_{3,{\mathrm{HB}}_{\mathrm{i}}}$) and reverse ($S_{1,{\mathrm{HB}}_{\mathrm{i}}}$ and $S_{4,{\mathrm{HB}}_{\mathrm{i}}}$) direction into the phase strand, respectively. Consequently, the switching-state of each H-bridge relative to the individual switches’ states, can be expressed as

$$S_{{\mathrm{HB}}_{\mathrm{i}}}=\{1,0,-1\}=S_{2,{\mathrm{HB}}_{\mathrm{i}}}{S}_{3,{\mathrm{HB}}_{\mathrm{i}}}-S_{1,{\mathrm{HB}}_{\mathrm{i}}}{S}_{4,{\mathrm{HB}}_{\mathrm{i}}}$$

(3)

which can be used to express the output voltage of each H-bridge according to

$$v_{\mathrm{H}{\mathrm{B}}_{\mathbf{i}}}=\frac{V_{\mathrm{DC}}}{2^i}{S}_{\mathrm{H}{\mathrm{B}}_{\mathbf{i}}}$$

(4)

with $i=1,2,\cdots ,n$. Using (2) and (4) the output voltage of the asymmetric MLC can be expressed as

$$v_{\mathrm{out}}=V_{\mathrm{DC}}{S}_{\mathrm{NPC}}+\sum _{i=2}^n{S}_{\mathrm{HB}i}\frac{V_{\mathrm{DC}}}{2^i}$$

(5)

while the switching-state vector can be defined as

$$S_{\mathrm{MLC}}={\left[\begin{array}{c}{S}_{\mathrm{NPC}}\\ S_{\mathrm{HB}1}\\ ⋮\\ S_{{\mathrm{HB}}_{\mathbf{n}}}\end{array}\right]}^{\prime }.$$

(6)

With n H-bridge modules, the number of output voltage levels L can be expressed as

$$L=2^{n+1}+1.$$

(7)

2.2. Nearest-Level Control

A simple approach to modulate the desired sinusoidal output voltage waveform is nearest-level control (NLC), as described in [13]. The fundamental component can be approximated with the help of the modulation index M according to

$${\widehat{V}}_{\mathrm{out},1}\approx V_{\mathrm{DC}}M\mathrm{with}{V}_{\mathrm{DC}}^{\prime }=\frac{2V_{\mathrm{DC}}}{L-1}.$$

(8)

With the help of the pulse transition angle vector

$$\alpha ={\left[\begin{array}{c}{\alpha }_1{\alpha }_2\dots {\alpha }_{\frac{L-1}{2}}\end{array}\right]}^{\mathrm{T}}$$

(9)

the staircase-shaped output voltage waveform can be expressed as

$$v_{\mathrm{out},\mathrm{ref}}^{\prime }\left(\omega t\right)=\sum _{j=1}^{\frac{L-1}{2}}{V}_{\mathrm{DC}}^{\prime }{\mathsf{\Gamma }}_j\left(\omega t\right)$$

(10)

with

$$\begin{array}{c}\hfill {\mathsf{\Gamma }}_j\left(\omega t\right)=\left\{\begin{array}{cc}+1;\hfill & \mathrm{if}{\alpha }_j\le \omega t\le \pi -{\alpha }_j\hfill \\ -1;\hfill & \mathrm{if}\pi +{\alpha }_j\le \omega t\le 2\pi -{\alpha }_j\hfill \\ 0;\hfill & \mathrm{else}\hfill \end{array}\right..\end{array}$$

(11)

If the modulation index is low, not all voltage levels are needed. With respect to $\alpha$, the number of needed pulse transition angles can be calculated according to

$$k=⌈\frac{M(L-1)}{2}⌉$$

(12)

where the operator $\lceil \rceil$ indicates to round up the result of the fraction to the nearest integer value. The value of the pulse transition angles can be calculated according to

$$(j-0.5)V_{\mathrm{DC}}^{\prime }=\frac{(2j-1)V_{\mathrm{DC}}}{L-1}=V_{\mathrm{DC}}Msin\left({\alpha }_n\right)$$

(13)

which results in

$${\alpha }_j=arcsin\left(\frac{2j-1}{(L-1)M}\right).$$

(14)

Consequently, the pulse transition angle vector $\alpha$ becomes

$$\alpha =\left[\begin{array}{c}{\alpha }_1=arcsin\left(\frac{1}{(L-1)M}\right)\\ ⋮\\ {\alpha }_k=arcsin\left(\frac{2k-1}{(L-1)M}\right)\\ {\alpha }_{k+1}=\frac{\pi }{2}\\ ⋮\\ {\alpha }_{\frac{L-1}{2}}=\frac{\pi }{2}\end{array}\right].$$

(15)

For example, Figure 2 depicts the modulated staircase-shaped output voltage (phase voltage) waveform using NLC for a 17-level converter ($n=3$ according to Figure 1) and a modulation index $M=0.95$.

Under nominal operating conditions, a single-phase, grid-connected inverter with a DC link voltage of 350 $\mathrm{V}$ is typically operated with a modulation index in the range of 0.85 to 0.95. Nonetheless, according to the IEEE Std. 2030 [37], “IEEE Guide for Smart Grid Interoperability of Energy Technology and Information Technology Operation with the Electric Power System (EPS),, End-Use Applications, and Loads”, grid-feeding converters shall be able to continue their operation during certain fault conditions, such as a low-voltage ride-through condition. Therefore, grid-connected converters, when operated in grid-feeding mode, must be able to operate with low modulation indices in the range from 0.15 to 0.25 [38]. Therefore, it is reasonable to employ a large number (>30) of output voltage levels for MLIs operated with NLC.

3. Weighted Total Harmonic Distortion of Higher Level NLC Waveform in Comparison to Three-Level PWM

This section should briefly quantify the quality of higher level NLC waveforms in relation to a three-level PWM waveform and its switching frequency.

The concept of the Weighted Total Harmonic Distortion (WTHD), as explained in [13], is a measure to compare the probable current quality of different voltage waveforms. To derive the expression of the WTHD, it is reasonable to start from the voltage THD expression, which can be described as

$${THD}_{\mathrm{V}}=\sqrt{{\left(\frac{V_{\mathrm{rms}}}{V_1,\mathrm{rms}}\right)}^2-1}.$$

(16)

Without a DC component, the voltage THD expression becomes

$${THD}_{\mathrm{V}}=\sqrt{\sum _{h=2}^{\infty }{\left(\frac{V_h}{V_1}\right)}^2}.$$

(17)

Similar as in (17), the current THD can be expressed as

$${THD}_{\mathrm{I}}=\sqrt{\sum _{h=2}^{\infty }{\left(\frac{I_h}{I_1}\right)}^2}.$$

(18)

Assuming that the voltage is applied to a lossless inductive load, the current harmonics can be calculated with the help of the voltage harmonics according to

$$I_h\approx \frac{V_h}{h{\omega }_{1}L}\mathrm{with}h=\{2,3,4\cdots \}.$$

(19)

Inserting (19) in the current THD expression given in (19), the weighted THD as a function of the voltage harmonics can be obtained according to

$$WTHD=\frac{1}{V_1}\sqrt{\sum _{h=2}^{\infty }{\left(\frac{V_h}{h}\right)}^2}.$$

(20)

According to [13], using NLC, the output harmonic components relative to the pulse transition angles can be expressed as

$$V_{\mathrm{out}}{,}_{\mathrm{h}}=\frac{8V_{\mathrm{DC}}}{(L-1)h\pi }\left(\cos \left(h{\alpha }_1\right)+\cdots +\cos (h{\alpha }_{\frac{L-1}{2}})\right)$$

(21)

with only odd harmonic components occurring, corresponding to $h=\{1,3,5,\cdots \}$. In comparison, when operating only the NPC main stage, the output voltage components using three-level, naturally sampled, sine-triangle PWM can be described according to [13] as

$$V_{\mathrm{out}},1=V_{\mathrm{DC}}M$$

(22)

and

$$V_{\mathrm{out},h}=\frac{4V_{\mathrm{DC}}}{\pi }\sum _{c=1}^{\infty }\sum _{b=-\lambda }^{\lambda }\frac{1}{2c}{J}_{2b-1}\left(c\pi M\right)cos\left([c+b-1]\pi \right)$$

(23)

with

$$h=2c{m}_{\mathrm{f}}+(2b-1).$$

(24)

The expression $J_{2\mathrm{b}-1}\left(c\pi M\right)$ denotes the Bessel functions of the first kind with c representing the order of the carrier harmonic and b representing the order of the corresponding sideband harmonic. The number/boundary of the considered sideband harmonics is $\lambda$, which is dependent on the carrier ratio

$$m_{\mathrm{f}}=\frac{f_{\mathrm{sw}}}{f_1},$$

(25)

which is usually considered to be an integer value. In practice, also to avoid overlapping, $\lambda$ is typically selected to be less than 10, because of the rapid roll-off in magnitude of the Bessel function $J_{2\mathrm{b}-1}\left(c\pi M\right)$ [13].

With the help of (21) and (23) the weighted THD $WTHD$, as described in (20), can be determined for NLC and three-level PWM relative to the modulation index M, as depicted in Figure 3. A grid-tied, 33-level inverter operated with NLC theoretically achieves a similar current quality as a three-level inverter operated with a switching frequency $f_{\mathrm{sw}}$ of 5 $\mathrm{k}$$\mathrm{Hz}$ to 25 $\mathrm{k}$$\mathrm{Hz}$.

4. Current Control and Voltage Balancing of the Asymmetric Cascaded Multilevel Converter

This section gives a brief description of the current control of a grid-tied, asymmetric cascaded MLC, as shown in Figure 1. Furthermore, as a main contribution of this paper, the novel capacitor voltage balancing approach and its sensorless variant are derived.

Typically, the apparent power at the grid side, can be determined as

$$P_{\mathrm{AC}}+j{Q}_{\mathrm{AC}}=V_{\mathrm{AC}}·I_{\mathrm{AC}}^{\ast }.$$

(26)

Thus, the desired reference current for a certain apparent power can be calculated as

$$I_{\mathrm{AC},\mathrm{ref}}=\frac{P_{\mathrm{AC},\mathrm{ref}}-j{Q}_{\mathrm{AC},\mathrm{ref}}}{V_{\mathrm{AC}}^{\ast }}.$$

(27)

A phase-locked loop (PLL) based on a second order generator, as described in [39], shall be used to to synchronize the voltage reference frame of the inverter with the grid voltage $V_{\mathrm{AC}}$.

4.1. Current Control Using a Proportional-Resonant Controller

The suggested control scheme of the output current $i_{\mathrm{AC}}$ for the grid-tied, asymmetric cascaded MLC (shown in Figure 1) is depicted in Figure 4 and explained in the following.

The derivative of the output current $i_{\mathrm{AC}}$ can be expressed as

$$\frac{d{i}_{\mathrm{AC}}}{dt}=-\frac{R_{\mathrm{filter}}}{L_{\mathrm{filter}}}{i}_{\mathrm{AC}}+\frac{1}{L_{\mathrm{filter}}}(v_{\mathrm{out}}-v_{\mathrm{AC}})$$

(28)

with $v_{\mathrm{out}}$ as described in (5). Using the Laplace transform of (28), the current $i_{\mathrm{AC}}$ in relation to the output voltage $v_{\mathrm{out}}$ can be expressed in transfer-function form as

$$G_{\mathrm{p}}\left(s\right)=\frac{i_{\mathrm{AC}}}{v_{\mathrm{out}}-v_{\mathrm{AC}}}=\frac{1}{s{L}_{\mathrm{filter}}+R_{\mathrm{filter}}}.$$

(29)

To control a sinusoidal single-phase current through the grid filter, a Proportional-Resonant (PR) controller, as described in [40] and emphasized in green in Figure 4, can be used. Its gain can be mathematically expressed as

$$G_{\mathrm{c}}\left(s\right)=\frac{v_{\mathrm{out},\mathrm{ref}}-v_{\mathrm{AC}}}{\Delta i_{\mathrm{AC}}}=K_{\mathrm{p}}+\frac{K_{\mathrm{i}}s}{s^2+{\omega }_0^2}$$

(30)

which corresponds to

$$G_{\mathrm{c}}\left(s\right)=K_{\mathrm{p}}+\frac{K_{\mathrm{i}}\frac{1}{s}}{1+{\omega }_0^2\frac{1}{s}\frac{1}{s}}.$$

(31)

As described in [41], to discretize the controller in (31), both the forward Euler method according to

$$\frac{1}{s}\to T_{\mathrm{s}}\frac{1}{z-1}$$

(32)

as well as the backward Euler method according to

$$\frac{1}{s}\to T_{\mathrm{s}}\frac{z}{z-1}$$

(33)

can be used to implement the integrator terms and preserve the properties of the continuous PR-controller. Thus, as suggested in [41], a combination of both methods is used: forward Euler for the integrator term in the numerator and the first integrator in the denominator, and backward for the second integrator term in the denominator. The resulting controller gain $G_{\mathrm{c}}\left(s\right)$ transformed into the z-domain is

$$G_{\mathrm{c}}\left(z\right)=K_{\mathrm{p}}+K_{\mathrm{i}}{T}_{\mathrm{s}}\frac{z-1}{z^2-z(2-{\omega }_0^2{T}_{\mathrm{s}}^2)+1}.$$

(34)

When using PWM, the sample time $T_{\mathrm{s}}$ is typically the inverse of the switching frequency $f_{\mathrm{sw}}$ at which the entire converter leg is operated. The controller parameters $K_{\mathrm{i}}$ and $K_{\mathrm{p}}$ can be parametrized in a similar manner as for a PI-controller, for example as described in [42,43]. To improve the performance of the current controller, the measured grid voltage $v_{\mathrm{AC}}$ was used in here as a feedforward term, as can be seen in Figure 4. Hence, the current controller determines the required output voltage $v_{\mathrm{out},\mathrm{ref}}$, which should be modulated by the nearest discrete output voltage level $v_{\mathrm{out},\mathrm{ref}}^{\prime }$. Then, an optimal switching-state combination should be chosen and applied to actually output the required voltage.

4.2. Capacitor Voltage Balancing Using a One-Time-Step Model Predictive Control Approach

To properly control the current, the capacitor voltages must be balanced according to their nominal rating by the alternate selection of optimal switching-state combinations, as highlighted in orange in Figure 4. In the following, a model predictive control (MPC) approach with a prediction horizon of one time step, which is often referred to as one-step ahead approach [44,45], is introduced to find the optimal switching-state vector to mitigate the capacitors’ voltage imbalance within the next switching interval as much as possible.

The dynamics of the capacitors’ voltages, according to Figure 1, can be described as

$$\frac{d{v}_{\mathrm{Cap}\mathrm{i}}}{dt}=-\frac{1}{C_i}{S}_{\mathrm{HB}\mathrm{i}}{i}_{\mathrm{AC}}$$

(35)

with $i=1,2,\cdots ,n$. The deviation of the capacitors’ voltages relative to their nominal reference voltages can be expressed as

$$\Delta v_{\mathrm{Cap}}=\left[\begin{array}{c}{v}_{\mathrm{Cap}1}\\ v_{\mathrm{Cap}2}\\ ⋮\\ v_{\mathrm{Cap}n}\end{array}\right]-\left[\begin{array}{c}{V}_{\mathrm{Cap}1,\mathrm{ref}}\\ V_{\mathrm{Cap}2,\mathrm{ref}}\\ ⋮\\ V_{\mathrm{Cap}n,\mathrm{ref}}\end{array}\right].$$

(36)

For each output voltage level of the EMMC, there are m switching-state combinations according to

$$S_{\mathrm{MLC}}\mathrm{m}=\left[\begin{array}{cccc}{S}_{\mathrm{NPC},1}& S_{\mathrm{HB}1,1}& \cdots & S_{\mathrm{HB}n,1}\\ ⋮& ⋮& \ddots & ⋮\\ S_{\mathrm{NPC},m}& S_{\mathrm{HB}1,\mathrm{m}}& \cdots & S_{\mathrm{HB}n,m}\end{array}\right].$$

(37)

Thus, considering just the switching-states of the H-bridges comprising the capacitor modules, $S_{\mathrm{MLC}\mathrm{m}}$ can be reduced to

$$S_{\mathrm{HB}}\mathrm{m}=\left[\begin{array}{ccc}{S}_{\mathrm{HB}1,1}& \cdots & S_{\mathrm{HB}n,1}\\ ⋮& \ddots & ⋮\\ S_{\mathrm{HB}1,m}& \cdots & S_{\mathrm{HB}n,m}\end{array}\right].$$

(38)

Consequently, the weighting vector W, relative to the direction of the current, to assess the effectiveness of each individual switching-state combination can be calculated as

$$W=\left\{\begin{array}{cc}+S_{\mathrm{HB}\mathrm{m}}·\Delta v_{\mathrm{Cap}}\hfill & \mathrm{for}{i}_{\mathrm{AC}}\ge 0\hfill \\ -S_{\mathrm{HB}\mathrm{m}}·\Delta v_{\mathrm{Cap}}\hfill & \mathrm{for}{i}_{\mathrm{AC}}<0\hfill \end{array}\right..$$

(39)

Thus, the switching combination achieving the maximum value of W yields the optimal switching-state combination according to

$$\max \left(W\right)\to S_{\mathrm{opt}}.$$

(40)

To understand the suggested approach better, a short example is given in the following. The output voltage $v_{\mathrm{out}}$ should be $\frac{V_{\mathrm{DC}}}{2^4}$ and the current is positive according to $i_{\mathrm{AC}}\ge 0$. The number of H-bridge modules is $n=4$. This results in $m=5$ possible switching-state combinations as stated in

Table 1. Switching-state combinations for $v_{\mathrm{out}}=\frac{V_{\mathrm{DC}}}{2^4}$ and $n=4$, which gives $m=5$ possible combinations.

${\mathit{S}}_{\mathbf{NPC}}\left(\frac{{\mathit{V}}_{\mathbf{DC}}}{2^0}\right)$	${\mathit{S}}_{\mathbf{HB}1}\left(\frac{{\mathit{V}}_{\mathbf{DC}}}{2^1}\right)$	${\mathit{S}}_{\mathbf{HB}2}\left(\frac{{\mathit{V}}_{\mathbf{DC}}}{2^2}\right)$	${\mathit{S}}_{\mathbf{HB}3}\left(\frac{{\mathit{V}}_{\mathbf{DC}}}{2^3}\right)$	${\mathit{S}}_{\mathbf{HB}4}\left(\frac{{\mathit{V}}_{\mathbf{DC}}}{2^4}\right)$
1	−1	−1	−1	−1
0	1	−1	−1	−1
0	0	1	−1	−1
0	0	0	1	−1
0	0	0	0	1

.

Presumably, the first two capacitor modules are balanced, whereas the third and fourth show a deviation of $-1$ $\mathrm{V}$ and 2 $\mathrm{V}$, respectively. Thus, the weighting vector can be calculated as

$$W=\left[\begin{array}{cccc}-1& -1& -1& -1\\ 1& -1& -1& -1\\ 0& 1& -1& -1\\ 0& 0& 1& -1\\ 0& 0& 0& 1\end{array}\right]·\left[\begin{array}{c}0\mathrm{V}\\ 0\mathrm{V}\\ -1\mathrm{V}\\ 2\mathrm{V}\end{array}\right]$$

(41)

which results in

$$W=\left[\begin{array}{c}-1\mathrm{V}\\ -1\mathrm{V}\\ 1\mathrm{V}\\ -3\mathrm{V}\\ 2\mathrm{V}\end{array}\right].$$

(42)

Finally, the optimal switching-state combination becomes

$$S_{\mathrm{opt}}=\left[00001\right].$$

(43)

A simple approach to properly dimension the capacitor sizes is given in [30]. As described in [30], the maximum voltage deviation of the converter’s output voltage occurs when all modules are inserted and it can be approximated according to

$$\Delta V_{\mathrm{out},\max }={\widehat{I}}_{\mathrm{AC}}{T}_{\mathrm{s}}{\sum }_{i=1}^n\frac{1}{C_i}$$

(44)

with ${\widehat{I}}_{\mathrm{AC}}$ and $C_i$ being the phase current’s amplitude and capacitance of the individual H-bridge modules, respectively. Thus, in comparison to the NLC approach in [30], the in here suggested approach can reduce the capacitor requirement according to (44), because the algorithm updates the switching-state combination with respect to the sample time $T_{\mathrm{s}}$ and not only when step-wise changes in the output voltage occur. Since the switching-state combination is not necessarily changed after each sample period, the suggested algorithm can be categorized as an MPC approach with variable switching time instants [46].

4.3. Sensorless Capacitor Voltage Balancing Using a Dynamic Programming Approach

Considering the suggested approach in Section 4.2, a series of offline calculated, optimal switching-state combinations for each discrete output voltage level and a series of current values, positive and negative, could be used to operate the inverter with a lookup table approach without measuring the actual capacitor voltages. Thus, the offline calculated optimal switching-state combinations are sequentially applied ($z^{-1}$), as shown in orange in Figure 4. This approach is referred to as dynamic programming.

To keep the capacitor voltages balanced, the optimal switching-state sequences simply need to drive the average capacitor currents, sometimes referred to as current-second areas (charge), to zero. Thus, considering a variation of the converter’s displacement power factor and current amplitude, a large, intricate array of switching-state sequences would be required in theory. Although, when considering the illustration of the cell-voltage combinations in [24] [Figure 4], it becomes obvious that both the current-second and the applied voltage-second areas at steady state for any discrete output voltage become zero, if the EMMC itself is operated with a unity displacement power factor. Therefore, to reduce the required computational effort and the memory for the lookup table, the output current should be controlled to be in phase with the converter’s output voltage, as depicted in Figure 5 for grid-feeding mode, which slightly reduces the actual power factor cos($\phi$). Nonetheless, this approach could affect the voltage stability when operating in grid-forming mode [47]. Consequently, an optimal switching-state sequence for each discrete voltage level when loaded with a DC current, achieving that the applied voltage-second areas of the H-bridge modules become zero, can be generated offline. The selected DC current value should preferably be as close as possible to the instantaneous current when the corresponding discrete level would be actually activated for the considered operating point. Nonetheless, if a different DC current is arbitrarily but reasonably chosen, the current-second areas become zero as well and, thus, only the capacitor voltages’ ripples are marginally affected. The suggested sensorless approach is only suitable for MLCs operated with only active power capability. Due to symmetry reasons, it is sufficient to calculate the optimal switching-state combinations for only half of the discrete output levels, e.g., for the ones creating a positive output voltage. The switching-state combinations for the negative output levels can be obtained through the multiplication of the switching-state combinations for the positive output levels and minus one. For further simplifications, in here it is suggested to use the average absolute value of the selected operating point’s AC current for all considered output levels when offline creating the switching-state combinations.

For example, Figure 6a shows the simulated capacitor voltages and the output voltage, corresponding to the fifth positive output voltage level, for a 33-level EMMC while balancing the capacitors for a certain DC current considering the approach described in Section 4.2. Thus, the switching-state combinations obtained for Figure 6a should be stored in a lookup table, and the approach should be repeated for all remaining positive voltage levels. When operating the inverter and generating an AC output voltage, a switching-state combination is sequentially chosen from the stored lookup tables for each of the desired reference voltage levels $v_{\mathrm{out},\mathrm{ref}}^{\prime }$. For example, assuming ideally balanced capacitor voltages, Figure 6b shows the output voltages of the asymmetric MLC and the individual converter stages corresponding to a fundamental output voltage of $V_{\mathrm{out},1}=330 \mathrm{V}$.

For the depicted switching pattern, the average switching frequency of the NPC main stage corresponds to about ${\overline{f}}_{\mathrm{sw}},\mathrm{NPC}\approx 950\mathrm{Hz}$, while the switching frequency of the individual H-bridges is about twice the switching frequency of the NPC module according to ${\overline{f}}_{\mathrm{sw}},\mathrm{HB}\approx 2{\overline{f}}_{\mathrm{sw}},\mathrm{NPC}$. Since the converter allows for bidirectional power flow, the described approach can be applied in a similar way when operating the converter as an electronic load.

5. Stability of the Sensorless, Dynamic Programming Approach

It is assumed that for some desired steady state current trajectory $i_{\mathrm{AC},\mathrm{ref}}$ the required switching-state sequences $S_{\mathrm{NPC}}^{\left(\mathrm{des}\right)}$ and $S_{\mathrm{HB}i}^{\left(\mathrm{des}\right)}$, for achieving the necessary output voltage $v_{\mathrm{out}}=V_{\mathrm{DC}}{S}_{\mathrm{NPC}}^{\left(\mathrm{des}\right)}+{\sum }_{i=1}^n{S}_{\mathrm{HB}i}^{\left(\mathrm{des}\right)}{v}_{\mathrm{Cap}i}$, can be accurately generated. This may eventually require a fine time resolution (or a relative high switching frequency). The developed converter system experimentally displays the following behavior: when driven by such an optimal switching-state sequence, independent of the initial state, the system eventually reaches the desired current trajectory. The goal of this section is proving such observed behavior.

The system considered is described by the current $i_{\mathrm{AC}}$ and n capacitor voltages $v_{\mathrm{Cap}i}$, which represent together the state vector. The deviation between the actual state and the desired reference trajectory is described by

$$\Delta i_{\mathrm{AC}}=i_{\mathrm{AC}}-i_{\mathrm{AC},\mathrm{ref}}$$

(45)

and

$$\Delta v_{\mathrm{Cap}i}=v_{\mathrm{Cap}i}-v_{\mathrm{Cap}i,\mathrm{ref}}.$$

(46)

The dynamics of the actual and the reference current, both driven by the same optimal switching-state sequences $S_{\mathrm{NPC}}^{\left(\mathrm{des}\right)}$ and $S_{\mathrm{HB}i}^{\left(\mathrm{des}\right)}$, are given by

$$\begin{array}{c}\hfill \frac{d{i}_{\mathrm{AC}}}{dt}=-\frac{R_{\mathrm{filter}}}{L_{\mathrm{filter}}}{i}_{\mathrm{AC}}+\frac{1}{L_{\mathrm{filter}}}(V_{\mathrm{DC}}{S}_{\mathrm{NPC}}^{\left(\mathrm{des}\right)}+\\ \hfill {\sum }_{i=1}^n{S}_{\mathrm{HB}i}^{\left(\mathrm{des}\right)}{v}_{\mathrm{Cap}i}-v_{\mathrm{AC}})\end{array}$$

(47)

and

$$\begin{array}{c}\hfill \frac{d{i}_{\mathrm{AC},\mathrm{ref}}}{dt}=-\frac{R_{\mathrm{filter}}}{L_{\mathrm{filter}}}{i}_{\mathrm{AC},\mathrm{ref}}+\frac{1}{L_{\mathrm{filter}}}(V_{\mathrm{DC}}{S}_{\mathrm{NPC}}^{\left(\mathrm{des}\right)}+\\ \hfill {\sum }_{i=1}^n{S}_{\mathrm{HB}i}^{\left(\mathrm{des}\right)}{v}_{\mathrm{Cap}i,\mathrm{ref}}-v_{\mathrm{AC}})\end{array}$$

(48)

respectively, such that the current error’s dynamics become

$$\begin{array}{c}\hfill \frac{d\Delta i_{\mathrm{AC}}}{dt}=-\frac{R_{\mathrm{filter}}}{L_{\mathrm{filter}}}\Delta i_{\mathrm{AC}}+\frac{1}{L_{\mathrm{filter}}}{\sum }_{i=1}^n{S}_{\mathrm{HB}i}^{\left(\mathrm{des}\right)}\Delta v_{\mathrm{Cap}i}.\end{array}$$

(49)

Analogously, the dynamics of the actual and the reference capacitor voltages, both again driven by the same optimal switching-state sequences $S_{\mathrm{NPC}}^{\left(\mathrm{des}\right)}$ and $S_{\mathrm{HB}i}^{\left(\mathrm{des}\right)}$, are respectively given by

$$\frac{d{v}_{\mathrm{Cap}i}}{dt}=-\frac{1}{C_i}{S}_{\mathrm{HB}i}^{\left(\mathrm{des}\right)}{i}_{\mathrm{AC}}$$

(50)

and

$$\frac{d{v}_{\mathrm{Cap}i,\mathrm{ref}}}{dt}=-\frac{1}{C_i}{S}_{\mathrm{HB}i}^{\left(\mathrm{des}\right)}{i}_{\mathrm{AC},\mathrm{ref}}$$

(51)

leading to the following dynamics for the capacitors’ voltage errors

$$\frac{d\Delta v_{\mathrm{Cap}i}}{dt}=-\frac{1}{C_i}{S}_{\mathrm{HB}i}^{\left(\mathrm{des}\right)}\Delta i_{\mathrm{AC}}.$$

(52)

The proof of the observed experimental behavior mentioned at the beginning of this section is easily shown by introducing the following Lyapunov function $V=V(\Delta i_{\mathrm{AC}},\Delta v_{\mathrm{Cap}i})$ according to

$$V=\frac{L_{\mathrm{filter}}}{2}{(\Delta i_{\mathrm{AC}})}^2+{\sum }_{i=1}^n\frac{C_i}{2}{(\Delta v_{\mathrm{Cap}i})}^2$$

(53)

analogous in form to the total energy stored in the inductor and capacitors of the system, although now referred to the deviations from the desired trajectory. This Lyapunov function V is strictly positive as long as the errors $\Delta i_{\mathrm{AC}}$ and/or $\Delta v_{\mathrm{Cap}i}$ do not vanish. As a result of the dynamics (49) and (52) function V is a nonincreasing function with time

$$\frac{dV}{dt}=-R_{\mathrm{filter}}\Delta i_{\mathrm{AC}}^2.$$

(54)

This time derivative is nevertheless only negative semidefinite, since the Lyapunov function $V=V(\Delta i_{\mathrm{AC}},\Delta v_{\mathrm{Cap}i})$ depends on all the $n+1$ dynamic variables, but its time derivative does only depend on one single variable ($\Delta i_{\mathrm{AC}}$). Consequently, the original Lyapunov theorem is of no use for proving the asymptotic stability behavior $\Delta i_{\mathrm{AC}},\Delta v_{\mathrm{Cap}i}\stackrel{t\to \infty }{⟶}0$ and the more general Krassowski–LaSalle invariance principle [48,49] is required. According to this latter principle, the dynamics asymptotically converge to some trajectory of the considered equations of motion (49) and (52), which simultaneously satisfied ${\displaystyle dV/dt=0}$; however, a constant stationary point of the equations of motion is also a (trivial) trajectory remaining on the same value during the whole time evolution. A vanishing time derivative of the Lyapunov function yields

$$\frac{dV}{dt}=-R_{\mathrm{filter}}\Delta i_{\mathrm{AC}}^2=0\Rightarrow \Delta i_{\mathrm{AC}}=0,$$

(55)

which according to (49) leads to ${\sum }_{i=1}^n{S}_{\mathrm{HB}i}^{\left(\mathrm{des}\right)}\Delta v_{\mathrm{Cap}i}=0$, although not to the separated vanishing of each single $\Delta v_{\mathrm{Cap}i}$. Since nevertheless the switching-state sequence values $S_{\mathrm{HB}i}^{\left(\mathrm{des}\right)}$ change all the time, once $\Delta i_{\mathrm{AC}}=0$ is achieved, the probability of satisfying condition ${\sum }_{i=1}^n{S}_{\mathrm{HB}i}^{\left(\mathrm{des}\right)}\Delta v_{\mathrm{Cap}i}=0$ with varying $S_{\mathrm{HB}i}^{\left(\mathrm{des}\right)}$ (and also changing $\Delta v_{\mathrm{Cap}i}$) is very low, particularly for a relative high number of capacitor modules: the only solution of condition ${\sum }_{i=1}^n{S}_{\mathrm{HB}i}^{\left(\mathrm{des}\right)}\Delta v_{\mathrm{Cap}i}=0$ under these conditions is therefore $\Delta v_{\mathrm{Cap}i}=0$ for each single capacitor. Since this only solution $\Delta i_{\mathrm{AC}}=0=\Delta v_{\mathrm{Cap}i}$ is also a trajectory of the equations of motion, the Krassowski–LaSalle invariance principle shows that the system cannot get “stuck” at any other trajectory than such stationary point. Hence, when driving the converter system with the optimal switching-state sequences corresponding to some desired reference trajectory, such trajectory is asymptotically reached

$$i_{\mathrm{AC}}\stackrel{t\to \infty }{\to }{i}_{\mathrm{AC}},\mathrm{ref}\mathrm{and}{v}_{\mathrm{Cap}i}\stackrel{t\to \infty }{\to }{v}_{\mathrm{Cap}i,\mathrm{ref}}.$$

(56)

The main ingredient in the previous proof is the existence of a nonvanishing (positive) resistance $R_{\mathrm{filter}}$ which constantly dissipates power, and thus, ensures the decreasing of the Lyapunov function value.

6. Measurements

To verify the effectiveness and the stability of the derived one-step ahead balancing algorithm and its sensorless variant (described above), a laboratory, 33-level converter is used, as can be seen in Figure 7. It is based on the commercially available converter modules from Imperix Ltd. and it comprises an NPC main stage [50] and four H-bridge modules [51]. The entire control and balancing algorithm is implemented in the B-Box RCP control unit [52] of Imperix Ltd. The DC inputs of the NPC module and each of the H-bridges are attached with a 517 $\mathsf{\mu }$$\mathrm{F}$ and a 5 $\mathrm{m}$$\mathrm{F}$ capacitor bank (electrolytic), respectively. The selected DC link voltage rating is $V_{\mathrm{DC}}=350 \mathrm{V}$, using unidirectional power supplies, and the chosen grid filter’s inductance rating is about 30 $\mathrm{m}$$\mathrm{H}$ ($L_{\mathrm{filter}}=28.8 \mathrm{mH}$, $R_{\mathrm{filter}}=0.2 \mathsf{\Omega }$ and $I_{\mathrm{rat},\mathrm{rms}}=30 \mathrm{A}$). Here, the design of the converter and the grid filter is not part of this paper’s scope. Especially, the size of the grid filter seems rather large, but it is chosen for simplicity. The inductance rating for an LCL-filter ( 60 $\mathrm{d}$$\mathrm{B}$ damping per decade) with a similar damping effect could be about 100 times smaller, corresponding to about 300 $\mathsf{\mu }$$\mathrm{H}$. The used charging resistors have a total resistance of $R_{\mathrm{charging}}=80 \mathsf{\Omega }$. The entire converter leg is operated with a sampling frequency of $f_{\mathrm{s}}=5 \mathrm{kHz}$, which results in an actual average switching frequency, similar as described in Section 4.3, of about ${\overline{f}}_{\mathrm{sw}},\mathrm{NPC}\approx 950\mathrm{Hz}$ and ${\overline{f}}_{\mathrm{sw}},\mathrm{HB}\approx 2{\overline{f}}_{\mathrm{sw}},\mathrm{NPC}$ for the NPC stage and the H-bridges, respectively. For the experimental verification, all waveforms are captured with an oscilloscope.

6.1. Capacitor Precharging

Before operating the converter in grid-feeding mode, the capacitors must be charged up using the suggested charging resistance $R_{\mathrm{charging}}$. During the charging process, the reference output voltage $v_{\mathrm{out}},\mathrm{ref}$ should be set to $v_{\mathrm{AC}}$. When already using the current controller, the reference current $i_{\mathrm{AC}},\mathrm{ref}$ should be set to zero. Figure 8a,b show the start-up charging of the H-bridges’ capacitors when operating the inverter with and without the voltage sensing, respectively.

Since the sensorless approach utilizes a switching-pattern, which was generated only for the actual operating point of ${\widehat{I}}_{\mathrm{AC}}=10 \mathrm{A}$, it takes about 20 $\mathrm{s}$ until the capacitors have reached their nominal reference voltages. This in turn verifies the stability described in Section 5. On the contrary, when using the capacitor voltages as a feedback, the nominal reference voltages are already reached after about $2.2$ $\mathrm{s}$. Hence, the dynamic response, using the sensorless approach, is compromised.

6.2. Operation in Grid-Feeding Mode

When the H-bridges’ capacitors are completely charged up, the charging resistor $R_{\mathrm{charging}}$ can be bypassed via the contactor. Subsequently, the converter can be operated according to Figure 5, feeding active power to the grid. Figure 9a,b show the grid voltage $v_{\mathrm{AC}}$, the converter output voltage $v_{\mathrm{out}}$ and the output current $i_{\mathrm{AC}}$ for one electrical period with and without the sensing of the capacitor voltages, respectively. The current’s magnitude is controlled to be ${\widehat{I}}_{\mathrm{AC}}=10 \mathrm{A}$, which results in a fundamental output voltage of about $V_{\mathrm{out}},1=330 \mathrm{V}$. Thus, the converter is feeding about $1.65 \mathrm{k}\mathrm{W}$ to the grid. The phase shift angle $\phi$ between the grid voltage $V_{\mathrm{AC}}$ and $I_{\mathrm{AC}}$ is about $16.5$ ${}^{\circ }$, leading (over excited). This corresponds to a power factor of about $\cos \left(\phi \right)=0.96$. Figure 9a shows that, due to the feedback of the capacitor voltages, the discrete output voltage levels are properly modulated while altering the switching-state combinations. Thus, the current THD becomes about $3.28$. On the contrary, when using the sensorless approach, the capacitor voltages slightly deviate during the operation. This is due to the fact that the nonlinear effects, such as the voltage drop across the IGBTs, the different self-discharge rates or the dead-time, are neglected during the offline generation of the optimal switching-state combinations. Thus, the discrete output voltage levels are slightly distorted while altering the switching-state combinations. This in turn results in an increased current THD of about $4.58$.

As described in the IEEE standard 519-2014 [53], “IEEE Recommended Practice and Requirements for Harmonic Control in Electric Power Systems”, a maximum current THD of up to 20 (depending on the connection point’s Thévnin impedance) and up to 5 is recommended for power consuming loads and power generating units, respectively. Consequently, the suggested control approach, including its sensorless variant, achieved a power-system-compliant current THD quality (<$5$).

Moreover, Figure 10a,b depict the harmonic components of the in Figure 9a,b depicted voltage and current waveforms, respectively. The depicted inset-figures in Figure 10a,b depict the harmonic components of the voltage and current waveforms in relation to their corresponding fundamental component and, in addition, the permissible, relative limits of the current harmonics according to the IEEE standard 519-2014 [53] are depicted by the green dashed line. All measured current harmonics comply with the specified limits. For both cases, with and without the sensing of the capacitor voltages, the third harmonic current component is the largest. Thus, the current THD value $TH{D}_{\mathrm{I}}$ is mainly driven by the third harmonic, which is caused by the third harmonic component of the inverter output voltage. Consequently, to improve the current quality further, it might be reasonable to implement a harmonic reduction technique, such as presented in [54,55] or [56], to decrease the third harmonic current component. Furthermore, triplen harmonics, such as the third harmonic, would not cause any currents if the inverter would be operated in an ungrounded three-phase system.

7. Conclusions

Based on the concept of the weighted THD of MLIs’ output voltage waveform, it was shown that a grid-tied ( 50 $\mathrm{Hz}$) MLI with 33 discrete output voltages levels, operated with NLC, can presumably achieve a similar current THD as a single-phase H-bridge converter operated with a switching frequency of 25 $\mathrm{k}$$\mathrm{Hz}$ (three-level PWM). To utilize this advantage, binary asymmetric voltage levels can be used for MLIs’ floating capacitor modules to reduce the number of required H-bridge modules.

This paper presented a novel capacitor voltage balancing approach applicable for cascaded multilevel converters with only one DC supply per phase and asymmetric capacitor voltages, tiered by a factor of two (binary asymmetric). Using a simple one-step ahead MPC approach, an optimal switching-state combination is mathematically determined among all redundant switching combinations to balance the capacitor voltages as quickly as possible. Furthermore, using the suggested optimal one-step ahead MPC approach, a series of offline calculated switching-state sequences for each discrete output voltage level can be used as lookup tables to operate the MLC without actually measuring (sensorless) the capacitor voltages. Using a Lyapunov function candidate, which is based on the energy stored in the grid filter’s inductor and the H-bridges’ capacitors, and considering LaSalle’s invariance principle, the proposed sensorless control approach is asymptotically stable, and thus, the capacitor voltages and the grid current converge over time to their desired references.

To experimentally verify the effectiveness and the stability of the presented one-step ahead balancing algorithm and its sensorless variant, a laboratory converter with four H-bridge stages, ideally achieving 33 discrete output voltage levels, was operated in grid-tied mode. Using a charging resistor during startup, the capacitor voltages converge to their desired reference levels, whereas the required charging time was increased from $2.2$ $\mathrm{s}$ to 20 $\mathrm{s}$ when using the suggested sensorless control approach. The converter was operated with a sampling frequency of 5 $\mathrm{k}$$\mathrm{Hz}$, which resulted in an actual switching frequency of 950 $\mathrm{Hz}$ and 2 $\mathrm{k}$$\mathrm{Hz}$ for the NPC stage and the individual H-bridge modules, respectively. For the chosen operating point (${\widehat{I}}_{\mathrm{AC}}=10 \mathrm{A}$) of the setup, the presented sensorless approach achieved a current THD $TH{D}_{\mathrm{I}}$ of about 4.58%, which is slightly increased in comparison to 3.28% when operating the converter with the voltage sensors. Nonetheless, it was verified that the suggested sensorless approach is asymptotically stable and can be used in practice, although the dynamic response of the system and the output current quality is enhanced when using the voltage sensors.

So far, only the active power capability of the sensorless approach was considered. Thus, in a future work, the algorithm could be extended to control also the reactive power.