A New Design of MP-HDCCB Topology Based on Hybrid Switching Device

Abstract

Since each branch of the multiterminal DC circuit system relies on the DC circuit breaker for breaking and fault isolation, the prohibitive cost and huge volume of the Hybrid DC Circuit Breaker (HCB) limit its development and broad application in multiterminal flexible DC systems. Multiport hybrid DC circuit breaker (MP-HDCCB) based on device and branch sharing reduces the configuration cost of the circuit breaker to a certain extent. In order to further reduce the cost of MP-HDCCB, a novel MP-HDCCB topology based on hybrid switching devices is proposed, adopting full controlled switching devices to achieve rapidity of breaking fault current, and using semi-controlled switching devices in series to withstand the transient interruption voltage (TIV), so as to reduce the construction cost and technical difficulty. In this paper, the working principle and fault breaking strategy of the topology are introduced in detail, then the parameters of the major circuit are analyzed theoretically, and the parameter design of each branch is given. In the end, the rationality and validity of the proposed topology is tested and verified by simulations and experimental tests.

1. Introduction

Voltage source converter based high voltage direct current (VSC-HVDC), a new DC transmission technology based on voltage source, is more suitable to constitute the multiterminal DC system, in the light of its advantages ranging from not changing voltage polarity during power flow reversal to independently adjusting active and reactive power, and supplying power for passive network. Therefore, it is more suitable to form the multiterminal high voltage direct current system (MT-HVDC) [1,2,3,4].

Under the circumstances of DC side short-circuit fault in VSC-HVDC, the freewheeling diode in parallel with IGBT in the converter valve is still on even if IGBT is blocked, which leads to its operation in the state of uncontrolled rectification [5,6,7]. Therefore, the short-circuit current will not be controlled by the converter. In addition, since the DC side line impedance is very small, the DC side capacitor discharge leads to a rapid increase in the short-circuit fault current. Consequently, if the traditional fault isolation method is adopted, VSC-HVDC can only trip the AC side circuit breaker when a fault happens. This will not only lead to the temporary shutdown of the whole system, but also have a serious impact on the parallel operation AC system, and seriously reduce the power supply reliability of the system. Therefore, it is necessary to equip the multiterminal DC system with DC circuit breaker so as to break the fault current and isolate the fault section; simultaneously, the normal operation of other remaining lines can be guaranteed [8,9].

From the perspective of a working principle, the DC circuit breaker is mainly classified into three types: Mechanical circuit breakers (MCB), pure solid-state circuit breakers (SSCB) and hybrid circuit breakers (HCB). Since the HCB not only has the properties of low on-state loss and potent insulation capacity of MCB, but also the properties of fast effective fault current breaking capability of SSCB, it has become the key focus in the domain of developing the HVDC circuit breaker [10,11,12].

The multiterminal DC System, however, usually involves one port connecting with many other ports via a power transmission cable. In order to ensure that each transmission line is capable of breaking the fault current quickly, many of the HCBs must be equipped at the same terminal according to the quantity of transmission lines connected to the terminal. Yet the great demand of HCBs on a wealth of power electronic devices gives rise to a significant increase in the development cost and installation volume of the DC circuit breaker [13]. Aiming to deal with the problems mentioned above, the multiport hybrid DC circuit breaker (MP-HDCCB) topology, having the properties of being fast and economical, is proposed in the present study.

The basic design idea is to make multiple DC circuit breakers share the same transfer branch and energy dissipation branch, so that the quantity of power electronic devices adopted can be reduced drastically. As a result, the control complexity of the HCB is effectively reduced on the one hand, and both development cost and installation volume are lowered on the other [14,15,16].

A novel multiport hybrid DC circuit breaker, suitable for the HVDC system, is proposed in [17], by which fast fault current breaking and low-on-state loss can be achieved. The scheme adopts the commutation mode of self-excited oscillation to achieve the rapid isolation of the short-circuit fault. However, the oscillation current cannot rise to a large enough value to form the current zero-crossing point over a short period. Given this, this scheme of MP-HDCCB can hardly be used in application scenarios having a relatively high requirement upon the speed of fault breaking. The MP-HDCCB proposed in [18,19], eliminating the need to take the direction of current into account, is able to break and isolate the fault current occurring on every port on its own. Nevertheless, this topology only conducted a parallel connection on every branch of many of the conventional hybrid DC circuit breakers, resulting in no decrease in the number of devices used in the transfer branch and energy dissipation branch at all. In such a case, the degree to which the cost is lowered is limited, let alone bringing about the thermal dissipation issue triggered by many circuit breakers working intensively at the same time. New topologies are proposed by using the low-cost thyristor and diode H-bridge circuit to ensure bidirectional current interruption on the one hand, and using the shared main breaker branch to further reduce the cost of the MP-HCB on the other [20,21]. However, this topology still needs IGBTs to turn off the fault current, and IGBTs should withstand the DC voltage.

A fast thyristors topology to shut down the fault current for the two terminal DC breaker is proposed in [22] proposed. The purpose of the multiport hybrid DC circuit breaker is to minimize the cost, which is the premise of the DC circuit breaker application. On the basis of the MP-HDCCB topology described above, a novel MP-HDCCB topology based on a series connection of hybrid switching devices is put forward in this paper. Aiming to lower the cost of transfer branches to the largest extent, transfer branches comprising series connection of thyristor and IGBT half-bridge module are used, swift breaking and commutating of the fault current is achieved via IGBT, and the thyristors are connected in series to withstand TIV. The turn-off speed of thyristor is improved by optimizing the full controlled module so as to reduce the cost without affecting the speed of the breaking fault current. The topology and working principles of the MP-HDCCB are introduced in Section 2. The parameter analysis is proposed in Section 3. Then, the rationality and validity of the proposed topology is tested and verified by simulations and experimental tests in Section 4 and Section 5 individually. Finally, the conclusion is drawn in Section 6.

2. The Proposed MP-HDCCB

2.1. Topology of the Proposed MP-HDCCB

Figure 1 shows the target MP-HDCCB topology designed on the basis of hybrid switching devices. This topology is made up of main branch, transfer branch, energy dissipation branch and clamping diodes branch. The MP-HDCCB is connected with an incoming line and outgoing line of the DC bus through a clamping diode, by which a single breaker is capable of protecting multiple lines.

The main branch: This is composed of an ultra-fast disconnector (UFD) and bidirectional load communication switch (LCS) in series. The bidirectional LCS consists of two IGBT modules in reverse series. In IGBT modules, diodes are antiparallel connected with IGBTs. By turning off the LCS of the corresponding line, the fault current is commutated from the main branch to the transfer branch so as to ensure that the UFD breaks without arc under zero current. When it is necessary to pre-close or reclose the circuit breaker, turn on the bidirectional LCS and turn on each switching device of the transfer branch. If there is no fault current detected in the transfer branch, turn on the UFD to commutate the current to the main branch.

Transfer branch and energy dissipation branch: The transfer branch is made up of the thyristor transfer branch and the capacitor transfer branch. In detail, the thyristor transfer branch is series-connected by the IGBT half-bridge submodule (SM) and T₁-thyristor, within which the function of withstanding the high DC voltage is served by thyristors, and the function of the fast breaking fault current is served by SM. The capacitor transfer branch consists of the individual C₂ capacitor. The energy dissipation branch is mainly composed of metal-oxide varistors (MOVs), which are used to limit TIV and to absorb the residual energy in the HVDC system. Illustrated in Figure 1 is the internal topology of the IGBT half-bridge submodule (SM). It is worth noting that C₁ in SM need be pre-charged; one is to ensure that there is a forward voltage drop when thyristor T₁ is turned on, which accelerates the conduction of the thyristor. The other is to use the energy stored by the reverse charging of capacitor C₁ to suppress the rise in fault current.

Clamping diode branch: Diode D₁₁…D_1n and D₂₁…D_2n are connected, respectively, to each end of the transfer branch and then connected to each port. The function of the diode branch is to ensure that the fault current of any port can flow to the transfer branch so as to achieve the purpose of sharing the transfer branch.

2.2. Working Principles of the Proposed MP-HDCCB

Figure 2 shows the working process of fault breaking accomplished by the MP-HDCCB proposed in this paper. The T1 and SM on the transfer branch, during normal working conditions, are both in a closed state; the load current of each port flows through UFD_i and LCS_i on the main branch connected to every port accordingly; the relevant current flow is shown in Figure 2a. Moreover, the capacitor C₁ in the SM of the transfer branch is pre-charged. In the case of ground-fault short circuit happening on a certain line, assuming it is the line on which port 1 locates in Figure 2a, the MP-HDCCB detects the fault and its action process is as follows:

(1) As shown in Figure 2b, the LCS₁ is commanded to be turned off first. Meanwhile, the thyristor T₁ and the IGBT module S₁ of SM are turned on immediately in order to force the fault current of port 1 to be commutated to the thyristor transfer branch. By then the load current at port 1 begins to drop. Because C₁ has pre-charge voltage, the fault current is commutated to S₁, rather than S₂.

(2) When the fault current of port 1 is about to reach zero, the UFD₁ is turned off. The mechanical switch achieves zero-current and zero-voltage turn-off.

(3) Once the UFD₁ is fully turned off, S₂ of the SM is commanded to be turned on. In the meantime, the thyristor T₁ and S₁ of the SM are turned off, forcing the fault current to be commutated to the capacitor transfer branch. Since there is a reverse recovery current during the turn-off process of thyristor T₁, this current will reverse charge capacitor C₁ in the SM. When the reverse recovery current of T1 drops to 0, the thyristor T₁ will withstand the voltage equaling to the difference of C₁ and C₂. With the purpose of turning off T₁ quickly, the voltage across the thyristor T₁ needs to constantly maintain the reverse standoff voltage over the period of fault current commutating from the thyristor branch to the capacitor branch. Therefore, the determination of the initial voltage of C₁ requires the voltage across C₁ to still be higher than the voltage across C₂ after the reverse recovery of T₁ is finished, keeping the thyristor T₁ withstand reverse voltage after the reverse recovery process. Illustrated in Figure 2c is the process of commutating fault current.

(4) As the thyristor T₁ is turned off completely, shown in Figure 2d, the fault current is completely commutated to the capacitor branch. The fault current charges C₂. When the C₂ voltage is bigger than the port 1 voltage, the fault current is beginning to decrease. The blocking time of the fault current is determined by the value of C₂; the smaller the value of C₂, the smaller blocking time.

(5) As shown in Figure 2e, when the voltage across C₂ reaches the clamping voltage of MOV on the energy dissipation branch, the fault current is commutated from the capacitor branch to the energy dissipation branch while the residual energy in the DC system is absorbed by MOV; later on, the fault current decreases gradually. Finally, as shown in Figure 2f, the residual current is interrupted. The fault current is completely isolated by the MP-HDCCB, and port 2 to port n still work normally.

Figure 2 shows that over the action process of the MP-HDCCB, the power exchange of transmission lines between other ports can be carried out through the path of UFD₂-LCS₂-LCS_n-UFD_n, ensuring that other normal lines are exempted from the impacts of the fault line and work in a normal state simultaneously. If the current direction of port 1 is reversed and other port current remains unchanged, the diodes D₁₁, D_1n and D₂₁ are conductive to provide the fault current path. Diodes D₁₁-D_1n and D₂₁-D_2n serve the function of achieving bidirectional current flow of MP-HDCCB on each line. The thyristor transfer branch only considers the unidirectional conduction, which will reduce the cost of the transfer branch.

3. Analysis and Parameter Design

3.1. The Major Circuit Parameter Design

The key focus of the parametric design of the proposed topology lies in assuring that the reverse voltage is kept valid over the process of thyristor reverse recovery. When the load current of port 1 exceeds the safety threshold, it commutates from the main branch of port 1 to the branch comprised of diode D_1n, thyristor T₁, SM (S₁) and diode D₂₁ in series; by then the fault current keeps rising. Assuming the duration of such a process is t₁, which is mainly used to wait for the UFD₁ to turn off completely, the relationship between associated thyristor T₁ and the current flowing through port 1 is shown below:

$$L_s\frac{\mathrm{d}{i}_{\mathrm{L}}\left(t\right)}{\mathrm{d}{t}_1}=U_{\mathrm{dc}}$$

(1)

Herein U_dc represents the line voltage from port 1 to port n, Ls stands for the line current-limiting inductor and i_L(t) is the current at port 1 after the fault occurs. The initial value of fault current, i₂, commutating from the thyristor transfer branch to the capacitor transfer branch, can be obtained when i_th and t₁ are substituted into the calculation. i_th is the operation threshold value of MP-HDCCB (initial value of i_L(t) in Equation (1)). t₁ is the current duration of thyristor transfer branch.

Using the voltage of C₂ in the capacitor transfer branch as the calculation target

$$C_2\frac{\mathrm{d}{U}_{{\mathrm{C}}_2}\left(t\right)}{\mathrm{d}t}=i_{\mathrm{L}}\left(t\right)$$

(2)

Substituting into Equation (1)

$$L_{\mathrm{s}}{C}_2\frac{{\mathrm{d}}^2{U}_{{\mathrm{C}}_2}\left(t\right)}{\mathrm{d}{t}^2}+U_{{\mathrm{C}}_2}\left(t\right)=U_{\mathrm{dc}}$$

(3)

The results of substituting the initial value and conducting the eigenvalue equation are

$$U_{{\mathrm{C}}_2}\left(t\right)=U_{\mathrm{dc}}-U_{\mathrm{dc}}\cos (\frac{1}{\sqrt{L_{\mathrm{s}}{C}_2}}t)+\sqrt{\frac{L_{\mathrm{s}}}{C_2}}{i}_1\sin (\frac{1}{\sqrt{L_{\mathrm{s}}{C}_2}}t)$$

(4)

The fault current flowing through C₂ is

$$i_{{\mathrm{C}}_2}\left(t\right)=i_1\cos \frac{1}{\sqrt{L_{\mathrm{s}}{C}_2}}t+U_{\mathrm{dc}}\sqrt{\frac{C_2}{L_{\mathrm{s}}}}\sin \frac{1}{\sqrt{L_{\mathrm{s}}{C}_2}}t$$

(5)

The value of C₂ can be obtained via Equation (4) by assuming that the duration of state maintenance is t₂ and the clamping voltage of MOV is U_{mov_th}. The C₁ of the SM mainly serves the function to provide the thyristor T₁ with reverse stand-off voltage over the whole process of fault current commutating from the thyristor transfer branch to the capacitor transfer branch. As shown in Figure 2c, after the S1 of the SM is turned off, the voltage across capacitor C₁ is higher than that across C₂, which leads the fault current to commutate from the thyristor transfer branch where C₁ is located to the capacitor transfer branch where C₂ is located. In the meantime, thyristor T₁ is not fully turned off. Then, the fault current starts to charge C₂ on the capacitor transfer branch during the time when the thyristor undergoes reverse recovery. Over the time period of t_rec, increase in voltage, U_C2s, of the C₂ on capacitor transfer branch can be obtained by having the duration of reverse recovery of thyristor T₁ (t_rec) substituted into Equation (4).

In order to make sure thyristor T₁ is completely turned off, it is necessary to ensure that the voltage (U_C1) across C₁ is still higher than that (U_C2) across C₂ after t_rec. During t_rec the charge in thyristor T₁ is fully neutralized by C₁; hence,

$$\{\begin{array}{c}{C}_1\frac{\mathrm{d}{U}_{{\mathrm{C}}_1}}{\mathrm{d}t}=i\\ Q=idt\end{array}$$

(6)

As per Equation (6), the relationships among voltage, capacitance and charge of capacitor C₁ are

$$\mathrm{d}{U}_{{\mathrm{C}}_1}=\frac{Q}{C_1}$$

(7)

Assuming a decrease in voltage of C₁ is U₀ and the reverse charge of the thyristor is Q within t_rec, the value of capacitance C₁ can be calculated by Equation (7). Based on the analysis done above, the initial voltage of C₁ needs to be higher than the sum of the voltage required to neutralize the reverse recovery charge and the voltage to charge C₂ during the duration of the reverse recovery, namely U_C2s + U_C1.

The end time point of fault breaking is referred to as the point of time when the current of the fault line at port 1 reaches the peak value and begins to drop. When the voltage across C₂ rises to the system voltage, the voltage across the line inductance is 0; by then the line current starts to decrease, deriving from Equation (4)

$$U_{\mathrm{dc}}=U_{\mathrm{dc}}-U_{\mathrm{dc}}\cos \frac{1}{\sqrt{L_{\mathrm{s}}{C}_2}}t+\sqrt{\frac{L_{\mathrm{s}}}{C_2}}{i}_1\sin \frac{1}{\sqrt{L_{\mathrm{s}}{C}_2}}t$$

(8)

Thus, the breaking time is

$$t=\sqrt{L_{\mathrm{s}}{C}_2}\arctan \left(\frac{U_{\mathrm{dc}}}{i_1}\sqrt{\frac{C_2}{L_{\mathrm{s}}}}\right)$$

(9)

The breaking time and the capacitance C₂ can be calculated by substituting system parameters into the present equation.

Taking the practical application of the MP-HDCCB into account, a relatively low value of capacitance C₂ indicates a faster speed of breaking fault current, in light of the fact that U_C2 is able to increase to U_dc more quickly, but at the same time, the voltage of charging C₂ (U_C2) is rendered too high within the time of the thyristor reverse recovery. Thus, the initial voltage of SM has to be set very high, resulting in the increase in the voltage withstood by IGBT in SM (S₁, S₂) and the increase in the number of IGBTs required to be series connected, which, in the end, boosts the cost, volume and energy loss. Therefore, the designing stage involves a thorough and in-depth trade-off between breaking time and capacitance according to specific project conditions.

On HVDC transmission lines, the value of capacitance C₂, according to the calculations above, is uF level [11], and C₁ of the mF-level capacitance value is preferable to make sure the impedance of C₂ is far lower than that of C₁.

Figure 1 shows a simplified version of typical HCB topology, in the practical engineering application; the thyristor of the thyristor transfer branch is formed by valve groups in series, so the SM needed to be series connected. The thyristor valve groups withstand TIV, and its quantity in series is determined by the line voltage, while the quantity of the SM forming series connection depends on the voltage of C₁ derived from Equations (8) and (9). The quantity of the required SM can be obtained once the parameters of thyristors are made sure of, which is the design basis for thyristor series connection and SM series connection under different DC voltage levels.

The energy dissipation branch involves mainly considering the design of two sets of parameters; one is the clamping voltage of MOV and the other is energy required to be absorbed by MOV. The energy dissipation branch involves mainly considering the design of the two sets of parameters; one is the clamping voltage of MOV and the other is the energy required to be absorbed by MOV.

Using fault current i_L(t) as the calculation target, the results of the derivation conducted on Equation (4) are

$$i_{\mathrm{L}}\left(t\right)=i_1\cos (\frac{1}{\sqrt{L_{\mathrm{s}}{C}_2}}t)+\sqrt{\frac{C_2}{L_{\mathrm{s}}}}{U}_{\mathrm{dc}}\sin (\frac{1}{\sqrt{L_{\mathrm{s}}{C}_2}}t)$$

(10)

When the energy dissipation branch is conductive, initial fault current i₂ can be obtained by substituting t₂ into Equation (8). The energy dissipation branch is equivalent to the voltage source of U_C2; at this moment the fault current decreases to 0; therefore, the total energy required to be absorbed by the energy dissipation branch consists of two parts: (1) Energy stored by the line inductor at the moment when the branch is conductive; (2) energy offered by port n after the energy dissipation branch is connected, which herein is simplified as power source U_dc.

The energy of part (1) is

$$W_1=\frac{1}{2}{L}_{\mathrm{s}}{i}_2{}^2$$

(11)

Over the process of discharging energy by MOV, the decrease in the circuit current can be regarded as a linear relationship. Thus, the time required for the current to drop to 0 is

$$t_3=\frac{L_{\mathrm{s}}{i}_2}{U_{C_2}-U_{\mathrm{dc}}}$$

(12)

The energy of part (2) provided by source supply U_dc is

$$W_2=\frac{1}{2}{U}_{\mathrm{dc}}{t}_3{i}_2$$

(13)

Thereby the total energy required to be absorbed by the energy dissipation circuit is

$$W=W_1+W_2$$

(14)

In real application scenarios, the clamping voltage of MOV is usually 1 to 2 times the rated voltage [14]; assuming the clamping voltage of MOV is U_C2s = γU_dc, at the moment of MOV conduction, there is

$$\gamma U_{\mathrm{dc}}=U_{\mathrm{dc}}-U_{\mathrm{dc}}\cos \frac{1}{\sqrt{L_{\mathrm{s}}{C}_2}}t+\sqrt{\frac{L_{\mathrm{s}}}{C_2}}{i}_1\sin \frac{1}{\sqrt{L_{\mathrm{s}}{C}_2}}t$$

(15)

The time of the charging capacitor is

$$t=\frac{\arcsin \frac{\left(\gamma -1\right)U_{\mathrm{DC}}}{\sqrt{{\mathrm{a}}^2+{\mathrm{b}}^2}}-\arcsin \frac{\mathrm{a}}{{\mathrm{a}}^2+{\mathrm{b}}^2}}{\mathsf{\omega }}$$

(16)

within which

$$a=-U_{\mathrm{DC}};b=\sqrt{\frac{L_{\mathrm{s}}}{C_2}}{i}_1;\omega =\frac{1}{\sqrt{L_{\mathrm{s}}{C}_2}}$$

(17)

As can be seen from Equation (16), setting the clamping voltage of MOV too high results in the rise in the peak voltage of C₂, leading to prolonged charging time of capacitor and, furthermore, having the time for the fault current to drop to zero increase after the DC circuit breaker completes the breaking of the fault current, which is followed by an increase in the cost of the capacitor, although the validity of the breaker is not affected.

3.2. Economic Analysis

Figure 3 shows a typical circuit breaker topology [6] when full controlled switching devices are used as main breakers.

Based on this topology, a wealth of IGBTs need to be series connected to withstand TIV, bringing about issues of voltage sharing and current sharing of full controlled devices. Yet in the proposal given in the present study, IGBT only needs to withstand the pre-charge voltage U_C1 for the reverse breaking of SCR; this voltage value is significantly lower that system voltage.

Table 1. Comparison of the number of power electronic devices in different schemes.

	IGBT	SCR	C
IGBT single port scheme	j$\times k$$\times$m	0	j
IGBT multiport scheme	k$\times$m	0	1
Hybrid switching device single port scheme	j$\times$m	j$\times$n	2j

lists the comparisons done between the quantity of power electronic devices of the present proposal and those using IGBTs as the transfer branch. Herein n stands for the number of SCRs used in the present proposal, m represents the number of IGBTs needed in the present proposal, j represents the number of the port and k is the ratio of system voltage and the pre-charged voltage on C₁, which is 500 kV/10 kV = 50 among the system parameters used in the present study. It can be seen that compared with the IGBTs multiport proposal, only one more capacitor and more SCRs are used in the present proposal. Besides, the quantity of IGBTs used in the present proposal is remarkably smaller than that of the scheme in which the transfer branch completely uses the IGBT. The voltage U_C2, previously withstood by IGBT when system voltage is exceeded, is now withstood by SCR, leading to a significant decrease in the cost of the present proposal.

In addition, series connection of thyristors is adopted in the proposed topology in the present study to achieve high-voltage application of the DC circuit breaker; IGBT is added to secure fast breaking of thyristors. Hence, in comparison with full controlled switching devices, the overall cost of the proposed topology using a hybrid switching device in the engineering application is going to be lowered significantly.

4. Simulation Results

4.1. System Configuration

In order to further assess the performance of the MP-HDCCB proposed in the present study, four-terminal modular multilevel converter High Voltage DC (MMC-HVDC) test system models are built in this section. Herein the voltage of station 2 reaches 500 kV, the rated capacities of P₁, P₃ and P₄ reach 500 MW, 750 MW and 750 MW, respectively. Figure 4 shows the locations where MP-HDCCBs are equipped and the location where the fault happens. The parameters of the simulation model system are shown in

Table 2. The parameters of the simulation model system.

Line Parameters	Resistance Per Unit Length (Ω/km)	0.014
	Inductance Per Unit Length (mH/km)	0.22
	MMC1-MMC2 (km)	200
	MMC1-MMC4 (km)	100
	MMC2-MMC3 (km)	200
	MMC3-MMC4 (km)	200
MP-HDCCB Parameters	C1 (mF)	1
	C2 (μF)	60
	C1 Pre-charge voltage (kV)	10
	MOV action voltage (kV)	750
MMC Parameters	DC voltage Udc (kV)	±500
	Rated Capacity (MW)	1500
	SM capacitor (μF)	8000
	Arm inductance Lx (mH)	150
	Arm resistance Rx (Ω)	0.147
	Limiting current inductance Lm (mH)	300
	Number of submodular N	220

.

4.2. Simulation of Fault Isolation

Figure 5 shows the currents flowing on different branches; a short-circuit fault occurs on line MMC₁-MMC₂ when t = t₀ = 3 s; the current flowing through main branch rises rapidly. When the fault is detected after 1 ms, T₁ is turned on and S1 is opened; then the LCS₁ is open; the fault current commutates from the main branch to the transfer branch and keeps rising. At this moment, the mechanical switch UFD₁ begins to open in zero current. After a delay of 2 ms, UFD₁ is fully open. S₂ is turned on so that the U_C1 provides a reverse voltage on T₁, having T₁ turned off; thus, the fault current commutates to C₂ quickly, over which the fault current reaches the peak value of 11 kA. The fault current keeps charging C₂ till the voltage across C₂ exceeds the clamping voltage of MOV and commutates to the energy dissipation branch. Afterwards, the fault current declines to 0; hereby the fault is completely interrupted.

Figure 6 shows the voltages of major components over the process of breaking fault current. The voltage across the DC circuit breaker is suppressed by MOV. The clamping voltage of the MOV set in present proposal is 50% higher than the rate line voltage of system.

Figure 7 shows the port currents of the four-terminal test system; the fault happens on line MMC₁-MMC₂ when t is equal to 3 s. It can be observed from Figure 7 that, after the MP-HDCCB at both ends of line MMC₁-MMC₂ completes breaking, the power supply on the other normal lines has not been impacted.

4.3. Parameter Influence Analysis

Figure 8 shows the effects of different capacitance values of C₂ on the current flowing through the transfer branches and the voltage across C₂; the results indicate that the lower the capacitance value is, the faster the voltage of the capacitor rises, the quicker the MOV conducts and the lower the current peak value is. However, U_C2 needs to be large enough because the breaking condition of T₁ requires U_C1 to be higher than U_C2. The time of thyristors withstanding reverse voltage is set at 70 us; namely, U_C1 is higher than U_C2 within the temporal range of 70 us. Figure 9 depicts the corresponding pre-charge voltage of C₁ required for different capacitance values.

Under the conditions that the C₂ on the capacitor transfer branch is 50 uF and the MOV protection factors are different, the changes in current flowing through the MP-HDCCB and voltage across MOV are shown in Figure 10. It can be seen that the clamping voltage of MOV does not affect the rising time of the fault current (the breaking time of the fault current) when other parameters remain unchanged, but the time for the fault current to drop to zero is influenced. In addition, it can be concluded that the higher the clamping voltage of MOV is, the shorter of the time for the current to drop to zero, the less energy that MOV needs to absorb and the shorter the time for circuit breakers to reclose. However, a too high clamping voltage of MOV results in capacitors withstanding higher voltage, which is true for series thyristors as well, giving rise to an increase in the cost and volume of switching devices. Therefore, the clamping voltage of the MOV should be selected based on proper integration of these two factors.

5. Experiment Results

The proposed MP-HDCCB was established in our laboratory according to the topology shown in Figure 1, and a scaled-down test circuit was constructed, as shown in Figure 11, to verify the effectiveness of the proposed MP-HDCCB. The parameters of the test circuit are listed in

Table 3. Major parameters of test circuit.

Parameters	Value
UDC	100 V
C1	220 uF
C2	220 uF
UC1-pre	30 V
Thyristor Module	SKKT162
IGBT Module	FF300R17KE3

.

Figure 12 shows the fault current blocking waveform after the fault occurs at port 1. The current of the main branch begins to rise at time t₁. The IGBT of the main branch is turned off at t₂. The fault current is commutated to the thyristor branch and the fault current increases continuously. The IGBT of the thyristor branch is turned off at t₃. The fault current is commutated to the capacitor branch and C₂ is charged. When the voltage on C₂ is higher than the line voltage, the fault current of the capacitor branch begins to decrease until the fault current is completely interrupted. The time from t₁ to t₂ is the fault current blocking time, which is the key index for the DC breaker. The blocking time of the experiment is 3 ms because achieving the threshold current value needs 1 ms and waiting for the mechanical switch to shut down needs 2 ms.

The waveform after magnifying the time scale at t₃ in Figure 12 is shown in Figure 13. The IGBT of the thyristor branch turns off at t₃. C1 has an initial pre-charged voltage, which causes the thyristor withstand reverse voltage at t₃. The current through the thyristor branch is commutated to the capacitor branch while the current through the capacitor branch increases rapidly. The voltage of C₁ must be greater than the voltage of C₂ at t₄ to ensure that the thyristor is able to withstand the reverse stand-off voltage during its reverse recovery process. When the thyristor is turned off, the current is completely commutated to the capacitor branch and the fault current starts to charge C₂ of the capacitor branch.

Adjusting the value on C₂ to 100 uF, and the fault current blocking process is shown in Figure 14. The fault current is normally commutated to the thyristor branch at t₂. However, the current of the thyristor branch is not completely commutated to the capacitor branch at t₃. After the thyristor is turned off, the thyristor is turned on again, resulting in the current of the thyristor branch rising to the line current again. Figure 15 shows a detailed view of the enlarged time scale at t₃ in Figure 14.

The thyristor is turned off and the thyristor branch current begins to decrease at t₃ along with the fault current charges C₂. However, since the value of C₂ is too small, the voltage on C₂ was higher than the voltage on C1 at t_3-1 while the thyristor began to withstand the forward voltage before the end of the reverse recovery process. The thyristor was restored to the conductive state, and the current was commutated back to the thyristor branch, causing the failure of fault current interruption.

The proposed MP-HDCCB topology in a practical engineering application is shown in Figure 16. The thyristor transfer branch, which is formed by thyristor and SM, needs to withstand DC bus voltage. Because the cost and difficulty of the thyristor series is smaller than the SM series, the thyristor series is used to withstand the high voltage and the SM is used to turn off the current quickly. The thyristor series scheme is in widespread use [22,23,24]; the proposed topology reliability could be assured. The pre-charge voltage of C₁ is still satisfied concerning Equations (6) and (7), and the reverse charge Q is the sum of thyristor T₁ − T_n.

6. Conclusions

A multiport hybrid DC circuit breaker topology based on hybrid switching devices was proposed in the present study; comparisons of performance between the proposed topology in this study and a conventional scheme involving multiport hybrid DC circuit breakers were conducted, and the conclusions are as follow:

(1) The working principles and parameters of the proposed MP-HDCCB were studied and analyzed. It was concluded that this proposed scheme is capable of breaking the fault current reliably and isolating faults without impacting the normal operation of other lines.

(2) The proposed MP-HDCCB only needs one thyristor transfer branch, one capacitor transfer branch and one energy dissipation branch. The current of the thyristor transfer branch is unidirectional conduction, and the bidirectional fault current is solved by the clamped diode.

For the unidirectional current blocking, the scheme adopts full controlled switching devices in the thyristor transfer branch to ensure the rapidity of the breaking current, and the semi-controlled switching devices are connected in series to withstand TIV. According to the multiplexing transfer branch, unidirectional conduction and semi-controlled switching, the quantity of the full controlled switching devices is significantly reduced, showing a certain degree of application value in lowering the relevant project cost and technical difficulty.

(3) In order to turn off the thyristor, the capacitance value and pre-charge voltage should be configurated effectively to solve the problem of thyristor reverse recovery.