A Review on Modular Converter Topologies Based on WBG Semiconductor Devices in Wind Energy Conversion Systems
Abstract
:1. Introduction
2. The Role of Semiconductor Power Devices in WECSs
2.1. Modular Multilevel Converter
2.2. MMC SM Structure Based on Si Devices
2.2.1. Unipolar SMs
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- Half-bridge SM (HBSM): The most-common type of unipolar circuit due to its simple structure and cost. Figure 3a shows the HBSM’s structure, which mainly consists of two IGBT switches (S1, S2) connected with a single capacitor 𝐶 and operating in a complementary manner to produce two voltage levels at the output side (0, VC). The cell of the HBSM has a lower power loss compared to other topologies. However, it has a clear shortcoming against DC faults [57].
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- Single-clamped submodule (SCSM): This type of circuit was introduced to control the DC fault current problem without a significant increase in power loss and cost, as this kind is typically used in hybrid MMC topologies. Compared to HBSMs, the modified SM circuit has one further IGBT switch connected along with an additional diode 𝐷4 connected with the split DC capacitor C1 acting to provide the path of the current during DC faults. Figure 3b shows the SCSM structure, which can produce two output voltage levels (0 or VC), whereas during normal operating conditions, the switch S3 remains on constantly. The cell voltage is inserted against the fault currents because only two of the four diodes act at any instant. The main advantage of SCSMs is the ability of fault handling with only three switches, which results in lower power losses compared with other structures [53,58].
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- Half-voltage clamped submodule (HVCSM): Its structure is shown in Figure 3c, where three IGBT switches are connected in series with two capacitors. An additional protective diode D4 is connected instead of the IGBT switch. The HVCSM uses the voltages of the submodule capacitors to eliminate the freewheeling impact of diodes actively and achieve fast fault clearance and converter restart. The switch S3 is placed in the opposite direction to the S1, S2 switches to enable stopping the rectifier mode by turning the switch S3 off [59]. The main disadvantage of this cell structure is the difficulty of balancing the capacitors’ voltage when the arm current is negative. Furthermore, it suffers from higher conduction losses compared to the HBSM [56].
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- Asymmetrical unipolar full-bridge submodule (AUFBSM): This consists of three IGBT switches (S1, S2, and S3), four diodes, and two capacitors, as shown in Figure 3d. This modified cell SM is suitable for hybrid MMC-HVDC applications and has been introduced to overcome the DC fault current problems. In normal operating systems, S3 is always on, while in the case of a DC fault, all switches must be off, and the current will flow through the complementary capacitors (C1, C2), increasing their voltages. Asymmetric UFBSMs have the ability to block DC fault currents with less power loss compared to other cells [60].
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- Series switch submodule (SSSM) topology: The SSSM is an extension of the HBSM topology. Figure 3e shows the basic structure of this cell, which consists of two power switches connected in parallel with a capacitor, and an additional IGBT switch with a low voltage rating is required to be connected to the conventional HBSMs. It can be used for HVDC transmission systems, where the HVDC system is capable of blocking the fault current under DC-cable short-circuit conditions based on this model. Compared to the FBSM and hybrid SM types, the cost of the SSSM-MMC type is about 59.4% and 79.2%, respectively. Additionally, the power loss of the semiconductor devices of the SSSM is lower than that of the FBSM and comparable to the hybrid SM type [61].
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- Unipolar full-bridge submodel (UFBSM): The structure of this SM is based on the full-bridge SM, in which the IGBT S3 and its parallel diode are replaced by the diode D3, as shown in Figure 3f. During normal operation, the SM can generate two voltage levels by controlling switches S1 and S2; the SM is inserted/bypassed, while the switch S4 is always on. The UFBSM can block DC fault currents and provide DC-fault-handling capability. However, the conduction losses of the S4 contact switch are greater than those of any of the other switches [62].
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- Stacked switched capacitor (SSCSM): This is illustrated in Figure 3g. This topology is an enhanced unipolar SSCSM comprising six power switches and three capacitors (C1, C2, and C3). The physical volume of all capacitors in the SSCSM can be up to 60%. The performance of the SSCSM-based MMC model was found to be similar to that of the HB-based system. However, one of the main drawbacks of the SSCSM structure is the increased number of power devices, which leads to an increase in the power losses of between 7% and 15% during rated power operation [63].
2.2.2. Bipolar SMs
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- Full-bridge circuit or bridge cell (FBSM): This cell is widely used in multilevel converter topologies. Figure 4a shows the FBSM topology, which consists of four IGBT switches (S1, S2, S3, and S4) connected with a single capacitor C. This type of cell structure can supply both positive and negative voltages at its output terminals (+VC and −VC), where the output voltage is either equal to the voltage of its capacitor 𝑉𝐶 (switched on/inserted state) or zero (switched off/bypassed state), which depends on the switch states of the switches. The main feature of this SM is the capability of DC fault blocking and its suitability for connection with either AC or DC systems. However, the increased number of semiconductor switches in the structure of the FBSM may cause additional power losses and increase the cost of the total MMC compared to the HBSM-based MMC [64].
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- Diode clamped submodule (DCSM): This topology is also known as a neutral pinned point switch (NPPS) [13]. DCSM structures have been widely used in industrial medium-voltage applications. As shown in Figure 4b, three levels can be generated by two series cells in the upper and lower arms, which are connected to two bulk capacitors (C1, C2). The employed NPC technique has good output voltage quality as the cell can produce three output voltage levels (0, Vdc/2, and −Vdc/2). On the downside, this SM topology suffers from the complex capacitor voltage balancing, high power losses, and hence, low efficiency compared to other bipolar cells [65].
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- Flying capacitor submodule (FCSM): This bipolar SM circuit is an extension of the HBSM by using flying capacitors. The FCSM has the capability of generating three voltage levels (0, VC, and −VC). Figure 4c shows the cell structure where four switches are connected to a clamping capacitor via the upper and lower arms [14]. In the case of an increase in the number of voltage levels, an additional internal voltage balancing for the FCs is required. This SM structure is not attractive for MMCs due to the lack of modularity and reliability [66].
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- Double-submodule circuit (DSM) topology: The DSM model was introduced to improve the balancing of capacitor voltages at low switching frequencies. Figure 4d illustrates the basic structure of this SM cell, which consists of two capacitors and eight power switches to achieve three voltage levels. The DSM offers several advantages, including a reduction in capacitor voltage ripple, especially at low switching frequencies, and a reduction in size and cost [67].
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- Clamp-double circuit (CDSM): As shown in Figure 4e, the CDSM topology consists of two HBSMs connected in series through two diodes and additional integrated IGBT switch S5 in the middle. During the normal operation of CDSMs, the middle switch S5 is always switched on and capable of generating a negative voltage at its output terminal. It includes an increased number of series semiconductors in the conduction path compared to the FBSM. The CDSM configuration also allows the parallel connection of the capacitors within each SM bridge, which results in the low-frequency operation of the MMC topology, as it can reduce the ripple of capacitor voltage [56,67].
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- Mix-connected submodule (Mix SM): As shown in Figure 4f, the structure of the Mix SM combines the HB and FBSM topologies to generate the necessary negative polarity voltage for DC-side fault blocking. It can be considered as a hybrid configuration topology operating as HBSMs during the steady state. During faults, the HB leg provides voltage and current blocking as required [53].
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- T-submodule 1 (TSM1): The TSM1 and TSM2 topologies are designed for modular multilevel-converter-based HVDC systems. Figure 4g shows the TSM1 circuit, which consists of two unidirectional IGBTs with antiparallel diodes, one four-quadrant bidirectional switch in a common emitter configuration, and two capacitors (C1 and C2), whose voltages are controlled to be equal. TSM1 can generate three voltage levels (VC, VC/2, and 0) depending on the full-on, half-on, and bypass states. The new TSM topologies add additional benefits such as reduced voltage stress across the extra inserted switch and considerably lower semiconductor losses compared to the traditional HBSM. However, both the TSM1 and TSM2 topologies have shortcomings against DC faults [43].
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- T-submodule 2 (TSM2): TSM2 is unlike the HBSM topology as it only produces two voltage levels. Figure 4h shows TSM2, which operates similarly to TSM1. The SM structure comprises two unidirectional IGBTs with antiparallel diodes, with conduction occurring through two antiparallel diodes and an IGBT switch, and two capacitors (C1 and C2), whose voltages are controlled to be equal. Three voltage levels (VC, VC/2, and 0) can be generated depending on the switching states. The power losses in the TSM2 topology are higher than in TSM1, but this eliminates the need for an additional IGBT [43].
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- Cross-connected submodule (CCSM): As shown in Figure 4i, this SM consists of two half-bridge cells connected back-to-back in a crossed fashion via the cross-switches (S5, S6). Depending on the different switching states, this structure is able to generate a symmetrical five-level output voltage of 2Udc, Udc, 0, −Udc, and −2Udc. This SM topology has the capability of blocking a short-circuit current. However, the ratings of the semiconductors for the cross-switches and the comparatively high count add some complications to the CCSM configuration [68].
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- Semi-full-bridge submodule (SFBSM) topology: The SFBSM topology is an extension of the CDSM model with some differences. Instead of two diodes, active switches are used, which changes the submodule’s function and operating principles. The SFBSM configuration consists of two FB cells with two capacitors in both cells. These capacitors can be connected in parallel with both positive and negative polarity, which can increase the modulation index above unity or provide more voltage levels with fewer capacitors. However, there may be a slight difference between the capacitor voltages due to differences in the capacitance values, resulting in a current spike when they are connected in parallel. This can lead to some energy losses, but they are generally small [64,69].
2.2.3. Other MLI Topologies
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- Cascaded H-bridge multilevel inverter (CHB-MLI): The first CHB-MLI was suggested by Baker and Bannister in [72]. The basic model of the CHB inverter consists of a series connection of H-bridges with separate DC sources, as shown in Figure 5a. By cascading a number of H-bridge cells and each cell being supplied by an isolated DC source, a high number of voltage levels can be generated theoretically. The CHB-MLI topology offers several benefits. Firstly, it has a compatible structure, which makes it easy to modulate, control, protect, and maintain during failures. Secondly, it can handle higher voltages without voltage imbalance. Thirdly, it can eliminate common-mode voltages by selecting the proper modulation scheme. Fourthly, it produces an almost sinusoidal output, which means that an output filter is almost unnecessary. Fifthly, it requires fewer components compared to other topologies. Sixthly, it does not require flying capacitors or clamping diodes. Lastly, it has a uniform distribution of load power among all switching devices. Despite these advantages, this topology has some serious drawbacks such as requiring numerous separate DC sources and many DC link voltage controllers. The CHB-MLI topology finds applications in various fields, including the RER interface, motor drives, electric vehicle drives, laminators, blowers, fans, conveyors, DC power source utilisation, frequency link systems, and power factor compensators [71,73].
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- Packed U cell inverter (PUC) topology: The PUC topology consists of packed U cells, and each U cell comprises an arrangement of two IGBT power switches connected via one capacitor, as shown in Figure 5b. This type of inverter is capable of generating a seven-level voltage at its output terminal. The PUC offers high-energy conversion quality using a small number of power devices and capacitors, resulting in a low production cost [74]. Recently, a new configuration of a single DC source hybrid packed U cell (H-PUC) converter was proposed in [75]. This topology requires one DC source, twelve IGBT power switches, and three capacitors to provide a 23-level output voltage. Figure 5c shows the circuit structure comprising two high-voltage, low-frequency (LF) and low-voltage, high-frequency (HF) SMs, which lead to lower power losses and higher efficiency.
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- Packed E cell inverter (PEC) topology: In the PEC inverter, the U cells in the PUC inverter are replaced by E cells, which are packed cell structures. The E cells consist of two capacitors, which are shunted by a four-quadrant switch to form a single cell, as shown in Figure 5d. The two capacitors are actively balanced and simultaneously charged or discharged with redundant states to achieve nine voltage levels. The basic idea behind the E cells is to use a combination of capacitors and switches to achieve multiple voltage levels with fewer semiconductor devices. By using two capacitors in a shunt configuration, the E cell can be charged or discharged to one of nine possible voltage levels, depending on the state of the four-quadrant switch. One of the main advantages of this topology is that it reduces the number of semiconductor devices required compared to the PUC topology, which leads to lower power losses and cost. Additionally, the active balancing of the capacitors helps to ensure that the voltage levels are accurately maintained, resulting in a more-stable output voltage [76]. In addition, the boost packed E cell (BPEC) inverter was recently proposed based on the conventional PEC topology [77]. The single-phase BPEC is capable of generating a symmetrical 11-level voltage waveform using eight IGBT power switches and three DC capacitors in two DC links. The bottom two capacitors are connected in series and form the second DC link. This inverter topology is suitable for flexible AC transmission systems (FACTSs) and active power filter (APF) applications due to its multiple advantages, such as boost performance, low harmonics, low-voltage DC link, low-voltage stress, fault tolerance, and small size filter requirements. These advantages make the BPEC an affordable and reliable inverter.
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- Series-connected switched-source multilevel inverter (SCSS-MLI): The SCSS-MLI topology involves connecting voltage sources in series using power switches. A diagram of this configuration is shown in Figure 5e. The semiconductor power switches are connected to the poles of the voltage sources with lower magnitudes, and they are also connected to the poles of the voltage sources with higher magnitudes from an upstream source. This link is capable of synthesising a DC voltage with multiple levels, considering both polarities using the H-bridge. This structure reduces the number of switches required for the symmetrical inverter structure. However, this topology has several drawbacks, such as requiring power semiconductors with the same rating, making load sharing impossible due to various input stage configurations, and high-rated switches that need to be switched at the minimum possible frequency [73].
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- Nilkar multilevel inverter (N-MLI) topology: Figure 5f illustrates the basic module of the N-MLI, which consists of four IGBT power switches and two identical DC voltage sources with four semiconductor switching units for generating a staircase DC voltage waveform with positive polarity. The N-MLI can generate more voltage levels at the output terminal. In comparison with other classical MLI topologies such as the CHB, NPC, and FC multilevel inverters, the N-MLI offers additional advantages such as a smaller number of power switches, leading to the reduction of the size and power loss, a low THD, high efficiency, and a simple gate drive and control strategy [78].
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- Reversing-voltage multilevel inverter (RV-MLI) topology: The idea of the reversing-voltage MLI topology was initially proposed by Najafi et al. This topology generates a sinusoidal output voltage in both the level-generation and polarity-generation stages. The level-generation stage produces positive voltages, while the polarity-generation stage produces negative voltages, as illustrated in Figure 5g. This topology can be expanded to include any number of levels, allowing it to be applied to three phases as well. It offers flexibility in terms of switching sequences and requires only a few components to function, making it useful in applications such as FACTSs and HVDC. However, using different DC sources is not feasible in this topology because it is impractical to combine additive and subtractive DC sources [73,79].
3. MMC Modulation and Control Techniques
3.1. Multicarrier PWM Techniques
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- Level-shifted pulse width modulation (LS-PWM): The gate signals of power devices in each cell are immediately specified by comparing the reference voltage signal with the carrier’s signals. N is the number of carrier waveforms required in the control system, where these carriers are placed vertically, and their bands are arranged based on the LS techniques. The total switching of all the SMs in the upper and lower arms of the MMC topology will be equal to the carrier frequency, meaning that the number of SMs can be assumed to be four cells in both arms, in which case four N carriers will be used and vertically distributed from −Vdc/2 to Vdc/2 volts, and their magnitude is 0.25 to modify the waveform where the modulating waveform is shifted by fully turning on some of SMs and other SMs being turned off (bypassed) to generate an N − 1 voltage level at output side [89,90]. As shown in Figure 6, the most-common multiple carrier level-shifted techniques used for MMC control systems are classified into the: in-phase disposition (PD PWM), opposition disposition (OD PWM), and alternative opposition disposition (AOD PWM) techniques [91]. Figure 8 shows five level output waveforms of the aforementioned techniques, where in the PD PWM technique, the carrier signals are level-shifted, but all are in same phase. In the POD PWM technique, the positive carrier signals will have a 180° phase shift with the negative carrier signals, and in APOD PWM, the alternate carrier signals will have a 180° phase shift. The PD PWM control strategy has gained wide acceptance in the design of the MMC topology compared to other control technologies as this technique provides load voltage and current with lower losses and less total harmonic distortion (THD) [70].
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- Phase-shifted pulse width modulation (PS PWM): The configuration of the MMC topology is based on connecting a number of SMs, which are used in each phase leg to control the flow of the current and voltage to the load through an integrated system [92]. In this modulation technique, each SM in the MMC topology is controlled separately, and the balancing voltage function for each cell is divided into an averaging control and a balancing control, where (N + 1) levels require several triangular carrier waveforms, and all carriers must have the same frequency and peak of the amplitude as there is a phase shift between the adjacent carriers, this shift being given by φc = 360°/N. Therefore, the waveforms of triangular carriers for each phase are implemented according to the subharmonic techniques [93]. The average voltage at each individual SM capacitor is controlled by the averaging and balancing technique, respectively. The main drawback of the PS PWM technique is that the implementation voltage rises significantly when the number of SMs in each arm phase is increased, which leads to instability under certain operating conditions [94].
3.2. Direct Modulation
3.3. Indirect Modulation
3.4. Closed Loop Control Technique
3.5. Open Loop Control Technique
3.6. Selective Harmonic Elimination Technique
3.7. Space Vector/Nearest Vector Control
3.8. Model Predictive Control
4. WBG Semiconductor Device Technology
4.1. SiC Technology
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- At the converter level: by directly replacing the Si devices by SiC ones or simplifying the circuit topologies to improve the converter efficiency, fast switching capabilities, low power loss, and reducing the active and passive component numbers to reduce the converter size.
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- At the system level: converter topologies based on SiC switches are able to provide a better dynamic performance, high frequency capability, and high bandwidth enabled by the fast switching speed.
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- SiC can enable new applications such as solid-state transformers (SST) with high-efficiency and high-density, as well as high-speed motor drives. Recently, several commercial and research prototype inverters using SiC devices have been developed with promising results, which have shown a significant improvement in efficiency and power density.
4.2. Development of SiC Power Devices
4.3. SiC’s Key Challenges
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- SiC wafer and substrate fabrication: A SiC wafer is a semiconductor material that has excellent electrical and thermal properties. However, the SiC wafer has some drawbacks such as crystallographic defects within the wafer, and surface defects at or near the wafer surface still remains a challenge for manufacturers as improving SiC wafer quality is important for manufacturers because it directly determines the performance of the SiC devices [136].
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- SiC physics and device development: This means the development of the theoretical design of SiC-based devices, as well as the practical problems associated with the planning, fabrication, and construction of device circuits or integrated circuits (ICs). The related issues that need some improvements are: (i) the ohmic contacts and (ii) the strong dielectric oxide layers, whereas the essential step for making discrete devices able to withstand high temperatures is the proper passivation of the devices [137].
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- SiC device modelling: The ability to develop and validate accurate device models using modern computer simulation software programs is essential. Thus, users need to be able to simulate their own circuits and design the system with the SiC devices.
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- SiC packaging: The packaging of SiC devices has been mostly based on a wire bonding approach on a ceramic substrate, which is a standard method to form interconnects for multichip modules (MCMs), due to its ease of use and relatively lower cost. However, this packaging method has indicated that it is a technical barrier in moving to a higher-performance system enabling operation at high temperatures due to its inherent limitations [138].
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- SiC high-speed switching challenges: Although SiC devices are superior in high switching performance compared to their Si counterparts, special consideration needs to be given to fully benefit from their fast-switching feature. The fast-switching transients lead to some issues with the device and package internal electromagnetic parasitics, which are becoming fundamental barriers to the high-performance switching of SiC power devices, which needs to be fixed [126].
4.4. GaN Technology
4.4.1. Development of GaN Power Devices
4.4.2. GaN’s Key Challenges
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- Material growth: High-quality materials are the core of GaN-based power devices. Compared to the conventional Si material, the contact mismatch between SiC and sapphire is smaller, and it has higher thermal conductivity, which is a necessary feature for high-power conversion devices [155]. Nevertheless, the practical use of the devices is limited due to the high cost. Despite the large lattice mismatch between GaN and Si, its cost is lower as the lattice mismatch could be attenuated with the buffer layer preface for stress management. Therefore, the Si substrate is still the mainstream material of GaN-based power devices. Furthermore, due to the heterogeneous structure of GaN devices as the power devices, GaN technology is mainly a lateral structure, which makes these devices preferable in the high-frequency field, but also limits their high-power characteristics. At present, the further development and improvement of GaN-based switches by the semiconductor manufacturers have shown that GaN power devices with a rated voltage up to 1200 V will be more suitable for medium and high voltage [156].
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- Suppressing the collapse current effect: The effect of the current collapse of the AlGaN/GaN HEMT power devices is one of the major challenges that must be solved to achieve the success of GaN devices in high-power converters. The current collapse effect occurs when a great bias is applied to the drain terminal, where the leakage of the current decays, as shown in Figure 19. The phenomenon of the current collapse effect of GaN devices mainly includes the following [157,158]:
- The carrier traps resulting from the deep level centres in the material create the collapse of the current.
- The polarisation charge modification resulting from the surface effect and the surface state leads to a decrease in the concentration of 2DEG in the conductive AlGaN/GaN channel, which drives the current collapse.
- The structure of the material and the border of the energy band structure are critical parts because some disturbances will impact the 2DEG and cause current collapse [122]. However, there are some techniques that have been used to suppress the current collapse such as surface passivation treatment [123], the field plate structure [124] and the growth of the P-type cap layer [125].
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- Vertical isolation: The vertical isolation is one of the challenges of GaN device, which is affected by the dependence of the conductive substrate potential and drives a back-gating impact. A potential solution for this problem can be implemented by further development of the GaN buffer thickness or by replacing the step-graded buffer of Al-GaN/GaN with a superlattice buffer [159]. Another approach is to use Qromis substrate technology (QSTR) with deep trench isolation and a topical substrate connect [160]. These potential modes help avoid the backdoor effects. However, the GaN-on-Si with an improved buffer may lead to increasing the device’s cost compared to the Si technique. On the wafer level, this can be achieved by wafer transfer techniques in a second carrier substrate or by using the remaining frame for selective Si removal with mechanical stabilisation. At the package level, the printed circuit board (PCB) carrier substrate, which is the material that connects the tracks and components that form the basis of a printed circuit board, with embedded GaN-on-Si ICs can be used to remove the Si substrate [161].
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- GaN-based complementary metal–oxide semiconductor (CMOS) technology: There have been various demonstrations of GaN-based ICs. These demonstrations are based on the d-mode and e-mode integration of n-type AlGaN/GaN HEMTs. However, these technologies suffer from the static power dissipation and reduced voltage swing at the output terminal, where the GaN power IC technology also allows a p-GaN layer to be used for a p-channel transistor, and the first structure of a p-channel field effect transistor (P-FET) was realised in [162]. Then, both transistors were integrated into a GaN CMOS inverter and published in [163], but this technology also suffers from the lack of high performance, and the challenges of its monolithic integration with e-mode n-FET devices are the main roadblocks towards achieving a better technology since the integration of GaN p-FETs with n-FET devices is more expensive. Thus, the design of a more-efficient gate driver circuit may be required, and further peripherals are feasible through this extension [164].
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- The possibility of the combination of vertical and lateral device technologies: During the last two decades, power devices based on GaN technology have been reasonably improved by delivering commercial transistor types with operating voltages up to 1200 V such as a novel normally off GaN vertical transistor with submicron fin-shaped channels, which was published in [165]. In this device, the technology needs only n-GaN layers with no request for epitaxial regrowth or p-GaN layers and specific RDS (on) 0.2 mΩ, where the flow of the electrons from the source to the drain modified by the gate deposited on the sidewalls of a narrow sub-micron fin as the width and doping of the fin determines the threshold voltage of the device. A breakdown voltage over 1200 V has been demonstrated with a high on current up to 25 KA/cm2 and a low off current at 1200 V below 10−4 A/cm2, which makes rendering an excellent Baliga’s figure of merit up to 7.2 GW/cm2. The vertical and lateral GaN devices have the potential to serve a large range of power-switching applications. Thus, the integration of the lateral and vertical structures with a focus on the features of both technologies may lead to an improved transistor with better performance [166]. However, there are some challenges that need attention during the integration of both devices such as the substrate, P-GaN ion implantation, where ion implantation is a common method for Si doping of SiC, channel mobility, and e-mode operation [164,167].
4.5. Hybrid Device Technology
5. Comparison of Si with WBG-Based Devices
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- WBG materials have the potential of operating at higher temperatures up to 300 °C due to their energy gap width of three-times that of the Si material, which has a maximum temperature around 150 °C.
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- The WBG materials’ critical breakdown voltage is around ten-times that of the Si material. Therefore, the electric breakdown voltage strength is greater in SiC and GaN materials than Si. Additionally, WBG-based devices usually have a lower resistance value, which makes these devices have less conduction loss.
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- WBG materials have higher electron mobility compared with the Si-based material, which means the speed of electrons under an electric field is higher, indicating less electrical on resistance.
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- WBG materials have a higher switching frequency (speed), which means switching between the on and of states is higher for WBG technology compared to the Si-based material.
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- In terms of higher thermal conductivity, SiC-based devices have a thermal conductivity three-times greater than Si-based power switches, which means the thermal resistance is lower and the junction temperature rises at a lower rate compared to Si devices.
5.1. Si IGBT and SiC MOSFET Hybrid Technology
5.2. Integration of Si Devices with GaN HEMT Technology
6. Summary
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- Devices based on WBG power semiconductors typically have a thinner body and lower resistance RDS (on), where the lower resistance value results in a lower temperature and, hence, lower conduction losses, where replacing conventional devices in the MMC topology with devices that have a lower RDS (on) will result in less heat and lower power losses [186].
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- The power devices based on WBG materials have a higher breakdown voltage due to their high electric breakdown field. For example, the Si Schottky diodes are available at rated voltages of less than 300 V, while the commercial SiC Schottky diodes are usually available with rated voltages up to 600 V.
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- The market for WBG-based power semiconductors offers switches with different voltage levels such as SiC devices that are available at rated voltages up to 1700 V and current ratings of 80 A. GaN devices have a rated voltage up to 1200 V and current up to 90 A, allowing these devices to be used in the MMC topology for WECSs [171,179].
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- WBG power devices have a high thermal conductivity, as shown in Table 3 (1.5 W/cm-K for Si, 4.9 W/cm-K for SiC, and 2.3 W/cmK for GaN). Consequently, power devices based on WBG technology have lower junction thermal resistance (Rth-jc). This means that removing the heat from the device is easier, which results in a slowdown in the increase of the device temperature [191].
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- Semiconductor power devices based on WBG technology can operate at a high temperature as SiC devices can operate at high temperatures up to 300 °C, while GaN devices can operate at temperatures up to 225 °C. This is to be compared with the Si devices, where the maximum operating temperature is only up to 150 °C, where devices that have the ability to operate at higher temperatures can be beneficial by reducing switch failures in the MMC system.
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- Power devices based on WBG technology are more reliable since they have slightly different forward and reverse characteristics with temperature and time.
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- Power devices based on WBG materials have a superior recovery property with lower current reverse recovery. This leads to a reduction in switching losses and EMI, and there is less need for snubber circuits.
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- Semiconductor power devices based on WBG materials can operate at higher frequencies (>20 kHz). These devices with fast switching will be useful for the MMC topology.
7. Conclusions
Author Contributions
Funding
Data Availability Statement
Acknowledgments
Conflicts of Interest
References
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Modulation/Control Scheme | Merits | Demerits |
---|---|---|
MMC [39,40,48,80] |
|
|
NPC [17,81] |
|
|
FC [39,82,83] |
|
|
CHB [17,71,84,85] |
|
|
SCSS [56,73] |
|
|
N-MLI [73,78] |
|
|
RV-MLI [79] |
|
|
PUC [74,75] |
|
|
PEC [76,77] |
|
|
CCHB [56,73] |
|
|
CCSSM [68] |
|
|
Modulation/Control Scheme | Merits | Demerits |
---|---|---|
Open loop system [41,98] |
|
|
Closed loop system [96,97] |
|
|
Phase-shifted PWM technique [86,88,89] |
|
|
SHE technique [100,101,102] |
|
|
SVC technique [106,108] |
|
|
MPC technique [109,111] |
|
|
Properties | 1st-Generation | 2nd-Generation | 3rd-Generation | |
---|---|---|---|---|
Si | GaAs | SiC | GaN | |
Energy bandgap EG (eV) | 1.12 | 1.4 | 3.2 | 3.5 |
Breakdown field EB (V/cm) × 106 | 0.3 | 0.4 | 2.2 | 3.3 |
Saturation drift velocity vs (cm/s) × 107 | 1 | 2 | 2.7 | 2.7 |
Thermal conductivity (W/cmK) | 1.5 | 0.5 | 4.9 | 2.3 |
Permittivity εr | 11.8 | 12.8 | 9.7 | 9.5 |
Electron mobility μn (cm2/Vs) | 1500 | 8500 | 650 | 900–2000 |
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Athwer, A.; Darwish, A. A Review on Modular Converter Topologies Based on WBG Semiconductor Devices in Wind Energy Conversion Systems. Energies 2023, 16, 5324. https://doi.org/10.3390/en16145324
Athwer A, Darwish A. A Review on Modular Converter Topologies Based on WBG Semiconductor Devices in Wind Energy Conversion Systems. Energies. 2023; 16(14):5324. https://doi.org/10.3390/en16145324
Chicago/Turabian StyleAthwer, Abdulkarim, and Ahmed Darwish. 2023. "A Review on Modular Converter Topologies Based on WBG Semiconductor Devices in Wind Energy Conversion Systems" Energies 16, no. 14: 5324. https://doi.org/10.3390/en16145324
APA StyleAthwer, A., & Darwish, A. (2023). A Review on Modular Converter Topologies Based on WBG Semiconductor Devices in Wind Energy Conversion Systems. Energies, 16(14), 5324. https://doi.org/10.3390/en16145324