A Switched Capacitor Inverter Structure with Hybrid Modulation Method Lowering Switching Loss

Abstract

The high-frequency modulation method (HFM) for a switched capacitor (SC) inverter often leads to high switching loss since it increases switching frequency. In order to reduce the switching frequency and switching loss in the HFM for SC inverter, this paper proposes a novel hybrid modulation strategy as well as a corresponding demo switched capacitor topology. The hybrid strategy limits the number of high-frequency switches, thus reducing the switching loss significantly. Meanwhile, the demo topology maintains the merits of current switched capacitor inverter such as low switch count, quadruple voltage-boosting ability and self-balancing capacity. The principle of the hybrid modulation method and the circuit configuration of the inverter are analyzed in detail. And comparisons are introduced to demonstrate the advantages of the proposed modulation method and topology. Finally, experimental results have proved the feasibility of the proposed inverter.

1. Introduction

Compared with conventional two or three-level inverters [1], multilevel inverters show greater advantages such as lower total harmonic distortion (THD), less voltage change rate (dv/dt) and reduced electromagnetic interference (EMI) [2]. Therefore, they have been widely applied to various industry occasions such as photovoltaic (PV) generation systems [3], electric vehicles [4], active power filters and motor drives [5].

The topology structure and modulation strategy are the two most important factors that influence the quality of the multilevel inverter. Traditional topologies of multilevel inverters include the cascaded H-bridge topology (CHB) [6], neutral point clamped topology (NPC) [7] and flying capacitor topology (FC) [8]. The CHB topology employs a large number of independent sources while an FC inverter needs too many capacitors, which increases the volume of power devices. An NPC inverter has the disadvantage of voltage imbalance during operation. Therefore, additional equipment to control capacitor voltage is necessary.

Recently, a new branch of multilevel inverter topology called a switched capacitor structure has emerged. Researchers have paid great attention to designing SC inverters with less component count, reduced voltage stress, self-voltage balance ability and voltage-boosting ability. For instance, two step-up inverters with extension ability have been introduced in [9,10]. These two inverters both have a staircase structure to increase the level number and apply a backend H-bridge to determine the polarity of the output. Self-balance ability and low switch count are the main advantages of the inverters. However, power switches in the backend H-bridge have to withstand maximum output voltage, which significantly increases the voltage stress of the inverter. To reduce the voltage stress, SC inverters without H-bridges have been successively proposed in [11,12,13,14,15,16,17,18]. The topologies proposed in [11,12] are all seven-level SC inverters. Compared with [9,10], they have lower voltage stresses. However, they employ a large number of power devices. There are also SC inverters generating nine output levels [13,14,15,16]. The hybrid inverters proposed in [13,14] feature reduced switched counts and simplified control strategies since they only use four pairs of complementary signal power switches. However, their boosting factors are only two. The nine-level inverters with quadruple boost ability are proposed in [15,16]. They have high voltage-boosting ability and low voltage stress, whereas they utilize too many semiconductor switches, diodes and capacitors. To further increase the number of output levels and reduce the total harmonic distortion (THD), 13- and 17-level inverters have also been proposed by researchers. In [17], Ye proposed a 13-level inverter with a reduced switch count and high boosting ability, and he further improved the topology in [18]. The 17-level SC inverters are proposed in [19,20,21], all of which show their pros and cons, respectively. The topologies presented in [19,20] both have the advantage of a low component count, but the capacitor voltage in [19] cannot balance inherently and [20] employs more than one DC source. The inverter proposed by Kaibalya Prasad Panda [21] has a low capacitor count, single input source and self-voltage balance. Nevertheless, three power switches have to withstand peak output voltage.

On the other hand, the modulation method also significantly affects the power quality of the multilevel inverter. The modulation strategy of the multilevel inverter includes high-frequency modulation and fundamental frequency modulation (FFM). High-frequency modulation, which uses triangular carrier wave to determine the output, is employed more widely than FFM because it reduces the THD of the output and makes the filter design easier. However, the frequency of the triangular carrier signal in HFM is always much higher than the fundamental frequency. This leads to many switches, including those with high blocking voltage, operating at a high switching frequency. As a result, it will increase the switching loss of the inverter significantly. Taking [18] as an example, the modulation strategy as well as the switching signal proposed in this paper is demonstrated in Figure 1. It can be seen from the figure that all the switches except Q₁ operate at a high switching frequency, among which S₁, S₂ and S₃ have high blocking voltage (3 V_dc). If the frequency of the carrier signal increases, the switching loss of the inverter will increase significantly and may become unbearable.

To reduce the switching frequency and loss in an SC inverter under high-frequency modulation, this study proposes a novel hybrid modulation strategy and a generalized switched capacitor topology configuration suitable for using this modulation method. And it further gives a specialized 17-level switched capacitor demo topology based on the generalized configuration. The demo topology maintains the advantages of most SC inverters, such as self-voltage balance, high boosting gain and a single DC supply. The most prominent feature of the demo topology is that it reduces the switching loss significantly under the hybrid modulation because only switches with minimum blocking voltage work with high switching frequency and the switching frequency of other switches do not exceed seven times of the fundamental frequency. Therefore, it reaches a balance between the output THD and switching loss.

The rest of this paper is organized as follows: Section 2 will give the proposed generalized SC configuration and the principle of the proposed hybrid modulation strategy. Section 3 will introduce the demo topology and its working principle under the proposed modulation method. Section 4 will analyze the voltage balance process and losses in detail. The comparative study will be included in Section 5. Section 6 gives the simulation under linear load change conditions. Experimental results of the proposed demo topology and modulation method will be shown in Section 7. Finally, Section 8 gives conclusions.

2. Generalized Topology Configuration and Hybrid Modulation Strategy

2.1. Generalized Topology Structure

It is worthwhile to mention that the hybrid modulation method is only applicable to specific SC topologies. Therefore, it is necessary to explain what kinds of SC topology is suitable for the modulation strategy. As is shown in Figure 2, the generalized topology should contain a high-voltage module (HVM) and a low-voltage module (LVM). The capacitor voltage in HVM is often very large so as to achieve high boosting gain. The capacitor voltage in an LVM is equal to the minimum step voltage of the output, and the blocking voltage of the switches are low. In Figure 2, v_OH and v_OL represent the output voltage of the HVM and LVM, respectively. The whole inverter is formed by connecting the circuits of the HVM and LVM in series, and the output voltage of the inverter v_o = v_OH + v_OL.

2.2. Proposed Hybrid Modulation Method

The novel hybrid modulation method is introduced in this part. The modulation combines HFM and FFM and uses different strategies to modulate different parts of the inverter. Phase disposition pulse-width modulation (PD-PWM) is employed in the low-voltage module while nearest level control (NLC) is used to modulate the high-voltage module. Figure 3 demonstrates the principle of the proposed hybrid modulation method. The reference signals of high-voltage module and low-voltage module are v_refh and v_refl, respectively. The mathematical expression of v_refh can be written as:

$$v_{refh}=AM\sin (\omega t)$$

(1)

where A is the maximum output level, M is the modulation index and ω is the angular frequency of the signal.

To acquire the reference signal of the low-voltage module v_refl, we first define a step wave signal v_stair whose expression can be represented as:

$$v_{stair}=\left\{\begin{array}{l}A\begin{array}{cc},& \begin{array}{cc}& \end{array}{v}_{refh}>A-0.5\end{array}\\ A-1,\begin{array}{cc}& A-1.5<v_{refh}<A-0.5\end{array}\\ \dots \\ 1,\begin{array}{cc}& \begin{array}{cc}& \end{array}0.5<v_{refh}<1.5\end{array}\\ 0,\begin{array}{cc}& \begin{array}{c}\end{array}\begin{array}{c}\begin{array}{c}\end{array}\end{array}\begin{array}{c}\end{array}-0.5<v_{refh}<0.5\end{array}\\ -1,\begin{array}{cc}& \end{array}\begin{array}{l}\hfill \end{array}-1.5<v_{refh}<-0.5\\ \dots \\ -A+1,\begin{array}{r}\hfill \end{array}\begin{array}{r}\hfill \end{array}-A+0.5<v_{refh}<-A+1.5\\ -A,\begin{array}{cc}& \begin{array}{cc}& v_{refh}<-A+0.5\end{array}\end{array}\end{array}\right.$$

(2)

The reference signal of the LVM is the difference between the reference signal of the HVM and the step wave signal, that is:

v_refl = v_refh − v_stair

(3)

By comparing v_refl with two triangular carrier signals (u_c and −u_c) with a peak-to-peak value of 0.5, the output signal of LVM v_OL can be determined. The amplitude of the v_OL is the minimum step voltage of the inverter. Finally, the entire inverter output v_o is equal to the sum of v_refh and v_refl. Its waveform is shown in Figure 3.

3. Demo Topology and Its Working Principle

3.1. Demo Topology

Figure 4 demonstrates a 17-level demo switched capacitor topology that conforms to the configuration mentioned in Section 2.1. In Figure 4a, switches S_x1, S_x2, T_a1, T_a2 and bi-directional switch S_a, DC power source V_dc as well as the capacitor C_a1 and C_a2 make up the low-voltage module. Other power devices make up the high-voltage module. The voltage of C_a1 and C_a2 are both rated at V_dc/2, the capacitor voltage of C_b1 and C_b2 are rated at V_dc and the capacitor voltage of C_c1 can be rated at 2 V_dc. The circuit in Figure 4a can be simplified into the topology in Figure 4b, which means the output voltage remains the same even if some power devices are removed. The equivalence principle will be introduced in detail in Section 3.2.

3.2. Modulation Method and Working Principle of Demo Topology

The switching states of the HVM and LVM in Figure 4a are listed in

Table 1. Switching state of high-voltage module.

Mode	vOH	States of Power Devices
		Tb1	Sb1	Sc1	Sc3	Sc4	Sy1	Cb1	Cb2	Cc1
4	4 Vdc	0	1	0	1	0	1	D	C	D
3+	3 Vdc	1	1	0	1	0	1	D	C	D
3−		0	0	0	1	0	1	C	D	D
2+	2 Vdc	1	0	0	1	0	1	C	D	D
2−		0	1	1	0	0	1	D	C	C
1+	Vdc	1	1	1	0	0	1	D	C	C
1−		0	0	1	0	0	1	C	-	C
0+	0	1	0	1	0	0	1	C	-	C
0−		0	1	1	0	0	0	-	C	C
(−1)+	−Vdc	1	1	1	0	0	0	-	C	C
(−1)−		0	0	1	0	0	0	C	D	C
(−2)+	−2 Vdc	1	0	1	0	0	0	C	D	C
(−2)−		0	1	0	0	1	0	D	C	D
(−3)+	−3 Vdc	1	1	0	0	1	0	D	C	D
(−3)−		0	0	0	0	1	0	C	D	D
−4	−4 Vdc	1	0	0	0	1	0	C	D	D

and

Table 2. Switching state of low-voltage module.

Mode	vOL	Switching State
		Sx1	Sx2	Sa	Ta1
1	+Vdc/2	0	0	1	1
0+	0	1	0	0	1
0−		0	1	0	0
−1	−Vdc/2	0	0	1	0

, respectively. As is mentioned above, we use the NLC method to modulate the high-voltage module and the PD-PWM method to modulate the LVM. Figure 5 illustrates the modulation principle and the switching signals of the demo topology. In the Figure, θ₁, θ₂, θ₃, …, θ₇ represents the switching angle between two adjacent modes in the HVM. Their values can be expressed as:

$${\theta }_i=\arcsin (\frac{i}{8M})\begin{array}{cc}& i=1,2,\mathrm{...7}\end{array}$$

(4)

The output voltage of the demo topology is a 17-level high-frequency step wave from −4 V_dc to 4 V_dc with a minimum step voltage of 0.5 V_dc. In Table 1 and Table 2, ‘0′ denotes the switch is turned off and ‘1′ means the switch is turned on. In the column of capacitors, ‘C’, ’D’ and ‘-’ mean charge, discharge and idle state, respectively. The signal of (T_a1, T_a2), (T_b1, T_b2), (S_b1, S_b2) and (S_y1, S_y2) are complementary, and the switching signals of S_c1 and S_c2 are the same.

As is shown in Table 1, the outputs of ±3 V_dc, ±2 V_dc, ±V_dc and 0 all correspond to two different modes, marked ‘+’ and ‘−’ on the top right corner of the number, respectively. When the output of the HVM is NV_dc (N = 0, ±1, ±2, ±3), if v_refh < N, then the HVM works in mode N⁻; if v_refh > N, then the HVM works in mode N⁺. Therefore, in certain output levels, it uses two modes in different time intervals.

According to Figure 5, the switching state of T_a1 and T_b1 are completely identical. Since T_a1 and T_a2 and T_b1 and T_b2 have complementary switching signals, T_a2 and T_b2 also have identical switching signals. As a result, when the circuit in Figure 4a operates, the voltage between the point a₁ and a₂ V_a1a2, as well as the point b₁ and b₂ V_b1b2, are zero. Therefore, the topology shown in Figure 4a can be simplified into Figure 4b without changing the waveform of the output voltage. The topology in Figure 4b is regarded as the demo topology.

It can be seen that in the HVM of the demo topology, the switching frequency of all power switches does not exceed seven times of the fundamental frequency, so the hybrid modulation reduces the switching loss significantly.

4. Voltage Analysis of Capacitors and Loss Calculation

4.1. Self-Balance Process of Capacitors

The voltage balance of capacitor in the HVM is achieved by imposing the rated voltage to the corresponding capacitors in various charging circuits. As is shown in Figure 6a, when S_b2 is turned on, D₁ conducts and the capacitor C_b1 can be charged through the voltage of power source V_dc. As is shown in Figure 6b, when S_b1 is turned on, D₂ conducts and the capacitor C_b2 can be charged to V_dc. As is shown in Figure 6c, when S_c1 and S_c2 are turned on, C_b1 and C_b2 are connected in series and their voltage is imposed to C_c1. Since the rated voltages of C_b1 and C_b2 are both V_dc, C_c1 can be charged to 2 V_dc through the charging circuit.

As for the capacitor in LVM, suppose that the voltages of C_a1 and C_a2 are V_ca1 and V_ca2, respectively. Then, it is easy to work out that:

V_ca1 + V_ca2 = V_dc

(5)

As is shown in Figure 7, the voltages of C_a1 and C_a2 are mainly influenced by neutral point current i_c, whose mathematical formula can be expressed as:

$$i_c=\left\{\begin{array}{l}{i}_o, S_a \begin{array}{cc}is & turned \begin{array}{c}on\end{array}\end{array}\\ 0, S_a \begin{array}{cc}is & turned \begin{array}{c}off\end{array}\end{array}\end{array}\right.$$

(6)

where i_o is the output current. Due to the symmetric conducting interval of S_a and the output current i_o, the average value of i_c is zero in one output period, that is:

$$I_c=\frac{1}{2\pi }{\displaystyle {\int }_0^{2\pi }{i}_{c}d(\omega t)}=0$$

(7)

Assuming i_ca1 and i_ca2 are currents flowing in the capacitor C_a1 and C_a2, respectively, then if C_a1 = C_a2, Formula (8) can be deduced according to the Kirchhoff’s Voltage Law:

$$\left\{\begin{array}{l}{i}_c+i_{ca1}=i_{ca2}\\ i_{ca1}=C_{a1}\frac{d{v}_{ca1}}{dt}\\ i_{ca2}=C_{a2}\frac{d{v}_{ca2}}{dt}\end{array}\right.$$

(8)

By solving Equation (8), we can receive i_ca1 = −0.5 i_c, i_ca2 = 0.5 i_c. This represents the average value of i_ca1 and i_ca2 are both zero, meaning that C_a1 and C_a2 can achieve self-voltage balance.

4.2. Capacitance Calculation

In switched-capacitor inverters, it is important to determine the capacitance in the inverter since the voltage ripple of the capacitor influences the quality of the output waveforms significantly [22]. To calculate the capacitance in the demo topology, we first estimate the voltage ripples of capacitors.

For the capacitor in high-voltage modules (C_b1, C_b2 and C_c1), the maximum voltage ripple is most likely to occur during the largest discharging gap for pumping the stored energy to the load side in a fundamental cycle [23]. From the analysis in Section 3.2, the maximum discharging intervals of C_b1 and C_b2 are [θ₆, π − θ₆] and [π + θ₆, 2π − θ₆], respectively. And the maximum discharging interval of C_c1 is [θ₄, π − θ₄]. Therefore, the voltage ripples of C_b1, C_b2 and C_c1 can be estimated using the following equation:

$$\left\{\begin{array}{l}\Delta V_{Cb1}=\frac{1}{C_{b1}}{\displaystyle {\int }_{{\theta }_6/\omega }^{(\pi -{\theta }_6)/\omega }{i}_{o}dt}\\ \Delta V_{Cb2}=\frac{1}{C_{b2}}{\displaystyle {\int }_{(\pi +{\theta }_6)/\omega }^{(2\pi -{\theta }_6)/\omega }{i}_{o}dt}\\ \Delta V_{Cc1}=\frac{1}{C_{c1}}{\displaystyle {\int }_{{\theta }_4/\omega }^{(\pi -{\theta }_4)/\omega }{i}_{o}dt}\end{array}\right.$$

(9)

where △V_Cb1, △V_Cb2 and △V_Cc1 are the maximum voltage ripples of C_b1, C_b2 and C_c1, respectively. Suppose that the expression of the output current is

$$i_o=\frac{4M{V}_{dc}}{Z_L}\sin (\omega t-\phi )$$

(10)

where M is the modulation index, Z_L is the load impedance and ψ is the phase difference of output voltage and current, then the expression in Equation (9) can be further simplified as:

$$\left\{\begin{array}{l}\Delta V_{Cb1}=\frac{4M{V}_{dc}}{Z_L{C}_{b1}}{\displaystyle {\int }_{{\theta }_6/\omega }^{(\pi -{\theta }_6)/\omega }\sin (\omega t-\phi )dt}\\ \Delta V_{Cb2}=\frac{4M{V}_{dc}}{Z_L{C}_{b2}}{\displaystyle {\int }_{(\pi +{\theta }_6)/\omega }^{(2\pi -{\theta }_6)/\omega }\sin (\omega t-\phi )dt}\\ \Delta V_{Cc1}=\frac{4M{V}_{dc}}{Z_L{C}_{c1}}{\displaystyle {\int }_{{\theta }_4/\omega }^{(\pi -{\theta }_4)/\omega }\sin (\omega t-\phi )dt}\end{array}\right.$$

(11)

As for C_a1 and C_a2, their voltage deviation is influenced by the neutral point current i_c. The maximum ripples of C_a1 and C_a2 occur at the zero-crossing time of i_o since this moment is the longest time that i_c flows in one direction. That is:

$$\left\{\begin{array}{l}\Delta V_{Ca1}=\frac{1}{C_{a1}}{\displaystyle {\int }_0^{\pi /\omega }\left|\left.i_{ca1}\right|\right.dt=\frac{1}{2C_{a1}}{\displaystyle {\int }_0^{\pi /\omega }\left|i_c\right|dt}}\\ \Delta V_{Ca2}=\frac{1}{C_{a2}}{\displaystyle {\int }_0^{\pi /\omega }\left|\left.i_{ca2}\right|\right.dt=\frac{1}{2C_{a2}}{\displaystyle {\int }_0^{\pi /\omega }\left|i_c\right|dt}}\end{array}\right.$$

(12)

From Equation (6), it can be seen that the integration of i_c in the positive half cycle is obviously smaller than that of i_o in the positive half cycle. Therefore, it can be deduced that:

$$\left\{\begin{array}{l}\Delta V_{Ca1}<\frac{1}{2C_{a1}}{\displaystyle {\int }_0^{\pi /\omega }\left|i_o\right|dt=\frac{2M{V}_{dc}}{Z_L{C}_{a1}}{\displaystyle {\int }_0^{\pi /\omega }\sin (\omega t)dt}}\\ \Delta V_{Ca2}<\frac{1}{2C_{a2}}{\displaystyle {\int }_0^{\pi /\omega }\left|i_o\right|dt=\frac{2M{V}_{dc}}{Z_L{C}_{a2}}{\displaystyle {\int }_0^{\pi /\omega }\sin (\omega t)dt}}\end{array}\right.$$

(13)

Therefore, the voltage ripples of C_b1, C_b2 and C_c1 can be calculated by using Equation (11) and the voltage ripples of C_a1 and C_a2 can be estimated using Formula (13). Generally, it is required that the voltage ripple should not exceed 10% of its rated voltage [24]. Therefore, based on Equations (11) and (13), the capacitance range can be estimated, which is shown in Equation (14).

$$\left\{\begin{array}{l}{C}_{a1},C_{a2}\ge \frac{80M}{\omega Z_L}\\ C_{b1},C_{b1}\ge \frac{80M}{\omega Z_L}\cos {\theta }_6\cos \phi \\ C_{c1}\ge \frac{40M}{\omega Z_L}\cos {\theta }_4\cos \phi \end{array}\right.$$

(14)

4.3. Switching Loss

The switching loss is an important part of the energy loss when the inverter operates. It is caused by the overlap between the drain current and the drain–source voltage during the turn-on or turn-off moment. The switching losses include turn-on loss and turn-off loss which can be calculated by Equation (15) [25]:

$$\left\{\begin{array}{l}{P}_{sw,on}=(V_b{I}_{on}\times \frac{t_{ri}+t_{fu}}{2}+Q_{rr}{V}_b)f_{sw}\\ P_{sw,off}=(V_b{I}_{off}\times \frac{t_{fi}+t_{ru}}{2})f_{sw}\end{array}\right.$$

(15)

where P_sw,on and P_sw,off represent turn-on losses and turn-on losses, respectively. V_b is the blocking voltage (drain-to-source voltage) of the switch at switching moment. t_ri and t_fu are the current rise and voltage fall time during the turn-on moment. t_fi and t_ru are the current fall time and voltage rise time during the turn-off moment. Q_rr represents the reverse-recovery charge which can be looked up in the datasheet of the power switch. I_on and I_off are the drain–current after turning on and before turning off, respectively. f_sw is the switching frequency.

Table 3. Switching frequency and blocking voltage of various switches.

Switch Label	Switching Frequency fsw	Blocking Voltage Vb
Sb1, Sb2	7 fo	Vdc
Sc1, Sc2	2 fo	2 Vdc
Sc3	fo	2 Vdc
Sc4	fo	2 Vdc
Sy1,Sy2	fo	2 Vdc
Sx1, Sx2	fc/2	Vdc/2
Sa	fc	Vdc/2

lists the switching frequency and blocking voltage of each power switch in the demo topology.

The total switching losses are the sum of the switching losses of all the power switches, so it can be calculated using Formula (16):

$$P_{sw-total}={\displaystyle \sum _{all\begin{array}{c}\begin{array}{c}\begin{array}{c}\end{array}the\begin{array}{c}\end{array}switches\end{array}\end{array}}{P}_{sw}}$$

(16)

From the datasheet of the power switch used in the experiment (see Section 7), we can understand that t_ri and t_ri are 43.6 ns, t_fi and t_fu are 43.2 ns and Q_rr of the power MOSFET is 7.58 μC. Supposed that V_dc = 24 V, the carrier frequency is 10 kHz, the load is 200 Ω and I_on and I_off are assumed as the root-mean-square value of the output current. Then, the switching losses of various power switches can be calculated, which are shown in Figure 8. Obviously, the switching losses of switches in the HVM are much lower than that in the LVM. This is because the power switches in the HVM have very low switching frequencies. From Figure 8, it can be seen that the total switching loss is estimated to be 2.0883 W.

4.4. Conduction Losses

The conduction losses are caused by the parasitic resistance of the power switches and the forward voltage of the diodes. The conduction loss generated by one power switch and diode can be estimated as follows:

$$\left\{\begin{array}{l}{P}_{con-SW}=R_{on}{I}_{on}^2\\ P_{con-D}=V_D{I}_{on}\end{array}\right.$$

(17)

where P_con–SW and P_con–D represent the conduction losses generated by the power switch and diode, respectively. R_on, V_D and I_on are the on-state resistance of power switch, forward voltage and current flowing through the semiconductor devices, respectively.

Figure 9 shows the conduction losses of various diodes and switches. The load current is still assumed to be Equation (10). The V_dc is still set to be 24 V and load is set as 200 Ω. The on-state resistance is set as 0.38 Ω and the forward voltage is regarded as 0.8 V. The output current is assumed to be the Equation (10). Therefore, the total conduction loss is estimated to be 0.6776 W.

4.5. Ripple Losses

The voltage ripple of the capacitors results in the ripple losses. It is associated with the maximum voltage difference between the rated voltage and the voltage of the capacitor right after the longest discharging period. The ripple loss of one capacitor can be calculated using the equation below [13]:

$$P_{rip}=\frac{1}{2}C{f}_o{(\Delta V)}^2$$

(18)

where P_rip is the ripple loss, f_o is output frequency and △V is the maximum voltage ripple.

Figure 10 shows the ripple loss of various capacitors in the demo topology. The V_dc is still 24 V, and the load is still 200 Ω. The maximum voltage ripple of various capacitors can be calculated using Equations (9) and (12). And the total ripple loss is estimated to be 0.1503 W.

The above three sections have analyzed the switching losses, conduction losses and ripple losses, respectively, which nearly includes all the losses in the proposed inverter. Therefore, the overall efficiency can be deduced based on the data above. The formula of the efficiency is shown in Equation (19):

$$\eta =\frac{P_{out}}{P_{out}+P_{rip,tot}+P_{con,tot}+P_{sw,tot}}\times 100\%$$

(19)

where P_out is the output power; and P_rip,tot, P_con,tot and P_sw,tot represent the total ripple losses, conduction losses and switching losses, respectively. The theoretical efficiency is calculated to be 88.76% under the 24 Vdc, 200 Ω resistive load.

5. Comparative Study

To highlight the merits of the proposed demo topology and modulation strategy, a comparative study is conducted in this part.

5.1. Quantitative Comparison

To assess the scale, voltage stress as well as the cost of the demo topology and other similar inverters, a quantitative comparison is demonstrated in

Table 4. Comparison results with other similar inverters.

Topology	Nsource	Nsw	Ng	Nd	Nc	TSV(×Vstep)	Nlevel	CF	Self-Balance
CHB	8	32	32	0	0	32	17	45.17	-
[9]	1	12	12	14	7	95	17	8.24	√
[12]	1	8	7	4	3	16	7	5.43	√
[13]	1	8	8	2	3	20	9	4.56	√
[14]	1	8	8	1	2	22	9	4.56	√
[17]	1	10	10	4	4	36	13	4.92	√
[19]	1	10	9	2	4	42	17	3.94	×
[20]	2	10	8	0	2	36	17	6.59	√
[21]	1	12	12	2	3	50	17	4.65	√
Proposed demo topology	1	12	10	4	5	45	17	4.47	√

N_source—Number of switches; N_SW—Number of switches; N_g—Number of gate drivers; N_d—Number of diodes; Nc—Number of capacitors; TSV—Total standing voltage; N_level—Number of output levels; CF—Cost Function; “√”—The inverter can achieve self-balance; “×”—The inverter cannot achieve self-balance;”-”—The inverter does not have capacitors.

. In the Table, N_source, N_sw, N_g, N_d, N_c, N_level and TSV represent the number of DC sources, power switches, gate drivers, diodes, capacitors, output levels and total standing voltage, respectively. To make the comparison fair, the unit chosen for the TSV is the minimum step voltage of the inverter. To evaluate the cost of the inverters, the cost function (CF) used in [17] is employed. The CF value can be calculated using Formula (20):

$$CF=\frac{N_{source}(N_{sw}+N_g+N_d+N_c+TSV)}{N_{level}}$$

(20)

From Table 4, it can be observed that the traditional CHB inverter needs eight DC sources to generate 17 levels, so it has strict requirements on the number of input sources. The inverter proposed in [9] uses a backend H-bridge to control the polarity of the output, which increases the voltage stress greatly.

As for the CF value, it can be seen that the only the topology proposed in [19] is lower than the demo topology. However, the inverter in [19] cannot achieve self-balance and needs extra circuits to regulate the output. Therefore, the demo topology has better quality than its counterpart in general terms.

5.2. Switching Loss Comparison

One of the most prominent advantages of the proposed inverter is that it has reduced switching loss when operating in HFM. To highlight this merit, the switching loss comparison of different inverters working in HFM is presented in this module. In order to make the comparison fair, the amplitude of the output voltage is uniformly set as 96 V and the load is uniformly assumed to be 200 Ω. Formula (15) is selected to be the calculation equation and the rise time, fall time as well as Q_rr are set to be the same as that in Section 4.3.

Figure 11 demonstrates the calculated switching loss of the proposed and other similar inverters when the carrier frequency changes from 1 kHz to 10 kHz. It can be seen that the slope of the proposed inverter is much lower than that of other inverters, which means the carrier frequency has the least influence on the switching loss of the proposed inverter. Moreover, the proposed inverter has the lowest switching loss almost during the whole range. Therefore, the advantage of low switching loss has been verified.

6. Simulation Results

To verify the feasibility of the proposed modulation and topology, a simulation model is set up in PSIM. The simulation parameters are listed in

Table 5. Simulation parameters.

Items	Specification
Input source voltage Vdc	50 V
Capacitance	3300 μF
Working/output frequency fo	50 Hz
Carrier signal frequency fc	5 kHz
Load resistance	50–200 Ω
Load inductor	46 mH

.

Figure 12a demonstrates the waveform of output voltage and current (amplified 40 times) under RL-load. The inductor is set as 46 mH. The resistance firstly increases from 50 Ω to 200 Ω, then it keeps constant and finally decreases linearly from 200 Ω to 50 Ω. It can be observed from the Figure that the output voltage is a 17-level staircase AC waveform with the amplitude of 200 V. The output current is a near-sinusoidal waveform. When the load increases, the amplitude of output current decreases gradually and reaches the lowest value at 0.98 A. After that, the load resistance reduces, and the output current rises correspondingly.

Figure 12b shows the voltage of capacitors in the demo topology. It can be seen that the voltages of C_a1 and C_a2 are maintained around 25 V, the voltages of C_b1 and C_b2 are balanced at 50 V and the voltage of C_c1 is balanced at 100 V. Therefore, under the proposed modulation, the capacitor voltages in the demo topology are self-balanced. Moreover, it can be observed that the voltage ripple increases when the load impedance reduces. The voltage ripples of C_b1, C_b2 and C_c1 reach the maximum value when the resistance becomes 50 Ω. However, the voltage ripples of all the capacitors do not exceed 10% of their rated voltage, which means the selection of capacitor parameters all satisfy the 10% ripple requirement.

7. Experimental Results

In order to verify the feasibility of the proposed inverter and modulation method, an experiment was conducted. TMS320F28335 was chosen to be the DSP generating the switching signal. Then, the signal was sent to the dead-time circuit board to avoid a short circuit. Next, TLP250 was employed to drive the gate of the switches. All the experimental waveforms were captured by an oscilloscope whose model number is ZDS3024. The parameters of the experiment are listed in

Table 6. Experimental parameters.

Components	Specification
Input source voltage Vdc	24 V
Capacitance	3300 μF
Power switches	SMF20N65
Diodes	MURF1040CT
Working/output frequency fo	50 Hz
Carrier signal frequency fc	10 kHz
Loads	200 Ω/80 Ω/46 mH

.

7.1. Switching Signal Tests

Figure 13 demonstrates the waveforms of the switching signals of each power switch under two different modulation methods: one is the hybrid method proposed in this paper (pink waveforms) and the other is the traditional phase disposition modulation method (PD-PWM) which is widely used in other papers [12,13,14,15,16] (blue waveforms). The two different modulations lead to different switching signals and, certainly, switching frequency.

As for S_x1, S_x2, S_a, S_y1 and S_y2, the switching frequencies using these two modulations are the same, which means the switching action times during one cycle is the same. However, for S_b1, S_b2, S_c1, S_c2, S_c3 and S_c4, as is shown in Figure 13, the switching frequency using hybrid modulation is much lower: it can be seen that the switching frequencies of S_b1 and S_b2 are 350 Hz during one cycle while the results under PD-PWM turn out to be 3450 Hz; the switching frequencies of S_c3 and S_c4 are only a fundamental frequency (50 Hz) under hybrid modulation while the figure for PD-PWM is 1 kHz. It is obvious in Figure 13 that the switching action time under PD-PWM is much higher than that under hybrid modulation. Therefore, compared to the traditional HFM method, the proposed hybrid method reduces the unwanted switching frequency and loss significantly.

7.2. Static Response Tests

Figure 14 demonstrates the experimental waveforms of output voltage and current when the inverter works under a 200 Ω pure resistive load. The modulation index M is set as 0.98. It can be seen that the output voltage is a 17-level staircase-like waveform, which is consistent with the theoretical waveform. The peak value of the output voltage is 90.2 V, which is close to the theoretical value (96 V).

Figure 15 illustrates the capacitor voltage as well as the voltage ripple. As is shown in the Figure, the voltages of C_a1 and C_a2 are steady at 12 V with a voltage ripple of 360 mV. V_cb1 and V_cb2 are stable at 24 V. Their voltage ripple is measured to be 960 mV. The average value of V_Cc3 is 45 V, which is a bit lower than its desired value (48 V) because of the forward voltage of diodes and parasitic resistance in the power switch. From Figure 15, it can be observed that all the capacitor voltages are self-balanced and their voltage ripples are all within 10% of their rated voltage.

Figure 16 presents the output voltage and current under 200 Ω + 46 mH inductive load. The modulation index is set to be 0.98 in Figure 16a and 0.45 in Figure 16b. As is shown in the Figure, when the modulation index reduces from 0.98 to 0.45, the number of the output level decreases from seventeen to nine, and the amplitude of i_o reduces correspondingly. The current THD in Figure 16a,b is 2.09% and 2.6%, respectively.

7.3. Dynamic Response Test

A load change experiment was carried out to examine the transient response of demo topology and modulation method. Figure 17 illustrates the output waveforms under the condition of a sudden load change from 80 Ω + 46 mH to 280 Ω + 46 mH. The output voltage remains unchanged while the output current reduces greatly because the load impedance increases. The results in Figure 17 show the proposed demo topology and modulation method have good dynamic responses.

8. Conclusions

This paper presents a novel hybrid modulation method and a corresponding generalized switched capacitor topology configuration which can be modulated by the proposed modulation. The method is aimed at reducing switching frequency and switching loss in SC inverters. Then, a 17-level demo topology is exemplified to demonstrate how the switching frequency and loss is reduced using the proposed hybrid modulation method. Comparison results indicate that the proposed inverter not only has a lower switching loss, but also maintains most of the advantages of current SC inverters such as a single DC source, self-voltage balance and low cost. The experimental results have verified that the voltage ripples of the capacitors are all within 10% of their rated voltage. The comparison waveform in Figure 13 shows the advantage of reduced switching frequency of the proposed modulation compared to traditional modulation. The simulation and experimental waveforms all show the excellent steady and transient responses of the proposed inverter.