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Article

Fixed-Time Backstepping Sliding-Mode Control for Interleaved Boost Converter in DC Microgrids

1
College of Electrical Engineering & New Energy, China Three Gorges University, Yichang 443002, China
2
School of Electrical and Control Engineering, Henan University of Urban Construction, Pingdingshan 467036, China
*
Authors to whom correspondence should be addressed.
Energies 2024, 17(21), 5377; https://doi.org/10.3390/en17215377
Submission received: 7 October 2024 / Revised: 24 October 2024 / Accepted: 28 October 2024 / Published: 29 October 2024

Abstract

:
Interleaved boost converters (IBCs) are commonly used as interface converters for DC microgrids (MGs) due to their high efficiency and low output ripple. However, the MGs system can easily become unstable due to the negative impedance characteristics of constant power load (CPL) and rapid power fluctuations. This paper proposes a fixed-time backstepping sliding-mode controller (FTBSMC) aimed at stabilizing the MGs system and achieving fixed-time tracking of the DC bus voltage. Firstly, the fixed-time disturbance observer (FxTDO) estimates the load disturbance at a fixed time, which improves the fast disturbance resistance of the system. Then, based on the dis-turbance estimation, the FTBSMC is designed, which combines the fast dynamic response of the sliding-mode control with the global stability of the backstepping control, avoiding the singularity problem of the conventional sliding-mode control. In addition, a first-order nonlinear filter is employed to avoid the direct differentiation of conventional backstepping control and at the same time to ensure global fixed-time stability. The fixed-time convergence of the proposed FTBSMC is rigorously demonstrated by using Lyapunov stability analysis. Finally, the FTBSMC proposed is verified by simulation and experiment in terms of faster dynamic response and stronger robustness.

1. Introduction

Recently, there has been a notable increase in the penetration of distributed energy resources (DERs), including renewable energy sources (RESs) and energy storage systems (ESSs) in DC microgrids (MGs), in parallel with an increase in primary energy consumption and the continuous development of new energy technologies. MGs are widely utilized due to their capacity to effectively integrate DERs and a range of load types [1].
Due to the low and easily fluctuating output voltages of RESs and ESSs in DERs, conventional boost converters (CBC) are often used as interface converters between DERs and microgrid DC buses for boosting and regulating DC bus voltages. However, the CBC has limited conversion efficiency and large output ripple, which makes it difficult to meet the transmission requirements under modern control technology [2]. The interleaved parallel technique can effectively enhance the output power of the converter, increase the current output, reduce switching tube current stress, and effectively reduce the output ripple through the staggered phase-shifted conduction of the switching tubes [3]. Therefore, interleaved boost converter (IBC) as an alternative to the CBC has a broad prospect in the application of MGs.
IBC, as an interface converter between DERs and a microgrid DC bus, faces the challenge of DC bus voltage stabilization. The power electronic load with strict closed-loop control is regarded as constant power load (CPL) and exhibits negative impedance characteristics [4]. Consequently, MGs utilizing IBCs may experience unstable DC bus voltages, which in turn makes the MGs system unstable. To address this situation, a control strategy for the IBC system needs to be developed to mitigate the impact of CPL and stabilize the DC bus voltage.
At present, a number of techniques have been put forth as potential solutions to the issue of DC bus voltage instability in MGs caused by CPL. Linear control methods, such as the passive damping method, increase system damping to counter the effect of CPL on the MGs by adding passive components [5]. This approach is more straightforward, but the extra components increase system losses. The active damping method stabilizes the MGs by adjusting the control loop to increase the virtual impedance [6], but modifying the loop can affect the dynamic response of the system. However, both methods rely on a linearized small-signal model, which only ensures asymptotic stability within a limited range around the steady-state operating point, highlighting their inherent limitations.
In order to address the limitations of linear control, scholars have proposed many nonlinear control strategies. In reference [7], the exact feedback linearization (EFL) technique is used to turn the nonlinear boost system into a linear one, effectively addressing the nonlinear issues caused by CPL. This method does not eliminate the nonlinear high-order terms of the system, which is a major advantage. Nevertheless, inaccuracies in the system’s mathematical model can reduce the control’s effectiveness [8]. The design of robust controllers can effectively deal with model uncertainty, and sliding-mode control (SMC) is attracting considerable attention due to its resilience to unmodeled dynamics and external disturbances. In reference [9], a fixed-frequency SMC is proposed for a buck converter feeding CPL. However, this approach requires measuring the output-side capacitor current, which can raise costs. In addition, the conventional SMC suffers from the singularity problem, while the backstepping control can effectively avoid this problem and achieve global stability and good transition quality for the system. In the reference [10], EFL is combined with backstepping sliding-mode control for a bi-directional converter. This combination ensures system robustness and stability under nonlinear conditions and external disturbances, but it has not been verified under CPL disturbance. Indeed, the majority of conventional robust controllers are unable to effectively mitigate disturbances in an active manner. In the face of large signal disturbances, robustness of these feedback controllers is limited [11]. To solve this problem, the use of nonlinear disturbance observer (NDO) as a compensation technique becomes an effective choice [12]. In references [13,14,15,16], the combination of NDO with back-step control and SMC for load power estimation and fast tracking of the output voltage of the converter was investigated, but the NDO only asymptotically estimates the disturbance.
The nonlinear control strategies discussed in the above reference effectively improve the stability of the MGs system, but they can only achieve asymptotic stability for infinite time. CPL in MGs often undergoes rapid high amplitude load power changes, which can lead to large signal changes at the operating point of the MGs [17]. Therefore, the control strategy with fast convergence speed and flexible control of convergence time is more suitable for MGs systems. At present, finite-time control methods are proposed to be applied to the converter feedback control in MGs. In reference [18], a composite finite-time controller, based on a comprehensive large signal stability analysis, is proposed to ensure finite-time stability under significant signal disturbances. Nonetheless, its convergence time is subject to the initial operating conditions. In reference [19], a fixed-time terminal sliding-mode controller is developed with a goal to stabilize the ship’s power system and to track the main DC bus voltage within a fixed time frame. However, the observer can estimate the instantaneous power of the CPL only in a finite time. To accelerate the system convergence even further, in reference [20], a control strategy is proposed, which employs a fixed-time sliding-mode observer in combination with fast fixed-time backstepping control. This strategy can track the DC bus voltage reference within a fixed time frame, with the upper limit of convergence time dictated solely by the design parameters. However, the controller design includes partial differential terms, which may complicate its implementation. And these studies of flexible control of convergence speed have focused on CBC, and research in IBC is still limited.
Drawing from the analysis presented, this paper introduces a fixed-time backstepping sliding-mode control (FTBSMC) strategy. The strategy is designed to tackle the instability issues in MGs systems that use IBC as the interface converter when feeding CPL. The fixed-time disturbance observer (FxTDO) accurately estimates load power variations within a fixed time. This improves the system’s resilience against external disturbances. The FTBSMC is designed based on disturbance estimation. It combines the robustness and fast response of SMC with the global signal stabilization and step-by-step design features of backstepping control, which effectively suppresses the singularity problem of SMC. In this approach, the direct differentiation of the virtual control law inherent in conventional backstepping controllers is circumvented by incorporating a first-order nonlinear filter in the controller design, and fixed-time convergence is guaranteed. Additionally, a simple current-sharing compensator ensures equalization of the inductor currents across each phase. The rigorous Lyapunov stability analysis substantiates the fixed-time convergence of the FTBSMC, and the estimated convergence time is provided. Finally, both simulation and experimental results validate that the FTBSMC proposed offers substantial improvements in dynamic response and robustness, making it a promising solution for enhancing the stability of microgrid systems.

2. Dynamical Modeling

Dynamical Modeling of IBC Feeding CPL in DC Microgrid

Figure 1 illustrates a typical DC microgrid (MG) system fed by an IBC. The IBC serves as an interface converter between the distributed energy resources (DERs) and the microgrid DC bus. It helps deliver power to the main DC bus. Many loads using power electronic converters are linked to the main DC bus. These loads are tightly controlled. If the control bandwidth of the loads is large enough, they can be treated as constant power load (CPL). The CPL equals a controlled current source as shown in (1).
i C P L = P C P L v o
where i C P L and v o are the instantaneous current and voltage values of the CPL, respectively. From (1), the presence of the voltage state in the denominator introduces nonlinearity into the system, which affects the overall stability in the MGs.
Figure 1 is simplified to Figure 2 by equating the DERs to a DC source, the CPL set to P C P L , and the resistive load equivalent resistance to R s .
Figure 2 shows the topology of a Simplified three-phase IBC-interfaced MGs, where V i n and v o are the input and output voltages of the IBC, C f is the capacitance at the output, i L i is the inductor current of inductor L i , i i n = i = 1 3 i L i is the total input current, and the load current is i o = v o / R s + P C P L / v o . Assuming that the IBC operates in continuous conduction mode (CCM), the averaged model of the IBC is expressed as follows
L i d i L i d t = V i n ( 1 d i ) v o C f d v o d t = i = 1 3 i L i ( 1 d i ) i o
where d i is the duty ratio of the ith phase.
IBC has the same input voltage V i n and output voltage v o ; at the same time, due to the addition of the current-sharing compensator in this paper, each phase of the switching tubes has the same duty cycle, with both being d = d 1 = d 2 = d 3 . Then it is assumed that each phase of the inductor current is the same, with both being i L 1 = i L 2 = i L 3 . Based on this, the generalized reduced-order averaging model is [17].
L e q d i i n d t = V i n ( 1 d ) v o C f d v o d t = i i n 1 d v o R + P C P L v o
where L e q = L i / 3 denotes the equivalent input inductance.

3. Controller Design

3.1. Preparatory Knowledge

Prior to the design of the controller, a series of preliminary lemmas are presented.
Lemma 1.
For a nonlinear system  x ˙ ( t ) = f ( x ( t ) ) ,  x ( 0 ) = x 0  . If there exists a Lyapunov function  V x  that meets the following [21],
V ˙ ( x ) ζ 1 V ( x ) r 1 ζ 2 V ( x ) r 2 + Θ
where  ζ 1 > 0 , ζ 2 > 0 , 0 < r 1 < 1 , r 2 > 1  and  Θ  is a positive constant,  Θ > 0  . Then the system will converge to a small field at the origin. The upper bound of the convergence time is
T 1 ζ 1 ( 2 r 1 1 ) 1 1 r 1 + 1 ζ 2 ( r 2 1 )
Lemma 2.
For non-negative real numbers  η i  , the following inequality holds constant, [22,23]:
( i = 1 n η i ) ρ i = 1 n η i ρ , 0 < ρ 1 n 1 ρ ( i = 1 n η i ) ρ i = 1 n η i ρ , ρ > 1

3.2. Coordinate Transformation

For ease of controller design, this paper constructs Brunovsky’s standard type equations [7], using the feedback linearization (EFL) technique, the new variables are set as the storage energy and the power input of IBC through the coordinate transformation for indirect control, as illustrated by the following equation:
y 1 = 1 2 L e q i i n 2 + 1 2 C f v o 2 y 2 = V i n i i n v o 2 R o
where y 1 denotes the energy stored by the IBC, y 2 denotes the total input power, and R o refers to the rated resistance of the resistive load.
Derivation of the new state quantities yields
y ˙ 1 = L e q i ˙ i n i i n + C f v ˙ o v o y ˙ 2 = V i n i ˙ i n 2 v ˙ o v o R o
Constructing the Brunovsky standard form,
y ˙ 1 = y 2 + f 1 y ˙ 2 = u + f 2
Joining (3) and (9) yields
f 1 = P P C L v o 2 R s + v o 2 R o u = V i n 2 L e q + 2 v o 2 R s 2 C f 1 d V i n v o L e q + 2 v o i i n R s C f f 2 = 2 C f R o P P C L + v o 2 R s v o 2 R o
where f 1 is the mismatch disturbance, f 2 is the matching disturbance, and u is the intermediate control law.
After the coordinate transformation, in order to make the initial control objective DC bus voltage v o track to the reference value V r e f , the transformation ensures that the new state variable y 1 follows its reference value y 1 d , then the reference value of the new state variable y 1 d is
y 1 d = 1 2 L e q i L r e f 2 + C f V r e f 2 = 1 2 L e q P L o a d V i n 2 + 1 2 C f V r e f 2 = 1 2 L e q V i n 2 V r e f 2 R o f 1 2 + 1 2 C f V r e f 2
where P L o a d = P C P L + V r e f 2 R s represents the total power of the load, encompassing both the resistive load and the CPL power P C P L .
According to the intermediate control law u in (10), the actual control law d is given by
d = 1 V i n 2 L e q + 2 v o 2 R s 2 C f u / V i n v o L e q + 2 v o i L R s C f

3.3. Fixed-Time Disturbance Observer

From (10), it can be seen that there is a strong correlation between the magnitude of the disturbance terms f 1 and f 2 and the variation of CPL and the disturbance of the resistive load parameters. In practice, it can be posited that the range of variation of the resistive load parameters is constrained and that the load power remains constant at a steady state. So it can be assumed that the disturbance terms f 1 , f 2 and their differential should be bounded.
Assumption 1.
The disturbance item  f 1 ,  f 2 , and their differentials of the system are bounded and satisfied:
sup t > 0 f j ( t ) f j j = 1 , 2 sup t > 0 f ˙ j ( t ) ω j j = 1 , 2
where  f j  ,  ω j  are two constant positive values, and  sup ·  represents the supremum function.
From (10), it is apparent that disturbances f 1 and f 2 affect the converter performance, while their uncertainty affects the controller design. To enable the controller to compensate quickly, it is necessary to estimate the disturbance terms f 1 and f 2 within a fixed time frame. Therefore a fixed-time disturbance observer (FxTDO) is constructed in this paper as in (14) [24,25]:
ξ ˙ 1 = γ 1 sig ξ 1 y 1 m + sig ξ 1 y 1 n + ξ 2 + y 2 ξ ˙ 2 = γ 2 sig ξ 1 y 1 2 m 1 + sig ξ 1 y 1 2 n 1
where γ 1 > 0 , γ 2 > 0 , ξ 2 = f ^ 1 , f ^ 1 is the estimated value of the disturbance f 1 , m 0.5 , 1 , n 1 , 1.5 , sig ( · ) λ = sign · · λ , observer gains γ 1 and γ 2 are assigned the matrix A 1 , and A 2 are Hurwitz.
A 1 = γ 1 1 γ 2 0 , A 2 = γ 1 1 γ 2 0
Theorem 1.
Under Assumption 1,  f 1  can be estimated by the FxTDO at a fixed time. There is an upper bound on the estimation time:
T 1 λ max p P r 1 p + 1 r 2 σ ϖ σ
where  p = 1 m ,  σ = n 1 ,  r 1 = λ min Q 1 / λ max ( P 1 ) ,  r 2 = λ min Q 2 / λ max ( P 2 ) ,  ϖ λ min ( Q 2 )  is a positive number, and  Q 1 ,  Q 2 ,  P 1 ,  P 2  are symmetric positive definite matrices satisfying  P 1 A 1 + A 1 Τ P 1 = Q 1 , P 2 A 2 + A 2 Τ P 2 = Q 2 .
Proof of Theorem 1.
Define the FxTDO estimate errors as
ξ ˜ 1 = ξ 1 y 1 ξ ˜ 2 = ξ 2 f 1
Derivation of Equation (17):
ξ ˜ ˙ 1 = γ 1 sig ξ ˜ 1 m + sig ξ ˜ 1 n + ξ ˜ 2 ξ ˜ ˙ 2 = γ 2 sig ξ ˜ 1 2 m 1 + sig ξ ˜ 1 2 n 1 f ˙ 1
The remainder of the proof procedure is the same as Theorem 2 in reference [25]. It can be shown that the FxTDO estimate errors ξ ˜ 1 and ξ ˜ 2 converge to a small neighborhood of the origin at a fixed time T 1 . □
Remark 1.
From inequality (16), it can be obtained that the convergence time limit  T 1  of the FxTDO is determined by the parameters  γ 1  ,  γ 2  ,  m  , and  n  and does not depend on the initial state. Larger  γ 1  ,  γ 2  , and  n  , and smaller  m  lead to faster convergence of the FxTDO, but also to overshooting, so the parameters of the FxTDO are chosen in a compromise.
The estimated value f ^ 2 of the matching disturbance f 2 is obtained from (7) as
f ^ 2 = 2 C f R o f ^ 1
Associating (11) and the FxTDO observation ξ 2 = f ^ 1 , yields the reference value y 1 d as
y 1 d = 1 2 L e q V i n 2 V r e f 2 R o f ^ 1 2 + 1 2 C f V r e f 2

3.4. Fixed-Time Backstepping Sliding-Mode Controller Design

According to (9), and ξ 2 = f ^ 1 for the observed values of the FxTDO, the fixed-time backstepping sliding-mode controller (FTBSMC) is constructed to obtain the intermediate control law u .
Step 1. Define the first tracking error e 1 = y 1 y 1 d , and derive
e ˙ 1 = y ˙ 1 y ˙ 1 d = y 2 + f ^ 1 y ˙ 1 d
The virtual control law y 2 c has the following structure:
y 2 c = α 1 sig e 1 q 1 + β 1 sig e 1 q 2 + y ˙ 1 d f ^ 1
where α 1 and β 1 are positive constants, 0 < q 1 < 1 , q 2 > 1 .
In order to avoid direct differentiation of the virtual control law y 2 c , the following first-order nonlinear filter is designed
τ y ˙ 2 d = sig y 2 c y 2 d q 1 + sig y 2 c y 2 d q 2
where τ > 0 , and τ represents a small positive number. After filtering, y 2 d is the new virtual control law.
Remark 2.
τ  should be designed to be sufficiently small, allowing  y 2 d  to converge quickly to  y 2 c . However, too small a  τ  can amplify unmodeled dynamics and noise. Therefore, the choice of  τ  should be compromised.
Define the filtering error ε = y 2 d y 2 c and the second tracking error e 2 = y 2 y 2 d . The dynamics of the first tracking error e 1 can be expressed as
e ˙ 1 = e 2 + ε α 1 sig e 1 q 1 + β 1 sig e 1 q 2
Step 2. Design the sliding-mode surface as below:
s = e 2 + 0 t α 2 sig ( e 2 ) q 1 + β 2 sig ( e 2 ) q 2 d τ
where α 2 and β 2 are positive constants. When the system state converges to a neighborhood of the sliding mode surface s ˙ = 0 , the dynamics of the second tracking error e 2 can be expressed as
e ˙ 2 = α 2 sig ( e 2 ) q 1 β 2 sig ( e 2 ) q 2
According to (9) and (26), the intermediate equivalent control law u e q is given by
u e q = y ˙ 2 d f ^ 2 α 2 sig ( e 2 ) q 1 + β 2 sig ( e 2 ) q 2
Design the sliding-mode approach law as s ˙ = α 3 sig ( s ) q 1 β 3 sig ( s ) q 2 , where α 3 and β 3 are positive constants. Then the arrival switching law u s w of the controller can be designed as
u s w = α 3 sig ( s ) q 1 + β 3 sig ( s ) q 2
According to (27) and (28), the total intermediate control law u is given by
u = u e q + u s w = y ˙ 2 d f ^ 2 α 2 sig ( e 2 ) q 1 + β 2 sig ( e 2 ) q 2 α 3 sig ( s ) q 1 + β 3 sig ( s ) q 2
The actual control law d can then be obtained from (12) and (29).

3.5. Stability Analysis

By the definition filtering error of ε , the derived form of ε can be expressed as
ε ˙ = y ˙ 2 d y ˙ 2 c = 1 τ sig ε q 1 1 τ sig ε q 2 y ˙ 2 c
The following assumption can be made here that y ˙ 2 c is bounded and satisfies y ˙ 2 c ϑ , ϑ is a positive constant, and ϑ > 0 .
Remark 3.
The boundedness of  y ˙ 2 c  in (30) needs to be guaranteed. The expression for  y 2 c  from (22) contains the sign function. Derivation of  α 1 sig e 1 q 1  results in a term of  α 1 e 1 q 1 1 e ˙ 1  . Since  q 1 1 < 0  , when  e 1 = 0  and  e ˙ 1 0  , the term  α 1 e 1 q 1 1 e ˙ 1  , and the boundedness of  y ˙ 2 c  is no longer satisfied. However, since  e ˙ 1 0  ,  e 1  will not remain at  e 1 = 0  . Once  α 1 e 1 q 1 1 e ˙ 1  is away from point  e ˙ 1 0  ,  e 1 = 0  , and then by Assumption 1,  f ˙ 1  is bounded (20), and the boundedness of  y ˙ 2 c  is guaranteed.
Theorem 2.
For system (6), if the controller is designed as (29), the system state quantities will converge in a fixed time. The upper limit of convergence time is  T 2 .
T 2 1 λ 1 2 q 1 + 1 2 1 1 q 1 + 1 2 + 1 4 1 q 2 2 λ 2 q 2 + 1 2 1
where  λ 1 = min α 1 2 q 1 + 1 2 1 ,   α 2 2 q 1 + 1 2 ,   2 q 1 + 1 2 τ 2 ,   α 3 2 q 1 + 1 2 1 λ 2 = min β 1 2 q 2 + 1 2 1 ,   β 2 2 q 2 + 1 2 ,   2 q 2 + 1 2 τ 2 ,   β 3 2 q 2 + 1 2 1 .
Proof of Theorem 2.
Construct the Lyapunov function V 1 containing the tracking error e 1 , e 2 , the filtering error ε , the sliding mode surface s , and the observer errors ξ ˜ 2 .
V 1 = 1 2 e 1 2 + 1 2 e 2 2 + 1 2 ε 2 + 1 2 s 2 + 1 2 ξ ˜ 2 2
Derivation of (32) with respect to time yields
V ˙ 1 = e 1 e ˙ 1 + e 2 e ˙ 2 + ε ε ˙ + s s ˙ + ξ ˜ 2 ξ ˜ ˙ 2
From Theorem 1, the disturbance estimate error ξ ˜ 2 will converge to the origin at time t > T 1 . Therefore, at time t > T 1 , ξ ˜ 2 = 0 , and (33) reduces to
V ˙ 1 = e 1 e ˙ 1 + e 2 e ˙ 2 + ε ε ˙ + s s ˙ = e 1 e 2 + ε α 1 sig e 1 q 1 β 1 sig e 1 q 2 + e 2 α 2 sig ( e 2 ) q 1 β 2 sig ( e 2 ) q 2 + ε 1 τ sig ε q 1 1 τ sig ε q 2 y ˙ 2 c + s α 3 sig ( s ) q 1 β 3 sig ( s ) q 2
According to sig e q = sign e e q , e sign e = e , and y ˙ 2 c ϑ , we get
V ˙ 1 α 1 e 1 q 1 + 1 β 1 e 1 q 2 + 1 α 2 e 2 q 1 + 1 β 2 e 2 q 2 + 1 1 τ ε q 1 + 1 1 τ ε q 2 + 1 α 3 s q 1 + 1 β 3 s q 2 + 1 + e 1 e 2 + e 1 ε + ε ϑ
According to the inequality M N M χ / χ + N κ / κ where M and N are non-negative, χ > 1 , 1 / χ + 1 / κ = 1 . The following inequality can be obtained:
e 1 e 2 + e 1 ε + ε ϑ 2 e 1 2 2 + e 2 2 2 + 2 ε 2 2 + ϑ 2 2 2 e 1 2 2 q 1 + 1 2 + 2 e 1 2 2 q 2 + 1 2 + e 2 2 2 q 1 + 1 2 + e 2 2 2 q 2 + 1 2 + 2 ε 2 2 q 1 + 1 2 + 2 ε 2 2 q 2 + 1 2
Based on the inequalities h h m + h n where h 0 , 0 < m < 1 , n > 1 , 0 < q 1 < 1 , and q 2 > 1 , then (35) can be rewritten as
V ˙ 1 α 1 2 q 1 + 1 2 e 1 2 2 q 1 + 1 2 β 1 2 q 2 + 1 2 e 1 2 2 q 2 + 1 2 α 2 2 q 1 + 1 2 e 2 2 2 q 1 + 1 2 β 2 2 q 2 + 1 2 e 2 2 2 q 2 + 1 2 2 q 1 + 1 2 τ ε 2 2 q 1 + 1 2 2 q 2 + 1 2 τ ε 2 2 q 2 + 1 2 α 3 2 q 1 + 1 2 s 2 2 q 1 + 1 2 β 3 2 q 2 + 1 2 s 2 2 q 2 + 1 2 + 2 e 1 2 2 q 1 + 1 2 + 2 e 1 2 2 q 2 + 1 2 + e 2 2 2 q 1 + 1 2 + e 2 2 2 q 2 + 1 2 + 2 ε 2 2 q 1 + 1 2 + 2 ε 2 2 q 2 + 1 2 + ϑ 2 2
Upon merging similar items, (37) can be written as
V ˙ 1 α 1 2 q 1 + 1 2 2 e 1 2 2 q 1 + 1 2 α 2 2 q 1 + 1 2 1 e 2 2 2 q 1 + 1 2 2 q 1 + 1 2 τ 2 ε 2 2 q 1 + 1 2 α 3 2 q 1 + 1 2 s 2 2 q 1 + 1 2 β 1 2 q 2 + 1 2 2 e 1 2 2 q 2 + 1 2 β 2 2 q 2 + 1 2 1 e 2 2 2 q 2 + 1 2 2 q 2 + 1 2 τ 2 ε 2 2 q 2 + 1 2 β 3 2 q 2 + 1 2 s 2 2 q 2 + 1 2 + ϑ 2 2
and making λ 1 = min α 1 2 q 1 + 1 2 2 ,   α 2 2 q 1 + 1 2 1 ,   2 q 1 + 1 2 τ 2 ,   α 3 2 q 1 + 1 2 , λ 2 = min β 1 2 q 2 + 1 2 2 ,   β 2 2 q 2 + 1 2 1 ,   2 q 2 + 1 2 τ 2 ,   β 3 2 q 2 + 1 2 , Θ = ϑ 2 2 can be obtained.
V ˙ 1 λ 1 e 1 2 2 q 1 + 1 2 + e 2 2 2 q 1 + 1 2 + ε 2 2 q 1 + 1 2 + s 2 2 q 1 + 1 2 λ 2 e 1 2 2 q 2 + 1 2 + e 2 2 2 q 2 + 1 2 + ε 2 2 q 2 + 1 2 + s 2 2 q 2 + 1 2 + Θ
By Lemma 2, (39) can be rewritten as
V ˙ 1 λ 1 e 1 2 2 + e 2 2 2 + ε 2 2 + s 2 2 q 1 + 1 2 4 1 q 2 2 λ 2 e 1 2 2 + e 2 2 2 + ε 2 2 + s 2 2 q 2 + 1 2 + Θ = λ 1 V 1 q 1 + 1 2 4 1 q 2 2 λ 2 V 1 q 2 + 1 2 + Θ
According to Remark 3, ϑ > 0 is a positive constant, so Θ is a positive real number. Using Lemma 1 and (40), we may show that at time t > T 1 , tracking errors e 1 and e 2 can converge to the origin in a fixed time, regardless of the initial conditions, and the convergence time upper limit is T 2 . The proof is completed. □
Remark 4.
The control parameters should be chosen so that  λ 1 > 0 and λ 2 > 0 .
Remark 5.
From (31), the controller convergence time  T 2 , is determined by  λ 1 ,  λ 2 ,  q 1 , and  q 2 . As  q 1  and  q 2  move away from 1,  T 2  becomes smaller but tends to lead to overshooting.  λ 1  and  λ 2  are determined by  α i  and  β i , and by (31), excessively large  α i  and  β i  also make  T 2  smaller but at the same time lead to the problem of overshooting. So there is also a compromise for the choice of controller parameters.
From the above analysis, according to the first tracking error e 1 = y 1 y 1 d , the new state quantity y 1 can be traced to y 1 d in a fixed time. And then according to (11), the actual DC bus voltage v o through the proposed controller will also be tracked to V r e f in a fixed time. Taking into account the convergence time T 1 of the FxTDO, the whole system convergence time is bounded by an upper limit of T = T 1 + T 2 .

3.6. Current-Sharing Compensator

In this paper, only the sum of the input currents i i n is used as the adjustable variable in simple controller design. However, in practice, the duty cycle deviation may lead to unbalanced inductor currents in each phase. In order to equalize the phase currents, a phase current-sharing compensator (CSC) based on proportional integral (PI) is used in this paper [2]. The CSC diagram for each phase is shown in Figure 3. Setting the reference tracking current of each phase as I c o m = i i n / 3 , the CSC can be designed as
d c o m i = K P c o m ( I c o m i L i ) + K I c o m ( I c o m i L i ) d t
where K P c o m and K I c o m are the compensation gain parameters, and d c o m i is the compensation duty ratio of the ith phase.
d i = d + d c o m i
From the literature [2], it can be shown that the control bandwidth of the CSC can be made much lower than the controller proposed in this paper by choosing the compensation gain parameters appropriately. In other words, d c o m i varies slowly and can be considered as a constant compared to d . Therefore, the effect of current compensation d c o m i on the system stability is negligible, and the stability of the controller proposed in this paper can be guaranteed.
On the basis of the above analysis, the general control block diagram of FTBSMC is illustrated in Figure 4.

4. Simulation and Experimentation

To verify the feasibility and effectiveness of the FTBSMC proposed, first the strategy is verified through simulations on the MATLAB/Simulink platform. Then, experimental verification is conducted by building a low-voltage experimental platform. The electrical parameters employed in the simulation are enumerated in Table 1. The observer parameters are γ 1 = 800 , γ 2 = 4 × 10 5 , m = 0.8 , and n = 1.2 . The controller parameters proposed in this paper are α 1 = β 1 = α 2 = β 2 = α 3 = β 3 = 6000 , q 1 = 9 / 11 , q 2 = 11 / 9 , and τ = 0.1 . The current-sharing compensator compensation gain parameters are K P c o m = 0.03 and K I c o m = 0.01 .
470 μ F

4.1. Selection of Parameters

Due to the FTBSMC proposed in this paper, there are more control parameters. Both the parameters of the FxTDO and FTBSMC proposed affect the dynamic performance of IBC systems, so the tuning of the parameters of both needs to be discussed.
The parameters of the FxTDO are adjusted first. Figure 5 shows the dynamic response of the FxTDO after a 10 kW step change in CPL, keeping γ 1 = 800 , m = 0.8 , and n = 1.2 constant. Figure 5a shows the dynamic performance of the FxTDO for different values of γ 2 . From the figure, it can be seen that the time of convergence of the FxTDO becomes gradually smaller as γ 2 increases, but overshooting occurs when γ 2 = 6 × 10 5 . Therefore, we compromise by choosing γ 2 = 4 × 10 5 . Figure 5b shows the dynamic response of the FxTDO when γ 1 is varied while keeping γ 2 = 4 × 10 5 , m = 0.8 , and n = 1.2 constant. From Figure 5b, it can be seen that a smaller γ 1 will lead to oscillations in the observed waveform of the FxTDO, while a larger γ 1 will slow down the dynamic response; so for the choice of γ 1 , we have to compromise with γ 1 = 800 . For the choice of m and n , the closer both are to 1, the faster the dynamic response of its FxTDO. Figure 5c shows the dynamic response of the FxTDO for different m and n by keeping γ 1 = 800 and γ 2 = 4 × 10 5 constant. From Figure 5c, the closer m and n are to 1, the faster the dynamic response of the FxTDO, but the larger the overshoot. So a compromise is needed for m and n as well. Choose m = 0.8 and n = 1.2 .
A discussion of FTBSMC parameter selection follows. Figure 6 shows the dynamic response of the DC bus voltage after a 10 kW step change in CPL. Figure 6a shows the dynamic response of DC bus voltage for different α i and b i (i = 1,2,3). From Figure 6a, it can be concluded that larger α i and b i lead to a shorter convergence time and smaller voltage transient dips. So larger α i = β i = 6000 is chosen. From Figure 6b, it can be seen that when the values of q 1 and q 2 are close to 1, the faster the DC bus voltage converges. However, we still compromise by choosing q 1 = 9 / 11 and q 2 = 11 / 9 .
Based on the above analysis, for the parameter selection of the controller and FxTDO, a flowchart is drawn as shown in Figure 7. The dynamic response of the FxTDO and DC bus voltage is observed by varying one parameter of the observer and controller and fixing the other parameters as constant. After the dynamic response is as expected, the parameters of the controller and FxTDO are determined.

4.2. Effectiveness of the FxTDO

In practice, CPLs have unknown and time-varying properties. This uncertainty makes controller design difficult. In this paper, the FxTDO is used to observe and compensate for the uncertainty of CPL. To check the effectiveness of the FxTDO, other parameters remain constant and the CPL power varies, as shown in the blue curve in Figure 8, and the red curve is the variation of the estimated value observed by the FxTDO. From Figure 8, it can be clearly observed that the estimates observed by the FxTDO at t = 0.1 s, 0.2 s, 0.3 s, and 0.4 s are able to converge to the value of the actual CPL power within 6 ms of the fixed time. In addition, a simulation comparison between the FTBSMC with and without the FxTDO is carried out, as shown in Figure 9. It demonstrates that without the FxTDO, the system cannot achieve zero steady-state error DC bus voltage regulation under CPL disturbance. The results indicate that the FxTDO can swiftly and accurately detect changes in CPL, effectively eliminate the steady-state error of the DC bus voltage, and enhance robustness against disturbances from CPL changes.

4.3. Effectiveness of the CSC

To verify the effectiveness of the CSC, a comparative experiment was conducted. Figure 10a shows the CSC being disconnected at 0.03 s, while Figure 10b illustrates its normal operation. By comparing the two, it is clear that after the CSC is disconnected at 0.3 s, the inductor currents of each phase become unbalanced. Furthermore, at 0.4 s, the CPL experiences a step change of 5 kW, which makes the uneven current phenomenon even more evident.
Figure 11a is the waveform diagram of the actual control law d and the compensation duty cycle d c o m i when the CSC is working normally. Figure 11b is the local amplification of Figure 11a. As illustrated in Figure 11b, on the same time scale, since the bandwidth of the current-sharing compensator is much smaller than the controller proposed in this paper, d c o m i changes slowly compared with d . Combined with the good current-sharing effect in Figure 10b, it is shown that the slow micro-adjustment of the current-sharing compensator can achieve the current sharing of each phase while ensuring the stability of the controller.

4.4. Effectiveness of the FTBSMC

Connecting the DC bus to a pure CPL is the worst possible operating condition for the MG. Therefore, in the simulation experiments, the resistive load was disconnected and only the CPL was connected. In Figure 12, the dynamic response of IBC by the FTBSMC proposed under different disturbances is shown.
Figure 12a illustrates the dynamic response produced by IBC under the disturbance of CPL power variation. The CPL power P C P L jumps from 10 KW to 20 KW before landing at 15 KW. As illustrated in the figure, the bus voltage is capable of being restored to the reference voltage value within 8 ms under the proposed controller. Moreover, the inductor currents of each phase achieve a good balancing effect.
Figure 12b illustrates the dynamic response of the IBC under the disturbance of DC bus voltage reference change. The reference voltage V r e f varies sequentially from 350 V to 400 V and 450 V. As can be observed from the figure, the DC bus voltage quickly regulated to the reference value in about 3 ms while the phase currents remained balanced.
Figure 12c illustrates the dynamic response of the IBC under the disturbance of input voltage V i n change. The input voltage V i n falls from 200 V to 150 V and subsequently increases to 180 V. As shown in the figure, a voltage dip or shock of less than 5 V occurs at the DC bus, and the output voltage response can fully recover from the input voltage disturbance within 3 ms. In addition, the inductor currents of each phase are balanced.

4.5. Simulation Comparison

In order to demonstrate the stability and rapid dynamic characteristics advantages of the FTBSMC proposed in this paper, we compare it with a backstepping sliding-mode controller + nonlinear disturbance observer (BSMC + NDO) and a conventional double-closed-loop PI controller.
Figure 13 shows the DC bus voltage waveforms for the IBC system under CPL disturbance, with other parameters unchanged. The variation in CPL is shown by the purple curve in Figure 13. For a fair comparison, the control parameters of the double-closed-loop PI controller were finetuned to ensure similar dynamic performance to the other controllers. As illustrated in Figure 13, at time t = 0.1 s, 0.2 s, 0.3 s, and 0.4 s, the CPL experiences a step change of 10 kW. The FTBSMC proposed allows the DC bus voltage of the IBC system to converge to its reference within 8 ms, with negligible steady-state error. In contrast, with BSMC + NDO and double-closed-loop PI controller, it takes about 14 ms. In addition, when the P C P L of the CPL power rises to 40 kW, IBC system DC bus voltage v o under the conventional double-closed-loop PI controller starts oscillating, and the amplitude of the oscillation is larger when the P C P L rises to 50 kW. The presented results show that the FTBSMC proposed shows a larger stability margin and better dynamic performance under CPL disturbance than BSMC + NDO and the double-closed-loop PI controller.
In Figure 14, the dynamic response of the IBC system DC bus voltage is compared for different controllers with varying DC bus voltage references. The reference value of the DC bus voltage is displayed as a purple curve. The results indicate that with the FTBSMC proposed, the DC bus voltage can follow the new reference within 3 ms, while the conventional double-closed-loop PI controller takes 10 ms and the BSMC + NDO takes 8 ms. This shows that the proposed controller achieves faster bus voltage tracking in the IBC system.
Figure 15 compares the dynamic response of the IBC system’s DC bus voltage across different controllers in response to disturbances from input voltage variation. The variation of the input voltage is shown by the purple curve in Figure 15. From Figure 15, it is obvious that when the input voltage disturbance occurs at 0.1 s and 0.15 s, the DC bus voltage under the proposed FTBSMC control dips and overshoots are less than 5 V, which can be recovered to the reference voltage in less than 3 ms. The BSMC + NDO has a similar dynamic response, and the voltage dips and overshoots of the conventional double-closed-loop PI controller are more than 10 V, which can be recovered to the reference voltage only in about 10 ms. In contrast, the IBC system DC bus voltage with the FTBSMC proposed by this paper exhibits a more rapid dynamic response and a reduction in bus voltage fluctuations.

4.6. Experimental Verification

Due to the limited experimental conditions, this paper builds a low-voltage experimental platform, as illustrated in Figure 16. The ITECH load is set in constant power mode as a CPL, and a pure CPL load is used in the experiment. The proposed control strategy is implemented on a Texas Instruments DSP (TMS320F28335) control board. The electrical parameters employed in the experimental platform are enumerated in Table 2. Due to the low power of the CPL used for the experiment. The parameters of the FxTDO for the experiment were chosen according to the methodology in Section 4.1 of the article, which will not be repeated here, and were chosen to be γ 1 = 500 , γ 2 = 8000 , m = 0.8 , and n = 1.2 . The parameters of the controller and the current-sharing compensator proposed in this paper remain unchanged.
Figure 17 shows the experimental waveforms when CPL is varied. The other parameters are kept constant, and the CPL power P C P L is increased by 20 W to 80 W and then decreased back to 20 W. As illustrated, the output voltage v o experiences a dip of approximately 2.5 V when the P C P L increases from 20 W to 80 W, and it shows a shock of about 2.5 V when the P C P L decreases from 80 W to 20 W. Then the output voltages of both recover to the reference value (30 V) within about 8 ms. This indicates that the FTBSMC proposed is effective in keeping the output bus voltage stable under CPL disturbances. In addition, the inductor currents in each phase remain well equalized during steady-state and transient processes.
Figure 18 illustrates the experimental waveforms of the IBC system under varying input voltage. The input voltage V i n rises from 15 V to 20 V and subsequently decreases back to 15 V, and the output voltage v o experiences a very small voltage overshoot and dips (<1 V) and returns to the bus voltage reference (30 V) after a transient process of about 3 ms. The results indicate that the FTBSMC proposed has a good robustness to the input voltage variation disturbance. Furthermore, the balance of the inductor current can be maintained during both transient and steady-state processes in each phase.
Figure 19 shows the experimental waveforms with other parameters kept constant and the output voltage reference V r e f increased from 30 V to 35 V. From the experimental waveforms, it is evident that when the V r e f changes, the IBC system output voltage can be tracked to the V r e f within 5 ms (3 ms). The experimental results indicate that the FTBSMC proposed has a large stability margin and good dynamic response to the DC bus voltage variation disturbance. Meanwhile, the phase currents can still be balanced in transient and steady states.

5. Conclusions

In this paper, the FTBSMC is proposed for an IBC feeding a CPL in a DC microgrid. By employing a generalized reduced-order averaging model and converting it to Brunovsky’s standard form, we simplify the controller design. The FTBSMC proposed combines the fast dynamic response of SMC with the global stability of backstepping control. This combination significantly enhances the system’s dynamic performance and robustness while effectively alleviating the singularity issues associated with SMC. Further, the FxTDO is used to estimate load disturbances in a fixed time, which further enhances the system’s immunity to disturbances. To address the direct differentiation problem in conventional backstepping control, a first-order nonlinear filter is introduced, while ensuring overall fixed-time stability. Furthermore, a simple phase current-sharing compensator ensures balanced inductor currents across each phase. The fixed-time convergence of the proposed control strategy is rigorously demonstrated by Lyapunov stability analysis, and an upper bound on the convergence time is approximated. Simulation and experimental results demonstrate that the FTBSMC proposed has better robustness and faster dynamic performance than BSMC + NDO and the conventional double-closed-loop PI controller. It quickly and efficiently handles time-varying constant power loads, reference voltage changes, and input voltage variation disturbances. It also maintains good phase-to-phase current balance in both transient and steady-state conditions.

Author Contributions

Conceptualization, H.W. and G.H.; methodology, H.W. and G.H.; software, H.W. and G.H.; validation, H.W. and G.H.; formal analysis, H.W. and G.H.; investigation, Y.D.; resources, G.H.; data curation, H.W.; writing—original draft preparation, H.W. and W.S.; writing—review, and editing, H.W. and G.H.; visualization, W.S.; supervision, Y.D.; project administration, Y.D.; funding acquisition, Y.D. All authors have read and agreed to the published version of the manuscript.

Funding

This research was funded by Henan Province, China, grant number 24210230202. The project name is Research and Application of Key Technology of Active Disturbance Rejection Control for Shunt Active Power Filter. The project host is Dong Yanfei.

Data Availability Statement

The data presented in this research study are available in this article.

Conflicts of Interest

The authors declare no conflicts of interest.

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Figure 1. DC microgrid system using IBC.
Figure 1. DC microgrid system using IBC.
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Figure 2. Simplified three-phase IBC-interfaced MGs.
Figure 2. Simplified three-phase IBC-interfaced MGs.
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Figure 3. Current-sharing compensator.
Figure 3. Current-sharing compensator.
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Figure 4. The general control block diagram of FTBSMC.
Figure 4. The general control block diagram of FTBSMC.
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Figure 5. Dynamic response of the FxTDO under different parameter variations. (a) γ 2 variation; (b) γ 1 variation; (c) m and n variation.
Figure 5. Dynamic response of the FxTDO under different parameter variations. (a) γ 2 variation; (b) γ 1 variation; (c) m and n variation.
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Figure 6. Dynamic response of the DC bus voltage under different parameters variation. (a) α i and β i variation; (b) q 1 and q 2 variation.
Figure 6. Dynamic response of the DC bus voltage under different parameters variation. (a) α i and β i variation; (b) q 1 and q 2 variation.
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Figure 7. Parameter selection flowchart.
Figure 7. Parameter selection flowchart.
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Figure 8. FxTDO dynamic response when CPL changes.
Figure 8. FxTDO dynamic response when CPL changes.
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Figure 9. The DC bus voltage response under FTBSMC control with FxTDO and without FxTDO.
Figure 9. The DC bus voltage response under FTBSMC control with FxTDO and without FxTDO.
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Figure 10. Output current response: (a) current-sharing compensator being disconnected at 0.03 s; (b) current-sharing compensator working normally.
Figure 10. Output current response: (a) current-sharing compensator being disconnected at 0.03 s; (b) current-sharing compensator working normally.
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Figure 11. The waveform of the actual control law and the compensation duty cycle. (a) CSC working normally and CPL power takes a 5 kW step change at 0.04 s. (b) Local enlargement of (a).
Figure 11. The waveform of the actual control law and the compensation duty cycle. (a) CSC working normally and CPL power takes a 5 kW step change at 0.04 s. (b) Local enlargement of (a).
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Figure 12. Dynamic response of IBC system under different disturbances. (a) CPL power variation disturbance. (b) DC bus voltage reference value change disturbance. (c) Input voltage variation disturbance.
Figure 12. Dynamic response of IBC system under different disturbances. (a) CPL power variation disturbance. (b) DC bus voltage reference value change disturbance. (c) Input voltage variation disturbance.
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Figure 13. DC bus voltage of IBC under CPL variation.
Figure 13. DC bus voltage of IBC under CPL variation.
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Figure 14. DC bus voltage of IBC under DC bus reference voltage variation.
Figure 14. DC bus voltage of IBC under DC bus reference voltage variation.
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Figure 15. DC bus voltage of IBC under input voltage variation.
Figure 15. DC bus voltage of IBC under input voltage variation.
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Figure 16. Experimental platform.
Figure 16. Experimental platform.
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Figure 17. Experimental waveforms when CPL changes: (a) CPL power change from 20 W to 80 W; (b) CPL power change from 80 W to 20 W.
Figure 17. Experimental waveforms when CPL changes: (a) CPL power change from 20 W to 80 W; (b) CPL power change from 80 W to 20 W.
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Figure 18. Experimental waveforms when the input voltage changes: (a) input voltage change from 15 V to 20 V; (b) input voltage change from 20 V to 15 V.
Figure 18. Experimental waveforms when the input voltage changes: (a) input voltage change from 15 V to 20 V; (b) input voltage change from 20 V to 15 V.
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Figure 19. Experimental waveforms when the output voltage reference is changed.
Figure 19. Experimental waveforms when the output voltage reference is changed.
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Table 1. Simulation of electrical parameters.
Table 1. Simulation of electrical parameters.
ParametersSymbolValue
Reference voltage DC busVref400 V
Input voltageVin200 V
CapacitanceCf 470   μ F
Interleaved inductorL1/L2/L31.5 mH
Switching frequencyfs20 kHz
Constant power loadPCPL10 kW
Table 2. Experimental electrical parameters.
Table 2. Experimental electrical parameters.
ParametersSymbolValue
Output voltage referenceVref30 V
Input voltageVin15 V
CapacitanceCf 470   μ F
Interleaved inductorL1/L2/L30.66 mH
Switching frequencyfs20 kHz
Constant power loadPCPL80 W
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Wang, H.; Dong, Y.; He, G.; Song, W. Fixed-Time Backstepping Sliding-Mode Control for Interleaved Boost Converter in DC Microgrids. Energies 2024, 17, 5377. https://doi.org/10.3390/en17215377

AMA Style

Wang H, Dong Y, He G, Song W. Fixed-Time Backstepping Sliding-Mode Control for Interleaved Boost Converter in DC Microgrids. Energies. 2024; 17(21):5377. https://doi.org/10.3390/en17215377

Chicago/Turabian Style

Wang, Hang, Yanfei Dong, Guofeng He, and Wenbin Song. 2024. "Fixed-Time Backstepping Sliding-Mode Control for Interleaved Boost Converter in DC Microgrids" Energies 17, no. 21: 5377. https://doi.org/10.3390/en17215377

APA Style

Wang, H., Dong, Y., He, G., & Song, W. (2024). Fixed-Time Backstepping Sliding-Mode Control for Interleaved Boost Converter in DC Microgrids. Energies, 17(21), 5377. https://doi.org/10.3390/en17215377

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