A Single DC Source Five-Level Switched Capacitor Inverter for Grid-Integrated Solar Photovoltaic System: Modeling and Performance Investigation

Abstract

Boost converters and multilevel inverters (MLI) are frequently included in low-voltage solar photovoltaic (PV) systems for grid integration. However, the use of an inductor-based boost converter makes the system bulky and increases control complexity. Therefore, the switched-capacitor-based MLI emerges as an efficient DC/AC voltage convertor with boosting capability. To make classical topologies more efficient and cost-effective for sustainable power generation, newer topologies and control techniques are continually evolving. This paper proposes a reduced-component-count five-level inverter design for generating stable AC voltages for sustainable grid-integrated solar photovoltaic applications. The proposed topology uses seven switching devices of lower total standing voltage (TSV), three diodes, and two DC-link capacitors to generate five-level outputs. By charging and discharging cycles, the DC capacitor voltages are automatically balanced. Thus, no additional sensors or control circuitry is required. It has inherent voltage-boosting capability without any input boost converter. A low-frequency-based half-height (HH) modulation technique is employed in the standalone system for better voltage quality. Extensive simulations are performed in a MATLAB/Simulink environment to estimate the performance of the proposed topology, and 17.58% THDs are obtained in the phase voltages. Using a small inductor in series or an inductive load, the current THD reduces to 8.23%. Better dynamic performance is also observed with different loading conditions. A miniature five-level single-phase laboratory prototype is developed to verify the accuracy of the simulation results and the viability of the proposed topology.

1. Introduction

Environmental concern, increasing fuel prices, and growing load demand led to the transformation of electricity generation in past two decades with more and more renewable energy sources feeding into the grid [1]. The grid-connected solar PV systems necessitate high-power medium-voltage inverters for converting DC to AC at the correct amplitude and frequency [2,3]. The conventional solar power generation system generally uses a step-up transformer, a boost converter, and a line filter as shown in Figure 1. Utilizing these components makes the system bulky, less efficient, and increases cost and operational difficulty [4]. It is essential that inverters are highly reliable and effective to minimize the cost of return without compromising quality [5]. Although a two-level inverter produces a quasi-square wave, its output contains a high value of THD (48.21%) requiring large filters and is also less efficient [6,7].

Following the invention of the first three-level inverter in 1975 [8], various multilevel inverter (MLI) topologies, such as the cascaded H-bridge (CHB), neutral-point-clamped (NPC), flying capacitor (FC), and modular multilevel converter (MMC) were suggested [9]. All of these have common attractive characteristics such as better output voltage quality, a lower device voltage rating, higher efficiency, better power loss distribution, lower harmonic distortion, lower dv/dt, lower EMI, and suitability for medium voltage or high voltage application. All these benefits can be obtained at the expense of a higher number of power switches and other passive components, also requiring complicated modulation and control circuitry. The FC MLI employs balancing capacitors on phase buses, which are clamped by capacitors rather than diodes. The CHB is widely used because of its modular design and greater flexibility. It typically consists of a group of H-bridge cells that may combine the DC voltage from a number of different sources to produce the required voltage [10]. In all topologies, the voltage quality improves as the number of levels increases. However, the control becomes challenging in conventional MLIs because of the exponential rise in the number of driving circuits and components required as the number of levels rises.

PV system demands compact MLIs with boosting capability that can generate low THD voltage. Recently, switched capacitor (SC)-based MLIs emerged as DC/AC voltage convertors with boosting capability. The SC unit has a variable voltage output range that covers an extensive range and depends on the configuration. A conventional active neutral point clamp (ANPC) topology using capacitors was developed in [11]. A sole DC voltage source, eight IGBTs, and three capacitors are required to produce five output voltage levels across the load terminal. Nevertheless, no means of increasing the output voltage is incorporated into this structure. Further ANPC topologies of two distinct varieties were introduced in [12]. These topologies lack voltage-boosting capability and face voltage-balancing problems like conventional NPC and FC topologies. The T-type nested neutral-point-clamped converter (T-NNPC) is a novel architecture suggested by [13] that uses a sole DC supply and four capacitors. This architecture can generate voltage across the load at five distinct levels. The drawbacks of this design are the increased switch voltage and the absence of boosting capability. For motor-driving applications, Ref. [14] presents a five-level H-bridge/NPC (5L-HNPC) structure involving a transformer that is phase-shifted to produce a DC supply with independent voltages for each phase. So, this topology could not be efficient since the transformer makes the system more extensive and expensive. For high-power uses, Ref. [15] presents a five-level nested neutral-point-clamped (5L-NNPC) converter which faces a complex controlling mechanism due to the lack of idleness in the operating states, and this topology entails an advanced model predictive control (MPC) mechanism to regulate the voltage of the flying capacitors under changeable load power factors and modulation indices [16]. A new five-level voltage source inverter (5L-VSI) has been proposed in [17], which uses two DC supplies and three capacitors to generate the desired output voltage. This topology uses high-switching devices and capacitors; therefore, it could not be cost-effective. These things considered, it lacks voltage-boosting capability. In [18], the author offers a ‘dual-T-type five-level inverter’ to mitigate the surge in impulse charging current. This structure’s eight power switches can be modulated to provide voltage at five distinct levels, with a gain of two. Including inductance raises the degree of difficulty in the system. To further minimize the number of IGBTs, a 1-Φ five-level asymmetric hybrid H-bridge inverter is described in [19,20] to reduce the amount of IGBTs, while in [21] a 5L ANPC inverter has been proposed for 1-Φ services. Two inverters’ three-phase extensions need six legs since each phase uses two asymmetrical legs. Thus, the two inverters cannot work with commercial three-level NPC modules. Again, it is seen that most switch capacitor multilevel inverters have faced voltage-balancing problems because of unequal charging and discharging. This problem arises when many capacitors are used with a single DC source. However, a few articles have tried to address this issue. For traditional neutral-point-clamped (NPC) MLI, a voltage-balancing system was implemented based on variables such as, for example, the modulation index (frequency and amplitude) and the power factor. Capacitor voltage balancing, however, becomes more complicated when more levels are added [22,23,24].

Although not easy, adjusting capacitor voltage is essential [25,26]. Therefore, researchers and academicians are now focusing on self-balancing topologies for reducing relevant voltage-balancing problems. In [27], the author proposed a five-level inverter topology that solves the problems of balancing by using two capacitors, inductance, four switching devices, and directional switching. Nevertheless, it lacks voltage-boosting capability. Researchers were intrigued by a proposed modified five-level ANPC inverter [28], which used many capacitors to generate five levels across the load terminal but still required a lot of power. Amplified voltage gain, the balanced voltage across capacitors, and less stress are all benefits of a recently suggested five-level split-midpoint cross-clamped (5L-SMCC) inverter [29]. Moreover, another author presented a novel topology for a five-level ANPC switched capacitor inverter, which would do away with the drawbacks of the traditional five-level ANPC inverter [30]. Despite its self-balancing and voltage-boosting abilities, its total blocking voltage and cost are prohibitive. Scientists are still working hard to perfect a topology that is not just cheap but also capable of boosting and self-balancing [31,32].

This paper proposes a single-phase five-level inverter based on switching capacitors. It is able to achieve an output voltage that is equal to two times the DC input voltage. The switched-capacitor-based inverter design that is being suggested produces five-level output voltages with only two capacitors, one DC source, and seven switching devices. A low-frequency half-height approach is utilized to generate the firing pulses of switching devices in a standalone system for higher output voltage quality and lower THDs. However, for current-controlled grid-integrated solar PV systems, we adopt high-frequency modulation technology because this approach decreases the filter size. However, the salient features of the proposed topology are:

• Double boosting of output voltage without an inductive element or boost converter suitable for sustainable renewable energy applications.
• Self-balancing of DC-link capacitor voltage without a controller or sensors.
• Stable output voltage with lower THD.
• Simple but effective control of switching devices using the half-height method for a standalone system.
• A reduced device count and smaller device footprint.
• Lower voltage stress across the switches.

There are eight main parts to this study. Section 2 outlines the modeling of the proposed multilevel inverter. The proposed MLI’s modulation method and capacitance calculation are covered in Section 3. Section 4 presents the grid-integrated PV system using the proposed inverter, while Section 5 discusses the results from the simulations. Section 6 discusses the results of the experiments. The comparative analysis is presented in Section 7. Finally, Section 8 concludes by summarizing the findings of the proposed work.

2. Proposed Multilevel Inverter Model

2.1. Structure

The structure of the proposed five-level inverter scheme is shown in Figure 2. It consists of 7 switches, 3 diodes, and 2 capacitors. Switches S₁–S₄ comprise the voltage inversion part, and S₅–S₇ make the voltage-balancing part. It uses a single DC supply and achieves balanced voltage across the capacitors. It generates stable and double-boosted output voltage with lower THD, making it superior to most other DC-link-based MLIs (such as NPC and FC). It works fairly well under both RL and dynamic loads. Its modular structure allows the generation of more levels via a cascading link.

2.2. Operation

The entire operation of the inverter can be explained using the five different modes, as mentioned in

Table 1. Functioning modes of suggested topology.

Operating Mode	Capacitor Charging and Discharging States				Five-Level Inverter					Vout
	S6	S7	C1	C2	S1	S2	S3	S4	S5
Mode 1	1	0	─	↓↑	1	0	0	1	0	V
Mode 2	0	1	↑↓	↓	1	0	0	1	1	2V
Mode 3	1	0	─	↑↓	0	1	1	0	0	−V
Mode 4	0	1	↑↓	↓	0	1	1	0	1	−2V
Mode 5	1	0	-	↑	0	0	1	1	0	0

↑: Charging, ↓: Discharging, and ─: Floating.

. Anytime the capacitor is connected in parallel with the source, V_in will be charged to a voltage V_c = V_in (Figure 3a) in a very short time determined by the time constant ${\tau }_c=r_c{C}_i$, where r_c is the total resistance in the charging path which is very small. When the capacitor is isolated from the source and the load (R_L) is connected across it (Figure 3b), it will be discharged slowly determined by the time constant ${\tau }_d=(r_c+R_L)C_i$. In the voltage-boosting mode, the capacitor will be connected in series with the load and source (Figure 3c), and both charging and discharging will take place simultaneously.

Details of the different switching modes are shown in Figure 4. The charging path is displayed in green, and the discharging path in blue; the red line represents the capacitor being charged and discharged simultaneously. The operation of each mode is described below:

Mode 1: To achieve a voltage V across capacitor C₂, as Figure 4a depicts, we first activate switch S₆. Thus, the output voltage is V when switches S₁ and S₄ are engaged.

Mode 2: Here, the capacitor C₁ is charged to V volts by activating switch S₇. C₂ is discharging at this moment which may cause a slight distortion in the voltage across the load terminal. With the purpose of getting 2V across the load terminal, switches S₁, S₄, and S₅ must be activated. The operation of this mode is depicted in Figure 4b.

Mode 3: By activating switch S₆, the capacitor C₂ is charged to voltage V. Figure 4c depicts this operation where activating switches S₂ and S₃ results in an output voltage of −V.

Mode 4: Switch S₇ activates capacitors C₁ and C₂ to produce a 2V voltage in this mode. Currently, C₁ is charging and C₂ is discharging. As indicated in Figure 4d, switches S₂, S₃, and S₅ must be flipped in order to provide a voltage drop of −2V across the load terminal 4.

Mode 5: As switches S₄ and S₃ are active, the voltage across the load is zero in this setup. Figure 4e shows a schematic representation of the corresponding circuit. Capacitor C₁ is only being charged in this configuration.

The balancing of capacitor voltage can be analyzed through the energy balanced in each capacitor during one complete cycle [33,34]. Figure 5 illustrates the charging and discharging of capacitors in one cycle.

Let us consider that the output voltage and current is a sine function.

$$V_o=V_m\sin \omega t$$

(1)

$$I_o=I_m\sin (\omega t-\varnothing )$$

(2)

where V_m and I_m are the peak values of output voltage and current, and $\varnothing$ is the phase difference between output voltage and current. Energy stored or released by the DC capacitor is given by Equation (3):

$$\begin{gathered} dU=Vdq=VIdt I=\frac{dq}{dt} \\ U=\int Vdq=\int VIdt \end{gathered}$$

(3)

where I, V, q, and U are the current flowing through capacitor, voltage across, charge, and energy stored by the capacitor, respectively.

The energy sored in the positive half for capacitor C₂ can be calculated as follows:

$$\begin{gathered} U_{C2}^{+}={{\displaystyle \int }}_0^{\pi }{V}_E{I}_m\sin \left(\omega t-\varnothing \right)dt \\ \begin{array}{c}={{\displaystyle \int }}_0^{{\alpha }_1}0.I_m\sin \left(\omega t-\varnothing \right)d\omega t+{{\displaystyle \int }}_{{\alpha }_1}^{{\alpha }_2}E.I_m\sin \left(\omega t-\varnothing \right)d\omega t\hfill \\ +{{\displaystyle \int }}_{{\alpha }_2}^{{\alpha }_3}\begin{array}{c}0.I_m\sin \left(\omega t-\varnothing \right)d\omega t+{{\displaystyle \int }}_{{\alpha }_3}^{{\alpha }_4}E.I_m\sin \left(\omega t-\varnothing \right)d\omega t+{{\displaystyle \int }}_{{\alpha }_4}^{\pi }0.I_m\sin \left(\omega t-\varnothing \right)d\omega t\end{array}\hfill \end{array} \\ =E{I}_m[\cos \left({\alpha }_1-\varnothing \right)-\cos \left({\alpha }_2-\varnothing \right)+\cos \left({\alpha }_3-\varnothing \right)-\cos \left({\alpha }_4-\varnothing \right)]. \end{gathered}$$

(4)

The energy sored in the negative half for capacitor C₂ can be calculated as follows:

$$\begin{gathered} U_{C2}^{-}={{\displaystyle \int }}_{\pi }^{2\pi }{V}_E{I}_m\sin \left(\omega t-\varnothing \right)d\omega t \\ ={{\displaystyle \int }}_{\pi }^{{\alpha }_5}0.I_m\sin \left(\omega t-\varnothing \right)dt+{{\displaystyle \int }}_{{\alpha }_5}^{{\alpha }_6}\left(E\right).I_m\sin \left(\omega t-\varnothing \right)dt \\ \begin{array}{c}+{{\displaystyle \int }}_{{\alpha }_6}^{{\alpha }_7}0.I_m\sin \left(\omega t-\varnothing \right)d\omega t\hfill \\ +{{\displaystyle \int }}_{{\alpha }_7}^{{\alpha }_8}\left(E\right).I_m\sin \left(\omega t-\varnothing \right)d\omega t+{{\displaystyle \int }}_{{\alpha }_8}^{2\pi }0.I_m\sin \left(\omega t-\varnothing \right)d\omega t \hfill \end{array} \\ =-E{I}_m[\cos \left({\alpha }_6-\varnothing \right)-\cos \left({\alpha }_5-\varnothing \right)+\cos \left({\alpha }_8-\varnothing \right)-\cos \left({\alpha }_7-\varnothing \right)]. \end{gathered}$$

(5)

However, α₅ =$\pi$+ α₁; α₆ =$\pi$+ α₂; α₇ =$\pi$+ α₃; α₈ =$\pi$+ α₄.

So, Equation (5) will be

$$U_{C2}^{-}=-E{I}_m[\cos \left({\alpha }_1-\varnothing \right)-\cos \left({\alpha }_2-\varnothing \right)+\cos \left({\alpha }_3-\varnothing \right)-\cos \left({\alpha }_4-\varnothing \right)].$$

(6)

Thus, $U_{C2}^{+}=-U_{C2}^{-}$.

This means that the energy stored in the capacitor C₂ over the course of a full cycle is balanced and constant, maintaining the capacitor voltage at a constant under all circumstances.

The energy sored in the positive half for capacitor C₁ can be calculated as follows:

$$\begin{gathered} U_{C1}^{+}={{\displaystyle \int }}_0^{\pi }{V}_E{I}_m\sin \left(\omega t-\varnothing \right)d\omega t \\ \begin{array}{c}={{\displaystyle \int }}_0^{{\alpha }_1}0.I_m\sin \left(\omega t-\varnothing \right)dt+{{\displaystyle \int }}_{{\alpha }_1}^{{\alpha }_2}0.I_m\sin \left(\omega t-\varnothing \right)d\omega t\hfill \\ +{{\displaystyle \int }}_{{\alpha }_2}^{{\alpha }_3}\begin{array}{c}E.I_m\sin \left(\omega t-\varnothing \right)d\omega t+{{\displaystyle \int }}_{{\alpha }_3}^{{\alpha }_4}0.I_m\sin \left(\omega t-\varnothing \right)d\omega t+{{\displaystyle \int }}_{{\alpha }_4}^{\pi }0.I_m\sin \left(\omega t-\varnothing \right)d\omega t\end{array}\hfill \end{array} \\ =E{I}_m[\cos \left({\alpha }_2-\varnothing \right)-\cos \left({\alpha }_3-\varnothing \right)] \end{gathered}$$

(7)

The energy sored in the negative half for capacitor C₁ can be calculated as follows:

$$\begin{gathered} U_{C1}^{-}={{\displaystyle \int }}_{\pi }^{2\pi }{V}_E{I}_m\sin \left(\omega t-\varnothing \right)d\omega t \\ ={{\displaystyle \int }}_{\pi }^{{\alpha }_5}0.I_m\sin \left(\omega t-\varnothing \right)d\omega t+{{\displaystyle \int }}_{{\alpha }_5}^{{\alpha }_6}\left(0\right).I_m\sin \left(\omega t-\varnothing \right)d\omega t \\ \begin{array}{c}+{{\displaystyle \int }}_{{\alpha }_6}^{{\alpha }_7}E.I_m\sin \left(\omega t-\varnothing \right)d\omega t\hfill \\ +{{\displaystyle \int }}_{{\alpha }_7}^{{\alpha }_8}\left(0\right).I_m\sin \left(\omega t-\varnothing \right)d\omega t+{{\displaystyle \int }}_{{\alpha }_8}^{2\pi }0.I_m\sin \left(\omega t-\varnothing \right)d\omega t \hfill \end{array} \\ =-E{I}_m[\cos \left({\alpha }_7-\varnothing \right)-\cos \left({\alpha }_6-\varnothing \right)] \end{gathered}$$

(8)

However, α₅ =$\pi$+ α₁; α₆ =$\pi$+ α₂; α₇ =$\pi$+ α₃; α₈ =$\pi$+ α₄.

So, the Equation (8) will be

$$U_{C1}^{-}=-E{I}_m[ cos\left({\alpha }_2-\varnothing \right)-\cos \left({\alpha }_3-\varnothing \right)].$$

(9)

Thus, $U_{C1}^{+}=-U_{C1}^{-}$.

This means that the energy stored in the capacitor C₁ over the course of a full cycle is balanced and constant, maintaining the capacitor voltage at a constant under all circumstances.

2.3. Three-Phase Arrangement of Proposed Inverter

This subsection details the five-level inverter’s proposed three-phase setup. As can be seen in Figure 6, a single-phase inverter is used to convert the DC-link voltage into a variable five-level output voltage. Since the proposed inverter has a voltage gain of 2, the DC-link voltage should be higher than the inverter output voltage (>Vo/$\surd 2$). An inverter’s ability to ensure power flow to the load depends on meeting these criteria. The three-phase transformer’s neutral points are then shorted, and a trio of single-phase five-level inverters is connected to the 12 terminals. The primary benefits include a greater output voltage with fewer active components, a smaller transformer, a direct current (DC) input source, and less complicated control circuits. This inverter’s fault detection and device replacement processes are simple.

3. Modulation Technique

Generating suitable switching signals for the power devices is an integral part of the MLI modulation method. Since switching losses and total harmonic distortion are so closely related, it has a pronounced influence on the converter’s efficiency and THDs. Several modulation strategies have been developed to improve harmonic performance while reducing losses; these techniques all make use of either the fundamental switching frequency and/or the high switching frequency [35]. In some cases, discontinuous PWM schemes are also proposed for better DC bus utilization [34]. Again, in some papers, a combination of two frequency signals (low and high) has been used to generate firing pulses of multilevel inverters to produce lower switching losses [36]. However, in the low switching frequency range, only one or two switching pulses occur per round, but in the high switching frequency range, numerous switching pulses occur per round [37]. A fundamental frequency modulation strategy was adopted for this study due to its low total harmonics distortion. The half-height method has the lowest THD value [38,39]. In this method, when the value of the sine function hits halfway between the minimum and maximum levels, a switching angle is set. In this technique, the output more closely resembles a sine wave. Following Figure 7, the general formula for determining the principal switching angles in the first quadrant (from 0 to 90°) is given below [39]:

$${\alpha }_i={\sin }^{-1}(\frac{2i-1}{N-1})where i=1,2,3\dots \dots ..\frac{N-1}{2}$$

(10)

where N is the number of levels.

For the suggested topology, the main switching angles (0–90°) are

$${\alpha }_1={\sin }^{-1}(\frac{2-1}{4})=14.48°, {\mathsf{\alpha }}_2={\sin }^{-1}(\frac{2\times 2-1}{4})=48.59°.$$

(11)

Other switching angle are determined as

α₃ = 180° − α₂; α₄ = 180° − α₁; α₅ = 180° + α₁; α₆ = 180° + α₂; α₇ = 360° − α₂; α₈ = 360° − α₁.

The switching arrangements of the designed topology using the half-height method are depicted in Figure 8. The calculated angle is tabulated in

Table 2. Calculated switching angle of the designed topology.

Number of Levels	Switching Angles
Five	α1 = 14.48°	α2 = 48.59°	α3 = 131.41°	α4 = 165.52°
	α5 = 194.48°	α6 = 228.59°	α7 = 311.41°	α8 = 345.52°

.

Calculation of Capacitance

The capacitor values are determined through the calculation of worst discharge time t₁ and t₂, as shown in Figure 7 [40]:

$$t_1=\frac{{\sin }^{-1}\left(\frac{1}{2}\right)}{2\pi f}$$

(12)

$$t_2=\frac{\mathsf{\pi }-{\sin }^{-1}\left(\frac{1}{2}\right)}{2\pi f}.$$

(13)

The maximum discharge quantity of the capacitor (ΔQc) is calculated as

$$\mathsf{\Delta }{Q}_c={{\displaystyle \int }}_{t_1}^{t_2}{I}_{peak}\ast Sin\left(2\pi ft\right)dt .$$

(14)

Now, the maximum capacitor value is given by

$$C\ge \frac{\Delta Q_c}{k.V_{dc}}$$

(15)

where k is the ripple ratio.

4. Grid-Integrated Solar Photovoltaic System with Proposed Multilevel Inverter

A single-phase grid-integrated solar PV system interfaced with proposed MLI is shown in Figure 9.

The input of this PV system employs only 6 series-connected modules per string and 4 parallel strings to generate 230 V(rms). Eliminating the boost converter and its large inductor reduces the cost and footprint of the PV system. In order to get rid of excessive total harmonics distortion, the inverter’s output is fed into an LCL filter circuit before being connected to the grid. Because of its superior attenuation at the system’s high switching frequency, the LCL filter is chosen here. To regulate the flow of current through the inverter and the grid, a proportional resonance controller (PR) current controller is employed. The controller parameters Kp = 500, Kr = 100, and ω²/Kr = 986.83 are determined through trial and error for optimum performance. The PR converter’s output is then added to the grid voltage and the resulting voltage is divided by V_dc to give V_ref. The proposed inverter circuit’s firing pulses are then derived by comparing the V_ref voltage to various carrier signals prepared using the phase disposition (PD) approach. In this grid-integrated system, it is difficult to control the current of the proposed grid connected system using the half-height method, although it works perfectly on a standalone system. For this reason, the PD method is used for the proposed grid connected system.

4.1. Selection of Solar PV Array

The PV system is designed for a 230 V(rms) AC system with a peak power capacity of 1 kW. The 1Soltech 1STH-215-P model is chosen from the PV array library to obtain the necessary parameters P_mpA, I_mpT, and V_OCA. It features an open circuit module voltage (V_oc) of 36.3 V and a 7.84 A short circuit module current (I_sc). Taking into account the PV array’s open circuit voltage V_OCA = 200 V and power P_mpA = 1 kW, the PV modules connected in a series string are estimated as [41]

$$N_s=\frac{V_{dc}}{V_{oc}}=\frac{200}{36.3}\approx 6 .$$

(16)

The maximum current of the solar PV array is given as

$$I_{mpT}=\frac{P_{mpA}}{0.85\times V_{OC}}=32.41 A .$$

(17)

The PV modules connected in a parallel string are estimated as

$$N_p=\frac{I_{mpT}}{I_{sc}}=\frac{32.41}{7.84}\approx 4 .$$

(18)

4.2. Calculation of Filters Parameters

Consider P = rated active power, V_g = grid voltage, V_dc = DC-link voltage, f = grid frequency, f_sw = switching frequency, and f_res = resonance frequency. Thus, the filter values will be referred to in a percentage of the base values [42]

$$Z_b=\frac{v_g{}^2}{P}$$

(19)

$$C_b=\frac{1}{2\pi f{Z}_b} .$$

(20)

Considering allowable output current ripple up to 10%, the inverter side inductance, L_i, is calculated as [42]

$$L_i=\frac{V_{DC}}{16\times f_s\times {\mathsf{\Delta }\mathrm{I}}_{Lmax}}$$

(21)

where $\mathsf{\Delta }{I}_{Lmax}$ is the 10% current ripple and is given by

$$\mathsf{\Delta }{I}_{Lmax}=0.01\times \frac{\sqrt{2}\times P}{V_g} .$$

(22)

Considering a maximum of 5% grid power factor variation, the filter capacitor is given by

$$\mathsf{\Delta }{C}_f=0.05\times C_b .$$

(23)

The grid side inductance $L_g$ can be calculated as

$$L_g=r\times L_i .$$

(24)

The resonant frequency for the filter circuit can be calculated as

$$f_{res}=\frac{1}{2\pi }\sqrt{\frac{L_i+L_g}{L_{i }\times L_g\times C_f}}$$

(25)

where $f_{res}$ must be $10f<f_{res}<0.5f_{sw}$.

Figure 10a illustrates the LCL filter’s frequency response. The noticeable sharp peak at the resonance frequency as well as the opposite sign in gain margin and phase margin confirms the instability of the system. A damping resistor is added in series with the capacitor (C_f), to decrease this sharp peak, and it is calculated using the following the equation:

$$R_{sd}=\frac{1}{3\times 2\pi \times f_{res}\times C_f} .$$

(26)

As shown in Figure 10b, this damping resistor makes the gain margin and phase margin of the same sign and, thus, stabilizes the system.

5. Results and Discussion

The performances of the standalone system and grid-integrated system were evaluated through extensive simulations using MATLAB/SIMULINK.

Table 3. Control Parameters of the Proposed MLI.

Types of System	Parameters	Ratings (Units)
Standalone	Input Voltage	150 V
	Fundamental Frequency	50 Hz
	Output Voltage	300 V
	Load (resistive)	R = 200 Ω, L = 100 mH
	Self-balancing Capacitors (C1, C2)	3300 μF
	L1, Lg, and C	202.8 mH, 202.8 mH, 100 µF,
	Modulation Technique	Half-height Method
Grid-Integrated System	Output Power	1 kW
	Grid Voltage	230 V (rms)
	Frequency	50 Hz
	Switching Frequency	10,000 Hz (PDPWM)
	L1, Lg, C and Rd	4 mH, 2.4 mH, 3 µF, and 7.5 Ω
	DC-link Voltage (Vdc)	200 V
	DC-link Capacitor	1000 µF

contains all of the simulation parameters. The full simulation results are presented below.

5.1. Simulation Results of Standalone System

This subsection presents the simulation results of the standalone system. Figure 11 illustrates the switching pulses of several different switches. The voltage across the capacitors (C₁ and C₂) is depicted in Figure 12. It shows that V_C1 is quite stable all throughout the simulation time frame. While V_C2 does suffer a slight discharge if the load current is flowing, it soon recovers during the next charging cycle. For this reason, its functioning is consistently reliable. The responses (voltage and current) for a constant resistive load (Z_L = 200 Ω) are depicted in Figure 13 and Figure 14, respectively. The voltage and current are perfectly in phase, as evidenced by the THD measurement of 17.58%. Using a small LCL filter, this can be brought down to below 5%. Figure 15 and Figure 16 present that the THD value of the output current drops to 8.23% when a resistive inductive load (R = 200 Ω, L = 100 mH) is connected due to the inductive effect.

To assess the performance with dynamic load change, Z_L is varied from no load to Z₁ (R = 200 Ω, L = 100 mH), then down to Z₂ (R = 100 Ω, L = 50 mH), and then again back up to Z₁ (R = 200 Ω, L = 100 mH). From the voltage and current responses, as shown in Figure 17, it is clear that the voltage remains consistently constant while the current follows the load variations. This shows excellent voltage regulation due to dynamic load. However, the three-phase output voltage, current, and THD profile are depicted in Figure 18. The THD generated by the inverter is about 0.25% using the half-height method.

5.2. Simulation Results of Grid-Integrated Solar Photovoltaic System

This subsection represents the detailed simulation results of the proposed grid-integrated solar photovoltaic system. A solar panel consisting of six series and four parallel strings are used to generate 200 volts across the DC-link capacitor of the solar panel. Figure 19a shows that the DC-link capacitor voltage remains at the designed value. The self-balancing capacitors voltages also maintain the same value as can be seen in Figure 19b and Figure 19c, respectively.

Figure 19d represents the output voltage (≈400 V) response of the proposed five-level inverter before the LCL filter. This double boosting eliminates the need for a boost converter with large size inductor and associated control circuits. These are the main merits of the proposed inverter.

The current controller (PR), designed in Section 4, is used to control the current in the proposed system. Figure 19e,f shows the grid current and inverter current, respectively. From these figures, it is seen that the grid voltage, grid current, and inverter current are in phase which reflects the perfect synchronization.

After analyzing these simulation results it can be concluded that the five-level inverter works fairly well under dynamic loads. These features, along with voltage boosting and self-balancing of the capacitor voltage, will make it a viable option for sustainable development.

6. Experimental Results

A small prototype is developed to validate the theoretical analysis of the suggested structure portrayed in Figure 20.

Table 4. Experimental Setup Parameters of the Proposed MLI.

S. No.	Parameters	Model No.	Ratings
1	DC source	PL-3003T	30 V, 3 A
2	MOSFET	IRF540N	33 A, 100 V
3	Capacitor		3300 µF, 25 V
4	Diodes	1N4007	1000 V, 1 A
5	Controller	Arduino Uno
6	Load	Resistive	220 Ω

lists the design parameters and component specifications. Arduino UNO based a low-cost microcontroller is used to produce switching signals using the half-height technique. Figure 21 demonstrates the gate pulse voltages of several distinct types of switches. Figure 22 displays the voltage across two DC-link capacitors. Figure 23 illustrates the voltage across the load of the suggested structure, which is quite close to the simulation result in Figure 13.

7. Performance Comparative Analysis

The suggested topology is statistically compared to conventional five-level inverters with regard to the component count, voltage gain, total blocking voltage, and balancing capacity. As depicted in Figure 24, the number of switching devices the designed structure requires to generate all five levels is lower than any existing topologies. Despite having three more diodes than the DC and FC MLI topologies, the suggested architecture only requires two DC-link voltages. In contrast to CHB MLI, the suggested topology does not utilize a clamping diode and capacitor. With the suggested topology, a boost converter is not necessary for a grid-integrated system.

Another comparison has been carried out among different switched capacitor five-level inverters and the suggested topology, as shown in Table 5.

The proposed topology uses seven switching devices which is more than Refs. [13,20,27]. The proposed topology uses three diodes which is lower than Refs. [14,30]. In addition, the suggested topology uses only two capacitors to obtain a voltage gain of two. In contrast, Ref. [30] uses three capacitors for a voltage gain of 2. The designed topology also has a low total blocking voltage compared to the topologies described in references [12,20,21,30]. From the above discussion, the suggested topology will be a better choice for a grid-integrated solar photovoltaic system. As can be seen, the proposed topology is more efficient in terms of DC supply, capacitors, and switching devices, while the topologies presented in Refs. [31,32,43] employ less components and have lower TBVs than the proposed topology. However, the design that is suggested only requires a single DC voltage, two capacitors, and seventeen switching devices to generate a three-phase voltage, whereas the other two topologies require three voltage sources, three capacitors, and eighteen switching devices. Therefore, the proposed design will function effectively within a three-phase system. In addition, it is simpler to regulate a single voltage source than it would be to manage three independent DC sources. Since this is also the case for DC voltage regulation, the proposed topology is preferable.

Table 5. Comparison of suggested multilevel inverter with different switch capacitor five-level inverters.

Topology	Total No. of
	Switches	Diodes	Capacitors	Inductor	TBV(×V)	Voltage Gain	Balancing Capacity
Barbosa et al. [11]	8	0	3	0	12	1	No
Soeiro et al. [12]	8	0	3	0	14	1	No
Bahrami et al. [13]	6	0	4	0	10	1	No
Vazquez et al. [14]	8	5	2	0	-	1	No
Dekka et al. [15]	8	2	2	0	-	0.5	No
Narimani et al. [16]	8	2	2	0	-	0.5	No
Dekka et al. [17]	10	0	3	0	-	0.66	No
Lee et al. [18]	10	0	1	1	-	2	Yes
Valderrama et al. [20]	6	0	2	0	20	1	-
Zhang et al. [21]	8	0	2	0	20	1	-
Ye et al. [27]	6	2	2	0	12	1	Yes
Sathik et al. [30]	7	4	3	0	24	2	Yes
Singh et al. [44]	8	-	1	-	-	2	Yes
Agarwal et al. [32]	6	1	1	-	11	2	Yes
Singh et al. [31]	6	1	1	0	-	2	Yes
Rehman et al. [43]	6	0	1	0	-	2	Yes
Proposed	7	3	2	0	12	2	Yes

Table 5. Comparison of suggested multilevel inverter with different switch capacitor five-level inverters.

Topology	Total No. of
	Switches	Diodes	Capacitors	Inductor	TBV(×V)	Voltage Gain	Balancing Capacity
Barbosa et al. [11]	8	0	3	0	12	1	No
Soeiro et al. [12]	8	0	3	0	14	1	No
Bahrami et al. [13]	6	0	4	0	10	1	No
Vazquez et al. [14]	8	5	2	0	-	1	No
Dekka et al. [15]	8	2	2	0	-	0.5	No
Narimani et al. [16]	8	2	2	0	-	0.5	No
Dekka et al. [17]	10	0	3	0	-	0.66	No
Lee et al. [18]	10	0	1	1	-	2	Yes
Valderrama et al. [20]	6	0	2	0	20	1	-
Zhang et al. [21]	8	0	2	0	20	1	-
Ye et al. [27]	6	2	2	0	12	1	Yes
Sathik et al. [30]	7	4	3	0	24	2	Yes
Singh et al. [44]	8	-	1	-	-	2	Yes
Agarwal et al. [32]	6	1	1	-	11	2	Yes
Singh et al. [31]	6	1	1	0	-	2	Yes
Rehman et al. [43]	6	0	1	0	-	2	Yes
Proposed	7	3	2	0	12	2	Yes

Another comparison has been made based on the matric of the cost function as defined in [45]. The cost function can be calculated by using the following equation. Here, Nsw, Ndc, Ngd, Nd, Nc, N_l, α, and TBVp.u. are the No. of switches, DC source, gate driver circuit, diode, capacitor, inductor, cost factor, and total blocking voltage per unit, respectively. The overall results of the net cost function have been presented in Figure 25. For this analysis, cost function is assumed to be 1.

$$\mathrm{CF}=(N_{sw}+N_{gd}+N_d+N_c+N_l+\alpha \times TB{V}_{p.u.})\times N_{dc}$$

(27)

$$NCF=\frac{CF}{N_L}$$

(28)

The figure reveals that the maximum value is found in Ref. [21], while the lowest value is found in Ref. [32]. The proposed topology also achieves the second-lowest value. The proposed topology uses only one DC voltage source and two capacitors, which is less than the three-phase topology (it will use three voltage sources and three capacitors) as presented in Ref. [32], but the proposed topology has a higher net cost function than Ref. [32] for single phase system. So, the proposed topology will be a prospective cost-effective design.

8. Conclusions

A single DC-source, capacitor-based, five-level inverter is developed with double-boosting capability. To generate five-level AC voltage, it uses only seven semiconductor switches, two DC-link capacitors, and three diodes. The switches are operated efficiently through switching signals generated using a simpler low-frequency modulation scheme. A cost-effective but efficient gate pulse generation technique using an Arduino UNO is demonstrated. During each positive and negative half cycle of the generated AC voltage, the capacitors are charged and discharged in a balanced way. So, capacitor voltages are self-balanced without needing extra voltage sensing and control circuits. The generated AC voltage has a THD of 17.58% which yields a current THD of 8.23% with RL load. Excellent dynamic load response demonstrates the inverter’s suitable applicability for a wide range of load variations. The performance of standalone as well as grid-connected single-phase systems have been extensively examined. Through a comparative analysis of device count, component ratings/sizes, output voltage quality (i.e., THD), and voltage-boosting capability, it is revealed that the proposed inverter is quite competitive with regard to contemporary proposed topologies. Boost-converterless and inductorless, this inverter with a capacitor self-balancing arrangement will make an attractive choice for many low- and medium-voltage industries including the grid integration of renewable energy systems. The scalability of the proposed topology for a three-phase system has been outlined. Its performance evaluation will be reported in future publications. Studies on more than five levels as well as higher voltage boosting could be a potential research area. However, the number of capacitors will increase and balancing their voltages will be challenging. In such a case, hybrid topology can be attempted.