2.1. Solar Cell I-V Curve Characteristics
The general
I-V curve characteristics of a solar cell are well known and can be predicted from the simplest electrical model, namely the one-diode model (
Figure 1).
Within this model, a current source (IP) is used to consider the photogenerated current of the solar cell and a diode (D) to model the fact that a cell is, in essence, a P-N junction between two semiconductors. Finally, a parallel resistor (Rp) and a series resistor (Rs) model show that the diode and the source are not ideals (contact resistances, impurities, annihilation between conduction electrons and holes, scattering, and collisions with the crystalline net, etc.).
Since the usual
Rp has a very high value and the
Rs has a low one, from this model it is easy to induce that, for moderate reverse voltages or forward ones under the conduction voltages of the diode, the external current is approximately equal to
IP (the forward current), since the diode is in an off-state and no (or very small) currents flow through it. This region corresponds to the flat sections within the first and second quadrants of the curve in
Figure 2b, where the I
P is labelled as
ISC (solar cell short circuit current), as they are the same. However, if the reverse voltage is applied enough, the avalanche (Zener) voltage of the diode could be reached and the reverse avalanche current through the diode will be added to the forward external current, resulting in currents rapidly increasing over the I
P value (the left region of the curve (b) in
Figure 2). On the forward voltage side, if the conduction voltage of the diode is reached, the forward current through the diode will be subtracted from
IP, and the output current will be reduced. From this point, if the forward voltage continues to rise, the output current will reach zero and will even be reversed, exponentially, to negative values, corresponding to the right region of the curve in
Figure 2b, within the first and fourth quadrants.
2.2. Principles of Operation
As shown in
Figure 3, the proposed
I-V tracer is just based on the current transfer between two capacitors of equal capacitances across a solar cell.
Our design for the three-quadrant I-V tracing takes advantage of the fact that most of the curve (from the second quadrant at the left to the zero current point in the first quadrant) corresponds to positive (forward) values of the current and, for a wide range of voltage values, is approximately constant in the current.
If we connect our solar cell under test to the positive plates of these capacitors, a forward current gives rise to a charge transfer from one capacitor to another and, consequently, the voltages change (one rises and the other diminishes). The changing rate of one capacitor voltage is expressed as shown (1):
So, as the capacitances of both capacitors are the same, their voltage changing rates are the same, with one rising and the other reducing, proportional to the current. Considering that the voltages across the solar cells are the differences of the voltages across each capacitor, these will vary at rates proportional to the currents. This means that, if we start from a difference between the capacitor voltages representing an initial reverse voltage for the cell, we will stand on the flat region of the curve; the solar cell voltage evolution will be (more or less) a linear sweep (as shown in Figure 23 below). As the cell voltage reaches values next to VOC, the cell current diminishes, and the voltage sweep speed slows down (as shown in Figure 22 below). This way, a voltage sweep will be performed naturally, with the curve traveling from the beginning negative voltage in the second quadrant to near the zero current (positive voltage VOC) point, where the charge transfer will stop, and the voltage sweep finishes.
To trace the fourth quadrant section of the curve, another voltage sweep needs to be performed (in this case, starting from an initial cell voltage over VOC and finishing again on VOC). After these two voltage sweeps, we will have traced a complete three-quadrant solar cell curve.
The measurement strategy could also be carried out on small associations of solar cells in series (small modules) and even regular photovoltaic modules (PV modules). For this reason, we designate it as the device under test (DUT).
Measurement process.
The process, controlled by opening or closing the needed switches at each step, is conducted as follows:
Firstly, both capacitors (C1 and C2) are discharged—V(C1) = V(C2) = 0—and all switches (S1, S2, S3, and S4) are opened.
Then, by closing S1, C1 is charged to the source voltage (VS). This voltage (VS), as will be explained later, will be the starting reverse voltage of the curve and could be conveniently adjusted.
S1 is then opened again. At this point, C1 stays charged at vs. and C2 is still discharged. So, V(C1) = vs. and V(C2) = 0 V.
S2 is then closed; at this point, the voltage at the DUT terminal is the differential voltage between the positive plate of
C2 and the positive plate of
C1—that is,
V(DUT) =
V(
C2) −
V(
C1)—. That means a reverse polarisation of the solar cell, which, considering its expected behaviour (described in
Section 2.1), will supply a current proportional to its irradiation flowing from
C1 toward
C2 and, consequently, increasing the
C2 voltage and lowering the
C1 voltage by means of the charge transfer. This current will only stop when the DUT reaches the open circuit forward polarisation voltage (
VOC), so the first and second quadrant regions travel (including the zero-voltage point); at the end of this process, the first voltage sweep (as described before) will be over.
Now, to perform the second voltage sweep, S2 is opened, and immediately, S3 is closed. This discharges C1, so V(C1) = 0 V. At this point, C2, whose voltage increased by means of the charge transfer process, will remain charged.
S2 has closed again while S3 remains closed. Now, the negative side of the DUT will stand at ground level while its positive side will be at V(C2). In this case, V(DUT) = V(C2)–0, which, by design, is far higher than the V(DUT)OC. The DUT is now forward-polarised beyond the open circuit point, and the current flows opposite to the previous cases, from C2 to the ground until V(DUT)OC is reached (decreasing from higher voltages). Consequently, the DUT is forced to travel the fourth quadrant of its I-V curve at this step.
Once the process ends and the current stops flowing, S4 is closed to discharge C2 completely, leaving the apparatus ready to start a new measurement from step 1 (S4 has opened again after the discharge).
Tracing the I-V curve of a photovoltaic cell.
Step 4 of the described process is the beginning of the tracing. With the capacitor
C1 charged to the source voltage (
VS) and the capacitor
C2 totally discharged, we apply a positive voltage at the negative terminal of the PV cell and zero to the positive terminal; that is, a negative voltage (see
Figure 2b). The starting negative value of the voltage is equal to −
VS, so by adjusting this source voltage it is possible to start the tracing at any desired point—even capturing the avalanche zone in the right region of
Figure 2b. In this case, the current will flow inside the cell mostly through the current source since the diode is reverse-biased and the parallel resistance should ideally be very high (see
Figure 4a). If the avalanche zone of the diode is reached with −
VS, the reverse current in the diode will be added to the cell current. Consequently, the current value is determined by the PV cell’s short-circuit current (
ISC) with the possible addition of an avalanche current at the beginning of the trace. The discharge of
C1 (due to this current) will produce the charge of
C2, or, equivalently, move to the right, along the
I-V curve (see
Figure 4b). When the voltage of both capacitors is equalised, the difference across the terminals of the cell will be 0 V; so in the
I-V curve, it will be at the crossing point with the current axis (
ISC). The cell will continue along its normal
I-V curve until it reaches
VOC, where it cannot push more electrons outside itself—so,
V(
C2) −
V(
C1) =
VOC—. These assumptions and graphs are also applicable to the PV module. Indeed, a PV module is just a series association of single cells (sometimes there are also parallel associations) and some bypass diodes, so the effect over the
I-V curve is just to multiply the
VOC by the number of cells in the series and the
ISC by the parallel lines (in case a parallel association exists). Of course, these assumptions are only valid if all the cells are equal and are in a good state. If there are bad cells, many deformations over the
I-V curve occur, but the study of these cases is beyond the scope of this paper.
After discharging the remaining charge in
C1 at step 5, the capacitor
C2 is positively charged—at about (
VS +
VOC)/2, since the capacitances of
C1 and
C2 are equal, so when the switch
S2 is closed at step 6, the PV cell is forced to jump to a state where a positive voltage is applied to its terminals (the fourth quadrant of its
I-
V curve). If the starting voltage of the previous process (
VS) is high enough, the remaining voltage in
C2 will be higher than
VOC. Then, as can be seen in
Figure 5a, the current will flow mostly across the diode (now polarised in the forward bias), because the photogenerated current goes in the opposite direction and the parallel resistance should be ideally very high. The current will flow until the potential difference at the ends of the diode reaches its forward conduction voltage. The
VOC of the PV cell now has a clear meaning—the voltage needs to put its own diode in conduction when the generated photo-charges flow across the P-N junction and annihilate. For this reason, it is impossible to overpass this point just by illuminating the cell; it must be forced with an external source. On the
I-
V curve, the path followed will be to the left, until
VOC (see
Figure 5b). Regarding the measurements of a PV module or serial associations of cells, the same reasons exposed before can be applied here; the process will be similar but with the voltages and/or currents raised.
2.3. Device Implementation
Time of the process and capacitance calculation.
The time spent in the charge transfer between
C1 and
C2 depends on the current flowing from the first to the second, as well as their capacitances. Of course, the higher the capacitances of both capacitors, the higher the time. The current depends on the technology fabrication of the PV cell and its efficiency, especially, on its surface area. For silicon technology (mono or polycrystalline) cells of common sizes today (around 160 by 160 mm),
ISC goes from 7 to 12 A, more or less (however, larger sizes are coming in future years). Current (
I) is related to charge (
Q) and time (
t) by its definition, and the voltage across the capacitors (
V) is obtained by dividing the charge stored (
Q) over the capacitance (
C), assuming a constant current process, as shown (2):
In fact, the current in a general case is not strictly constant, especially if the avalanche zone is also traced, but this calculation can provide us with the order of magnitude of the processing time for some chosen capacitances and voltages at the source. For a more precise estimation of the real-time, we simulate the circuit in LTSpice with the one-diode model for the DUT (see
Figure 6), for the first voltage sweep.
As an example, for the circuit simulated in
Figure 6, with an initial
V(
C1) = 15 V,
V(
C2) = 0 V,
I(DUT)
SC = 10 A and
C1 =
C2 = 10,000 μF (with reasonable values for the diode characteristics, the parallel resistance, and the series resistance), the current flow and voltages at capacitors are shown in
Figure 7. This simulation corresponds to the first voltage sweep described in
Section 2.2. The second quadrant curve is traced from the starting point to the time where
C1 and
C2 voltage traces overlaps; that is,
V(DUT) = 0 V, and then the usual
I-V curve of the PV device (first quadrant) is traced until the end of the sweep. We can appreciate better in
Figure 8 how effectively the final voltages of both capacitors are not equal, but the difference is the
VOC of the measured cell. The total sweep time in this example is around 9.4 ms, and the capacitor voltage trace overlap occurs at 7.4 ms, so the usual
I-V curve in the first quadrant is travelled in about 2 ms.
For our prototype, we chose capacitors with capacitances of 22,000 μF rated up to 40 V. This added to the use of PV cells with ISC = 7.5 A and gave us more than double the amount of time to perform the measurements.
If we simulate in LTSpice the second voltage sweep (step 6 of the process, see
Figure 9), we also obtain a time of around 2 ms (see
Figure 10), but as shown in the figure, this implies currents of hundreds of amperes that will destroy the current sensor, so, to limit the reverse current for this measurement, an external resistor must be placed in series with the circuit. A shunt diode conducted in the forward current direction of the current avoids this series resistance for first sweep measurements. The effect of adding a resistor of 0.3 Ω is shown in
Figure 11, where more moderate currents occur and the time spans 20 ms.
Prototype design.
For switch implementations, we selected metal oxide semiconductor field-effect transistor (MOSFET) devices controlled by a microcontroller (MCU) programmed adequately. The same integrated circuit (IC), a PIC16F1615, is capable of measuring voltages using a 10-bit analog-to-digital-converter (ADC) with eight multiplexed input channels. For the current measurements, a Hall-effect sensor IC (TMCS1100) in series with the current path was installed.
This IC delivers an output voltage proportional to the current measured, in the range [0, 2.5) V for negative values of the current and in the range [2.5, 5] V for positive currents (including 0 A), and is rated to a maximum current of ±10 A, delivering a voltage of 5 V in the case of +10 A and 0 V in the case of −10 A. The voltage swing entering the ACD input must be 0 V to 5 V, so the current measurement IC can be directly connected to the analog input of the MCU, but for the voltage measurements, a voltage level adaptor circuit must be inserted. Voltages across the two capacitors (
C1 and
C2) determine the DUT voltage that we want to finally measure, so an operational amplifier (OA) fed with the two capacitor voltages at its inverting and non-inverting inputs will output the difference between them, adding gain or attenuation if desired, depending on the external resistors. For the full
I-V curve tracing, we must measure differential voltages, positive (on the first and fourth quadrants) and negative (on the second quadrant); the voltage swing in the first case—from 0 V to around (0.6–0.8) V—is much smaller than in the second one—from 0 V to vs. around (10–15) V. In addition, a good resolution is desirable in the usual first quadrant section of the curve, just where the voltage swing is smaller. For this reason, two different level adaptors have been designed for each section, both with output voltage swings from 0 to 5 V: the first amplifying OA without inversion, with an input active differential voltage from 0 to 0.8 V for the positive adaptive voltages, and the second attenuating OA with inversion, with an input active differential voltage from −15 to 0 V for the negative adaptive voltages. Two of the ADC multiplexer inputs are connected to the outputs of the OA level adaptors described and the firmware within the MCU will select the proper input depending on the section of the curve being measured. The detection of the zero-voltage point crossing will be the decision point for the MCU (for switching one channel to another).
Figure 12 shows the connections of the OA level adapters (without external resistors for simplicity) and the current sensor IC.
The scheme used to measure the voltage and current is shown in
Figure 12. For the voltage across the solar cell, four-terminal sensing is used to determine it with enough precision. This concept must be transferred to the PCB design and the cables soldered to the DUT (using independent wires for the current and for the voltage to ensure a correct Kelvin sensing).
As soon as the MCU finishes the MOSFET (switches) sequence described in
Section 2.2 (to start the first voltage sweep), it selects the proper ADC channel (the negative voltages level adaptor) and starts sampling voltage/current points. For the sake of a proper sampling speed, these pairs of current/voltage samples (10 bits of resolution each) are stored within the internal EEPROM memory of the MCU. When the MCU detects the zero-voltage point, it switches to the positive voltage ADC channel and continues sampling. Finally, the detection of the current samples close enough to zero indicates the first sweep end, and then the MCU performs the MOSFET switches sequence to start the second voltage sweep corresponding to negative values of the current. The sampling continues until the zero current point is detected again (the fourth quadrant section of the curve is traced with decreasing values of the voltage), and the full
I-V tracing is over. At this moment, all the samples stored in the internal MCU memory are dumped to an external host via the RS232 serial port integrated within the MCU, where they will be properly scaled and plotted, and the device will be ready for another tracing.
For all these tasks, we used a cheap 8-bit MCU that had an internal clock of 32 MHz, a maximum sampling rate of 100,000 samples/s, and an internal EEPROM memory capable of 500 samples (10 bits of resolution each). As we mentioned before, it is desirable to achieve a better resolution in the first quadrant section of the curve, since it is the natural working area of the cell, so an adaptive resolution was programmed in the MCU firmware in such a way that the speed of sampling is higher in this section than in the others. This adaptive sampling could also be capable of taking curve points evenly distributed along the curve, even when the variations in the current in some sections during the sweeps lead to different sweeping speeds. Of course, the behaviour of the sampling could be adjusted as needed, or even modified from the host via RS232 commands. The most critical section for the sampling speed is the positive voltage one, where the current is close to ISC and a large resolution is required. We mentioned before that for our prototype the sweep time for this region of the curve was in the order of 1 to 2 ms, with a maximum sampling speed of the MCU (100,000 samples/s), so we could take between 100 and 200 samples for this small (but interesting) region of the curve, which was between a quarter and a half of the internal memory capacity; this setup allowed us to have a reasonable sample distribution along the curve.
2.4. Modular Platform Used
A modular platform was designed and used to help place the cell and the illumination LED board. The design was made using Autodesk Fusion 360 and then 3D-printed using fused filament fabrication (FFF) technology. In
Figure 13, two configurations of the platform can be seen—the base with the adapters for the (156 × 156) mm cells and the supporting rods in (a); and with the adapter for the LED illumination board used in (b). Bigger cells, up to M6—(166 × 166) mm—are possible with this design. For future trend sizes, such as M8—(182 × 182) mm—or M10—(210 × 210) mm—a redesign of the platform will be needed. A picture of the prototype can be seen in
Figure 14 along with the
I-V tracer device.
PV cells and LED illumination.
The characteristics of the PV cells used for testing are in
Table 1. Busbars were hand-soldered to the cells using a soldering iron with the help of flux and hot air at 150 °C (see
Figure 15a). The four busbars were then connected using a wider bar, which offered a low resistance path for the current and an easy zone to solder the voltage and current cables. Three cables were soldered at different points of each side (positive and negative) from the cell to the device to ensure the current flow with the lowest resistance possible. Another cable was soldered on each side for the voltage measurement.
The illumination system was composed of an aluminium PCB with 42 infrared (IR, 850 nm) LEDs—see
Figure 15b. This wavelength was chosen because the photon absorption curve for a silicon PV cell had its maximum efficiency in the near-infrared (NIR) zone, as shown in
Figure 16. When these photons illuminating the cell are at their peak wavelengths, they could absorb better, so less energy is needed to obtain a state at the cell similar to the nominal conditions (1000 W/m
2 with the spectral composition of the Sun’s irradiance at Earth’s surface). Under these irradiation conditions, the PV cell can generate the free charges needed to reach its saturation current and, consequently, walk around its own
I-
V curve. The calibration of the current needed on the LEDs for obtaining the right density of photons was conducted with a calibrated irradiation cell to obtain the same signal exposed to the Sun at nominal conditions.