Estimation of SMPS’ Conducted Emission According to CISPR Standards

Abstract

Switched-mode power supplies are very efficient and commonly used components in products nowadays. However, due to currents switched at a high frequency, the conducted emission test is a high concern for designers. The market is increasingly demanding in terms of the size of the components and their efficiency. In order to meet market requirements and reduce the size of the power supply (both built into the product or standalone), the switching frequency of the SMPS is rising; hence the base frequency and its harmonics cover a frequency range of the conducted emission test. Due to this fact, the estimation of the test result becomes a great concern for the designer. This paper describes the approach that one can utilize to estimate the switched-mode power supply’s conducted emission as a standalone component with simulation tools using only the power supply being designed. The workflow, which is the result of this work, can be utilized in order to optimize the design of power suppliers from the conducted emission perspective.

1. Introduction

Currently, as electronic products have to be more and more efficient, EMC performance is one of the key factors in the design of electronic devices. The possibility of reducing big-sized components such as chokes, capacitors, and filters are the current design goals. This gives the designers a chance to reduce the price of the device and the weight, which can be crucial when the device has to meet transportation cost requirements where the mass of the device plays a significant role, for example, environments at extremely high altitude, space, or deep underground.

Estimating the switched mode power supplies’ conducting emissions is crucial for overall product performance [1]. Normally, in order to estimate the performance of a solution, the prototype has to be produced and measured; this means that in order to choose the best solution from a few of them, each has to be produced [2]. However, nowadays, there are approaches to estimate conducted emissions using 3D modelling methods. This topic is widely described within the literature [3,4,5] with different approaches. Because of this reason, authors of recent publications incorporated 3D simulation tools in order to include layout in the conducted emission prediction. Furthermore, this method has been proven to work for layout improvement during the early stage of the design [6].

Unlike the industries in environment and consumer electronics, where obtaining the required qualification certificate based on testing of the final product is the standard, most tests are performed at the component level in the automotive industry. This approach ensures that the highest quality requirements are met at the component level. Only then, having information about every component, are final product-level tests performed. In the case of component-level testing, the proposed approach can be utilized to replace real tests and, in effect, a reduction in time to market can be achieved in addition to money saved on testing.

In this work, the authors verified the proposed workflow using two solvers. The motivation of this work was due to the fact that implementation of these kinds of solvers (full wave or quasi-static) in software requires a lot of effort; hence, the results of this paper can provide a guide for solver selection. If one decides to use commercially available software, the results of this work can guide which solver should be implemented.

2. Materials and Methods

2.1. General Method Description

For this paper, the authors decided to use the approach found in the literature [6] and introduced necessary changes to meet the requirement to obtain the conducted emission estimation according to the CISPR 16-2-1 [7]. Based on the work proposed by authors of [6], in order to estimate the conducted emission of a component, general workflow (Figure 1) can be defined using the parts listed below:

• Selected electric components located on PCBA,
• Layout,
• Electric model of the LISN.

The authors of this paper found that the proposed approach is sufficient in terms of different layout solutions comparison; however, in order to estimate the conducted emission value per CISPR 16-2-1, the complete test setup should be included in the simulation model. According to the CISPR 16-2-1 standard, the complete test setup (Figure 2) should include:

• LISN,
• Ground reference plane,
• PCBA,
• Harness.

The authors of this paper, based on approach [6], defined a modified version of the workflow (Figure 1) and added the required steps in order to include all the necessary components required by the CISPR 16-2-1 standard. The proposed workflow is presented in Figure 3.

In general, changes introduced according to the workflow from Figure 1 are:

• The Q3D extractor is replaced by a 3D extractor tool which makes workflow more generic,
• An added step for the test setup of S-parameter extraction, which allows performing an estimation compliant to CISPR 16-2-1.

In the next section of this paper, the results will be presented and verified with the real measurement. For the 3D extractor tool, the authors used two different solvers (ANSYS Q3D and ANSYS HFSS).

A decision about proceeding with any of those two solvers should be based on computing requirements and the time required to extract models. In general, a full-wave solver should produce more precise results for a high-frequency band (where the length of the object is smaller or comparable with the wavelength) than a half-wave solver. The drawback of its use is the requirement for more computational resources (memory and time).

2.2. Studied System

2.2.1. Two-Switch Forward Converter

The base for this study was the two-switch forward converter [8]. The general concept of the topology is presented in Figure 4. In these kinds of electronic circuits, the high-frequency switching currents effect electromagnetic compatibility, which is a deep concern. Due to the fact that SMPS modules supply other devices in the system, which can work as antennas and emit noise coming from the SMPS, those modules should be designed with an appropriate margin in terms of emissions.

The exact description and principle of the work of the two-switch forward converter can be found in the literature [8]. For this study, it is essential to define two working cycles presented in Figure 5.

The first cycle (a) is when the transistors (M1 and M2) are in the conducting state and current flows through them and through the transformer. When the cycle is switched to (b), transistors are in the non-conducting state, and current loops are closed by the two diodes (D2 and D3). From the EMC performance, the C1 capacitor is essential. It should be able to store enough energy so that the AC current will not be drawn from the power supply. Otherwise, the conducted emissions will be high. The inductances of the traces, due to the size of the physical module, are also a concern and should be taken under consideration when the physical layout is performed. The design of SMPS is always based on decisions and risk minimization. The components have physical dimension and pins that connect it to the layout. The shapes of the components and pins create “keep out” regions that prevent designers from achieving perfect layout proposed in application notes or technical datasheets of the components. Due to this fact, using the approach proposed by the authors, one can verify if the design of the module meets the design criteria from the conducted emission perspective.

In this paper, it has been assumed that in order to obtain satisfactory results in terms of conducted emission estimation, it is enough to focus on components related only to the two current loops shown in Figure 5. According to the previous statement, the electrical model of the SMPS has been built in the ANSYS TWIN BUILDER environment, which is presented in Figure 6.

In order to estimate conducted emission accurately, the electrical models of the components have to represent both static and dynamic behavior. As the time-domain simulator used to solve the conducted emission problem was the Twin Builder from ANSYS, all models used were compatible with this software. It is worth noting that all information required for the model preparation was found in each component’s datasheet, except for the Ferrite Bead model of which the parameters were provided by the supplier. It is important to keep in mind that model creation is the key part of the process. The authors took the approach that, once the first electrical simulation has been prepared and verified, then the electrical model is extended by adding the components required for conducted emission estimation. During the second stage, no further changes to the electrical models were introduced. A series resistance of the capacitors and inductors were added to the electrical simulation, and those values are added as separate components.

2.2.2. Test Setup with Ground Reference Plane and Harness

According to Figure 2, the complete test setup should consist of LISN, ground reference plane, harness, and DUT. For this purpose, the model of this test setup was prepared using the ANSYS HFSS tool and is shown in Figure 7.

It is worth noting that DUT on this level is only the place where the electrical signals will come in and out. The physical layout of the SMPS will be extracted on a separate level. It was decided to take this approach for an important reason. In order to make the simulation run with the minimum required time and computing resources required, it is beneficial to follow the submodeling approach. This approach induces that if the system consists of small and large components (when compared with each other), the system should be divided into submodels where each submodel is meshed with mesh of a similar size. In cases where the test setup and layout system were to be extracted immediately, there would be regions with very dense mesh layout with respect to the rest of the system. This situation could lead to a very large number of mesh elements and increase computing time significantly.

To properly extract S-parameters for cables used in the analyzed model, an additional third conductor is added. This conductor is a continuation of the LISN reference plane and, on the second side, it is terminated with a plane simulating the presence of DUT. This plane is also on the same potential as the LISN reference plane. Ports connected to the DUT end of cables are terminated to that plane. This approach was used because if the DUT side ports were terminated to a floating object, then the calculated S-parameters would not be correct due to the lack of a reference and current return path. This approach is also limited to the orientation of the additional reference conductor in space relative to the actual DUT conductors. The orientation of this conductor should be as similar as possible to the actual mutual spacing between the DUT conductors, which is the case in this work. S-parameters were not extracted for additional reference conductors. The impedance diagram of the modeled system for harness parameters extraction is shown in Figure 8.

A detailed model of this approach is shown in Figure 9. The terminal ports were marked in yellow. With the approach shown in Figure 9, it was possible to extract parasitic parameters of both the positive and negative potential wires. The cross-section of wires that were modeled is shown in Figure 10. The parameters were extracted for the following broadband solution: 1 Hz for low frequencies and 100 MHz for high frequencies, with 2700 points for which the S-parameters were calculated. The mesh size was set to default settings to allow the algorithm to choose the proper mesh size according to the solution frequency.

However, The LISN on this level of simulation is represented by only the metal housing that is part of the main current loop and electrical model, shown in Figure 11, of the real device that will be included in the electrical level of simulation. LISN_P and LISN_N are the positive and negative supply outputs of the LISN, while V_EMI_P is the node which the conducted emission will be calculated from.

2.3. The Layout of the SMPS

Within this work, it has been assumed that it is sufficient to model layout traces related only to the current loop of primary winding shown in Figure 5a,b. The reason for this approach is that most of the conducted emission results caused by the currents on the secondary side of the transformer are coupled through the transformer back to the primary side. This assumption is correct as long as the layout of the secondary side is capacitively decoupled from the primary side.

For the purpose of this work, two different 3D extracting tools were used and the results were compared with the following measurement: ANSYS Q3D and ANSYS HFSS.

2.3.1. ANSYS Q3D

ANSYS Q3D [9] is a half-wave parasitic RLC extractor that can compute capacitance, inductance, and resistance matrices for AC or DC problems. It uses the finite element method to model current flow within conductors (DC resistance problems) and the method of moments to solve inductance and capacitance problems. Since Q3D uses Maxwell’s equations simplification called quasi-static approximation, it assumes that the dimensions of the analyzed structures are small in comparison with the wavelength at the maximum frequency of analysis. Capacitance is extracted from the charge solution, DC resistance is extracted from DC conduction solution, and AC/DC inductance and AC resistance are extracted from the field solution. Afterwards, the ODB++ file was imported to the ANSYS Q3D software as a 3D model (shown in Figure 12). Then, nets were identified based on the previously chosen high-frequency current loop shown in Figure 5a,b. Nets are single pieces of conductors (whole traces or divided traces) for which parasitic RLC parameters were identified. The rest of the 3D model, not considered to be part of that loop, was removed from the analysis to prevent influence on the results and save the simulation time.

Once the nets were identified, ports (sinks and sources) for each net were assigned based on the supposed current flow direction. Sinks and sources assignment is necessary to have full RLCG matrices calculation. For capacitance and conductance matrices, Q3D applies 1 volt to a single conductor and 0 volts to all other conductors. For resistance and inductance matrices, Q3D applies 1 amp to a single source and 0 amps to other sources. Resistance matrices are calculated based on ohmic losses (skin effect and mutual resistances are considered in the AC solution).

The basic principle of Q3D simulation is the fact that the charge at infinity is assumed to be zero. This can be changed by “float at infinity” reduction which causes potential at infinity to float and enables the use of the local ground plane. Since there is no evident reference net in 3D SMPS layout model, it was decided to treat all the nets as signal nets and compute RLGC matrices for all of them, without indication of reference/GND net and use of “float at infinity” reduction.

Since one path on the layout can be connected to multiple elements (e.g., the path between the ferrite core and upper MOSFET transistor is also connected to the filtering capacitor), original paths were divided into sections (Figure 13) to be able to extract parasitic RLCG for relevant traces. Then, those divided paths were assigned nets, sinks, and sources before being connected back to the time-domain electrical simulation.

An interpolating sweep between 0 Hz and 100 MHz was chosen for analysis, while the solution frequency (solution for which the mesh is calculated) was chosen to be 1 GHz. It is worth noting that proper frequency range of the analysis should be chosen. In the case of the Q3D solver, for the low-frequency model, the starting point should be 0 Hz. The analysis end frequency—100 MHz—gives enough margin since the final emission analysis is done in the frequency range 9 kHz to 30 MHz. Error tolerance was set to 0.01%. The mesh size was set to default settings and is shown in Figure 14. An interpolating frequency sweep was used instead of a discrete frequency sweep because it estimates the solution for the entire frequency range and reduces the time required to calculate the parameters. The software uses frequency points in which the field solution is solved so that the entire interpolation solution is within the tolerance specified. It avoids solving solutions at each frequency point as it is done in a discrete sweep, which makes simulation converge in much less time. Full-field solution is saved only for the final point of the sweep, but RLGC matrices and S-parameters are saved for every solved point.

2.3.2. ANSYS HFSS

ANSYS HFSS [10] is a full-wave solver which considers mutual coupling between magnetic and electric fields. It considers all relevant magnetic phenomena connected to Maxwell equations, but the analysis can be more time-consuming than with Q3D. It uses the finite element method to generate an electromagnetic field solution. In this method, the area of the solution is divided into smaller regions called tetrahedra (finite element mesh). Then, fields in those subregions are estimated by local basis functions. Structures within the model are excited through ports, with field patterns that can originate from transmission lines of the same cross-section as the port. Finite element mesh is firstly created and refined for an adaptive solution frequency; also, the field solution is primarily computed for that frequency. Then, this mesh is used for the interpolating frequency sweep, which estimates solutions in the whole frequency range of interest. Frequency points at which field solutions are solved are chosen by HFSS software so that the entire interpolated solution is within the error tolerance specified by the user. During the solution process, S-parameters [11] are generated and saved for every frequency point. A driven terminal solution is used to calculate the S-parameters based on terminals. The S-parameters’ matrix is then expressed in terms of voltages and currents on the terminals. The layout that the authors worked with was lacking any plane that could be used for reference plane purposes. To overcome this problem and extract parameters of the layout with a full-wave solver, the authors of this publication added the artificial REF plane to the model at a distance of 20 mm (Figure 15) from the layout. According to the equation 1 and equation 2 from [12,13], a higher distance from the conductor to the reference plane means that the characteristic impedance is also rising. In order to replicate the lack of a reference plane in the real layout, the 20 mm distance of the reference plane to the layout traces were arbitrarily chosen so that the characteristic impedance of a 1 mm trace is 300 Ohm—which is considered to be a high enough value that all positive aspects of having a reference plane can be neglected. The transformer was modeled as a perfect conducting plane TR (Figure 15) with two ports. The shape of the plane is exactly the same as the shape of the real transformer. For simplicity of the analysis, it was assumed that secondary currents of the transformer flow to the reference plane REF (Figure 15).

$${\in }_{eff}=0.475{\in }_r+0.67,$$

(1)

$$Z_0=\frac{60}{\sqrt{{\in }_{eff}}}\ln \frac{5.98h}{0.8w+t},$$

(2)

where:

• $w$ is the trace width,
• $h$ is the trace height,
• $t$ is the trace thickness,
• ${\in }_{eff}$ is the effective dielectric constant,
• $Z_0$ is the characteristic impedance,
• ${\in }_r$ is the dielectric of the material.

Next, the traces associated with the current loops of primary winding shown in Figure 5 were divided into sections with two ports on each section. This limitation comes from the methodology of how S-parameters are calculated. The view of the ports, layout, and reference plane model is shown in Figure 16.

The solution parameters were set accordingly:

• Solution frequency 5 GHz,
• The mesh size of the model was set to default setting so the algorithm can adapt the mesh size to the solution frequency, Figure 17,
• Interpolating sweep from 10 kHz to 100 MHz with 2401 calculation points.

2.3.3. Submodels

As the result of both HFSS and Q3D extraction processes, the S-parameter [11] submodels were created. This approach treats the network as a two-port circuit. Only the port variables are considered, which are input and output voltage currents. During HF circuit characterization, those parameters relate to incident, reflected, and transmitted voltage waves after the insertion of a two-port network into a transmission line. Incident waves can be injected into any of the two ports, and they give rise to reflected and transmitted waves. S-parameters are calculated on the basis of incident and reflected waves; they define waves reflected from a particular port in which an incident wave is applied. Those submodels’ bases were used as an input into the TWIN Builder tool, which includes S-parameters calculated on the base of Q3D and HFSS simulations. For the Q3D simulation, sinks and sources in the simulation are converted to the Twin Builder component based on extracted S-parameters. In the case of HFSS, the ports for the S-parameters were calculated and translated into the appropriate dynamic components in Twin Builder.

2.4. Time Domain Simulation

Eventually, the TWIN Builder model consisting of the LISN model, HF cable model, layout dynamic components (HFSS or Q3D based), and passive and dynamic components was used for simulation. The complete simulation components are shown in Figure 18 for the HFSS approach and Figure 19 for the Q3D approach. After the simulation reached a steady state, the 10 ms portion of the signal from the V_EMI_P node was used to calculate FFT with the following parameters: sample size of the analyzed signal $N$ is equal to 1,000,002 points, lowest analyzed frequency $f_l$ is equal to 4500 Hz (which reflects half the RBW of the measurement), highest analyzed frequency $f_h$ is equal to 30 MHz and the sampling frequency $f_s$ is equal to 100 Mhz. Calculating the criteria $k_f\le \frac{N}{2}$ and $\frac{2}{N}\le \beta \le 1$ from [14] yields that FFT parameters are correct, where:

• $k_f=\frac{f_h}{f_l}=6.67\times {10}^{-3}$,
• ${\beta }_{max}=\frac{f_s}{f_l\ast N}=0.0222$,
• ${\beta }_{min}=\frac{{\beta }_{max}}{k_f}=3.33\times {10}^{-6}$,
• $\frac{2}{N}=2\times {10}^{-6}$,
• $\frac{N}{2}=500,001$.

The simulation integration time was set to a fixed value of 10 ns, which allows having results up to 50 MHz.

3. Results

The results obtained for the HFSS approach are shown in Figure 20, while those obtained using the Q3D approach are shown in Figure 21.

In order to verify the results, the real measurement was conducted. The test setup according to the CISPR 16-2-1 shown in Figure 22 was reproduced in the laboratory. Instruments that were used for measurement are shown in

Table 1. Devices used for conducted emission measurement.

Device Type	Device Part Number
LISN	Schwarzbeck NNLK 8121 RC
EMI Receiver	Rohde & Schwarz ESR7
Power Supply	LAB/HP51500 0–1500 V/0–4, 7 A
Load	20 Ohm Resistor

.

Figure 23 shows the result of the measurement in the laboratory conditions of the real sample using devices listed in Table 1; the software that was used was the EMC32. The parameters of the measurement are presented in

Table 2. Parameters of the measurement set in EMC32 Studio.

Parameter	10 kHz–150 kHz	150 kHz–30 MHz
RBW	200 Hz	9 kHz
FFT method	YES	YES
Dwell time	50 ms	50 ms
Detector	Peak and Average	Peak and Average

. It should be noted that chosen dwell time is longer than the minimum single frequency measurement time specified by CISPR 16-2-1. Single sweep in this case is sufficient to capture continuous, narrowband signals that are present in the EUT emission spectrum. In Figure 24 and Figure 25, the comparison of estimation and measurement is shown.

4. Discussion

Even though results obtained by the simulation are close to the real measurement, some differences can be observed. The source of those differences can come from:

-

Layout model has been simplified with respect to the original layout,

-

Electrical simulation was simplified.

When the proposed approach is implemented, the required level of simplification of the design should be considered in order to obtain the desired results. When the level of simplification will be too low, hence the analyzed model too complex, the computational requirements (RAM, CPUs, computing time) cannot meet actual resources available to the engineer. Due to this fact, before the implementation of the workflow, the right simplification strategy should be defined. This strategy should be carried out based on engineering judgment and should take into consideration:

• $\frac{\mathrm{d}i}{\mathrm{d}t}$ current loops,
• $\frac{\mathrm{d}V}{\mathrm{d}t}$ areas,
• Layout critical areas that can be the source of a concern.

On the other hand, when the simplification will be too high (model will not be detailed enough) the results may not meet the requirements.

Table 3. Areas of the model simplification and its effects.

Area	Simplification Level	Resources Required
Layout	Low	High amount of memory, CPU, comp. time
Layout	High	Low amount of memory, CPU, comp. time
Electrical simulation	Low	High amount of comp. time
Electrical simulation	High	Low amount of comp. time

summarizes the simplification effects and areas of their impact.

The engineer’s goal should be to determine the point at which the model not too complex and still include all parts related to phenomena that are crucial for the final result. In general, complex and detailed models give more precise results but require a lot of resources while simplified models can be used for rough solution estimation when resources are not available.

The results obtained by the authors, when compared with the measurement, show yields that in the proposed approach, from the accuracy standpoint, can be used for both:

• New design optimization treating the result as comparable with laboratory measurements,
• Design optimization procedure by comparing two or more potential solutions and choosing the best performing one.

As the conducted emission estimation using the proposed setup relates directly and only to the results obtained by the time-domain simulator, a few points need to be considered.

Electrical models: the authors of this work prepared electrical models based on datasheet information. Neither of the active components were modeled using general library components. This part of the analysis is crucial for the final result and played a major part in the work. All details of the parameters not shown on the schematic can be found in Appendix A.

Mesh size: during the work, the authors found that solution frequency (hence mesh size) has a big impact on the result. Due to this fact, for the layout models where HFSS and Q3D tools were used, the solution frequency was set to a relatively high value. If computational capabilities would be limited, the proper approach should be taken for proper mesh size definition.

Complexity of the design: from the workflow perspective there is no direct limitation of the complexity of the device being studied. However, in the case where multiple component system analysis should be performed, the best approach is to divide the system into single components and analyze them separately. This approach will assure that each of the components fulfill the EMC criteria. Eventually the system is built from validated components using the proposed workflow. This approach follows the idea of dividing the big analysis into smaller pieces and prevents from running out of resources and the need for extremely high computational time, when analysis is being performed.

Maximum frequency of the analysis and the equivalent circuit: authors of this work used two solvers, quasi-static and full wave, and eventually results were compared. This decision was based on commercial information about software capabilities:

• Quasi-static solver is capable to reproduce phenomena in structures up to $\frac{\lambda }{10}$, where wavelength ($\lambda$) for 100 MHz signal is 3 m,
• Full wave solver is suitable for phenomena related to structures of size $\frac{\lambda }{2}$ or even smaller.

The results obtained in this work show that both solvers are accurate enough in order to extract accurate equivalent circuits for conducted emission estimation purposes.

One of the most important factors that can have significant impact on the result is the submodels. During creation of them it should be taken care that they reflect the behavior of the layout in frequency range according to the time domain simulation with low error. As a general rule, the submodels, when created, should contain as much as possible both low- and high-frequency range margins. This will allow one to exclude any issues related to this part of the work. In the following cases, the submodels frequency ranges should be restricted: when analysis using the submodel in time-frequency domain analysis takes more time than is acceptable; or when time or memory resources required for extracting the submodel parameters from the 3D model (both full wave or quasi-static) are not acceptable.

According to knowledge of the authors, it is the only workflow presented in literature verified according to CISPR 16-2-1 standard. The other results presented in the literature could be based on other time-domain parameters, which are not always known and presented, and could affect the results. Because of this fact, it is impossible to compare obtained results in this work with results from other authors.

5. Conclusions

The authors of this paper presented a validated approach for conducted emission estimation according to the CISPR 16-2-1 standard using two approaches of extracting equivalent circuits. The results obtained allow us to successfully analyze the performance of the SMPS modules from a conducted emission perspective. Two approaches that deliver similar results and are based on the needs of the engineer can be used with success. The proposed approach, if used, may ensure that the module implemented in the final product is optimized from the conducted emission perspective and fulfills the requirements according to the international standard. This approach allows significant reduction in the number of tests and number of prototypes and may be sufficient to eliminate the requirement of performing tests at all. The next steps of this work would be to include more layout components such as gate drivers and secondary circuits in order to obtain even more precise results.