Frequency-Modulated Antipodal Chaos Shift Keying Chaotic Communication on Field Program Gate Array: Prototype Design and Performance Insights

Abstract

Using chaos for communication can provide more robust channel security, covert transmission, and inherent support for spread-spectrum modulation. Although numerous studies have explored this technology, its practical deployment remains limited due to substantial hardware demands, complex signal processing, and a lack of efficient modulation methods for chaotic signals. In this study, a novel chaotic digital communication system is proposed and studied. A prototype of a frequency-modulated antipodal chaos shift keying (FM-ACSK) system is implemented on an Intel Cyclone V field-programmable gate array (FPGA) along with a complete mathematical model using Matlab R2022a Simulink software. Using FPGAs to implement chaotic oscillators avoids analog system problems such as component drift and high thermal instability while providing determined system parameters, rapid prototyping, and high throughput. The employment of FM over a chaotic modulation layer provides a passband operation (currently at an intermediate frequency of 10.7 MHz) while adding the benefits of carrier frequency offset robustness and constant signal envelope. Within this study, the robustness of FM-ACSK to white noise in the channel was evaluated using bit error rate, which was tested through hardware experiments and simulations. The results show the feasibility and potential performance limitations of this approach to chaotic communication system design.

1. Introduction

The demand for secure communication systems has grown exponentially in recent decades. This surge is driven by the critical role of telecommunications in global connectivity and the increasing prevalence of devices in the Internet of Things (IoT). Secure and robust data transfer has become essential, especially considering growing cyber threats and privacy concerns. Traditional methods of ensuring secure communication often rely on encryption techniques, which can be vulnerable to advances in processing power, such as those provided by quantum computing. Encryption typically covers higher protocol layers, leaving the physical communication layer relatively unprotected. This is where chaotic communication can provide a promising avenue, leveraging the inherent unpredictability and nonlinearity of chaotic signals to enhance security and mitigate eavesdropping risks.

Chaotic systems possess distinctive characteristics that make them suitable for secure communication [1]. Their nonlinear, ergodic, and noise-like behavior ensures unpredictability. Their sensitivity to initial conditions and deterministic nature provides inherent encryption capabilities, adding complexity for intruders attempting to synchronize or decode the system without precise parameter knowledge. These systems also exhibit low autocorrelation, low inter-signal correlation, and a wide bandwidth, further reinforcing their potential as secure communication carriers with resilience to interference, providing some level of enhanced physical link security for wireless data transmission.

To translate theoretical advancements into practical applications, the hardware implementation of chaos oscillators must be considered. The traditional implementation of chaos oscillator involves an analog electronic circuit (e.g., Chua’s circuit [2], Rössler circuit [3], Colpitts oscillator [4]), which is a feasible and simple way to generate chaotic dynamics. However, the use of analog chaos generators in communication systems poses challenges, including component value drift caused by temperature, humidity, supply voltage fluctuations, and other environmental or operational factors. Even the slightest change in the resistance or capacity of elements will lead to different behaviors of the chaos dynamics. These parameter variations during operation are difficult to compensate for, complicating chaotic synchronization, which requires two chaos generators with identical parameters and proper coupling. Moreover, analog chaos generators lack control over their initial state. As the chaotic oscillator system can be described by a simple system of ordinary differential equations (ODEs), solving these equations in a discrete, digital form is another viable option. This can be carried out on any computer, but a much more efficient solution to this task can be provided by such a digital hardware platform as a field-programmable gate array (FPGA).

FPGAs combine flexibility, high computational power, and robust real-time processing through pipelining, making them ideal for advanced digital signal processing tasks. Their capability to synthesize fully deterministic discrete chaos generators eliminates component drift issues while addressing stringent performance and resource constraints. Additionally, their reconfigurable nature enables rapid prototyping with hardware description languages and potential adaptability to evolving communication standards, positioning FPGAs as a powerful platform for secure chaotic communication system implementations [5,6].

As FPGA technology becomes increasingly available for prototyping and deploying digital systems, this has led to a renewed interest in chaotic systems, given the potential for efficient digital realization. However, this approach also has several design challenges that require addressing, such as the efficient utilization of FPGA hardware resources and optimization for stable performance at higher clock speeds. Since the chaos implemented in the FPGA itself is discrete in nature, careful consideration must be taken of the width of the data bus in the fixed-point (sometimes floating-point) data format as well as methods for solving discrete ODEs. These choices affect the accuracy of the computation as well as the robustness and properties of the chaotic signals in the system, which may be critical for the system’s performance quality.

Two types of chaotic communication systems can be pointed out—those with coherent and non-coherent detection [7]. Coherent systems (such as chaos shift keying (CSK) [8]), which require chaotic synchronization between the transmitter and receiver, excel in privacy but demand precise parameter matching, as stable chaotic synchronization in the presence of channel noise is a challenging task. Non-coherent systems, on the other hand, simplify receiver design at the cost of reduced security. Non-coherent chaotic communication systems (such as differential chaotic shift keying (DCSK) [9]) are more popular, but they mainly use nonlinear wide-band properties of the chaotic signals for communication purposes. As they do not use chaotic synchronization, they do not need any chaos generator at the receiver.

Key challenges in chaotic secure communication include achieving stable synchronization, particularly in coherent systems, and mitigating parameter mismatches between the transmitter and receiver. The trade-off between the security of a chaotic communication channel and its robustness to noise is another challenge that needs to be addressed in the design. The predictability of chaos and simplicity of non-coherent communication schemes weaken the security of the system, while the increased complexity of the chaotic system risks making it less resilient to the channel noise and interferences. The search for new, more efficient and viable chaotic modulation methods is a relevant task and a necessary step to allow secure chaotic communications to become more popular among other communication methods.

While the topic of chaotic secure communications has been of interest to researchers for about three decades now, this subject is still vastly understudied. This could be related to the increased complexity of chaos theory and to the low popularity of chaotic communications in comparison to conventional communication systems. As scarce as this area of research is, the use of FPGAs to implement chaos generators has been gradually increasing in recent years. For instance, Nuñez-Perez et al. [10] proposed an FPGA realization of an image encryption system that employs 16-Chaotic Phase Shift Keying in a coherent communication scheme. A similar approach was used in the work of Estudillo-Valdez et al. [11], where the authors effectively deployed an FPGA realization of an image encryption scheme using DCSK chaotic modulation together with the code division multiple access (CDMA) technique for multichannel communication. In another study, Bonny and Al Nassan [12] addressed several challenges of cascaded chaos-based secure communication systems, while analyzing the security and efficiency of an FPGA-implemented system with various cascade levels. Karagiorgos et al. [13] focused their research on a novel digital chaotic encrypted communication scheme, which was implemented both in an FPGA and as software on the ESP32 Arduino platform. These studies, published in 2024, highlight the growing interest in and successful applications of FPGA technology for chaotic encryption and secure data transmission. Regarding earlier research on FPGA-implemented chaotic communication systems, only a limited number of relevant papers [14,15,16,17,18,19,20] have been identified. Some design parameters of these works were reviewed and compared in our previous study [21].

Table 1. Overview of design features in FPGA-based chaotic communication systems.

Paper	Chaos Generator	ODE Discrete Solving Method	Chaotic Synchronization Method	Modulation	Passband Method	Symbol Timing Recovery Method	Data Rate
[10]	various	not mentioned	Hamiltonian	16-CPSK	not present	separate signal channel	20 kbps
[11]	van Wyk	RK-4 1	none	DCSK-CDMA	not present	correlation	not mentioned
[12]	authors’	RK-4	not mentioned	chaotic masking	not present	not present	not mentioned
[13]	authors’, nonautonomous digital	not applicable	direct coupling	chaotic encryption	not present	not present	not mentioned
[14]	modified Chua	Forward Euler	Pecora-Caroll	authors’, digital algorithm	not present	not present	not mentioned
[15]	Lorenz	not mentioned	fuzzy controller	chaotic masking	not present	not present	not mentioned
[16]	authors’	Forward Euler	Hamiltonian	chaotic masking	not present	separate signal channel	not mentioned
[17]	authors’ and Sprott	not mentioned	none	COOK 3	not present	correlation	not mentioned
[18]	Rössler	Forward Euler	Pecora-Caroll	chaotic masking	not present	not present	not mentioned
[19]	Sprott	Forward Euler, trapezoidal, RK-4	Pecora-Caroll, Hamiltonian, OPCL 2	chaotic masking	not present	not present	not mentioned
[20]	authors’	Forward Euler	Hamiltonian	chaotic masking	not present	not present	not mentioned
present	modified Chua	Forward Euler	error linear feedback	FM-ASCK	FM	modified early–late gate	6.1 kbps

¹ Fourth-order Runge–Kutta; ² Open-Plus-Closed-Loop; ³ Chaos On-Off Keying.

provides an overview of the design features of the reviewed FPGA-based chaotic communication systems. Notably, the FM-ACSK system stands out as the only design with passband operation capabilities. Additionally, the symbol timing recovery feature (detailed in Section 2.3) is absent in the other reviewed coherent systems or relies on a separate signal channel—a solution that is impractical for wireless communication. For the two non-coherent systems that do not use chaotic synchronization, symbol timing depends on directly observing the output correlation in the demodulator. However, in the presence of channel noise, these systems would require additional signal processing to achieve reliable symbol timing. Unfortunately, some parameters and features are not mentioned within the reviewed papers, which complicates the comparison.

Most of the mentioned studies focus on integrating chaotic communication with image encryption schemes, relying on non-coherent chaotic modulation or the simplest form of coherent modulation, chaotic masking. In chaotic masking [7], the information signal is directly added to the chaotic carrier signal for obfuscation. While chaotic masking benefits from design simplicity, it suffers from low noise robustness and limited security compared to more advanced CSK modulation.

CSK-based implementations, however, remain rare due to historical challenges. In analog-based systems, utilizing CSK in wireless communication has proven difficult because of the inherent sensitivity of chaotic synchronization. Achieving synchronization ideally requires the use of identical chaos generators, which is unattainable with analog components. Furthermore, CSK systems require four chaos generators, which can be a disadvantage in terms of energy consumption.

Despite these challenges, we are confident that CSK holds significant potential for secure and reliable chaotic communication. By leveraging FPGA technology for implementation, identical chaos generators with fully controlled initial conditions become achievable, fundamentally transforming the possibilities for coherent chaotic systems in general and CSK-based designs in particular. This advancement paves the way for experimental exploration of CSK-based systems’ potential in practical applications. As an initial step, new FPGA-based chaotic communication system designs should be proposed, developed and tested.

The proposed coherent digital chaotic communication system is based on frequency-modulated antipodal chaos shift keying (FM-ACSK) modulation and shows a new approach to FPGA usage for chaotic communication design. By leveraging frequency modulation, the system enhances robustness against carrier frequency offsets and channel nonlinearities while providing improved control over signal bandwidth and maintaining a constant envelope [22].

This work builds upon our previous research [21], which introduces an ACSK-based chaotic digital communication system model implemented on an FPGA. The present study incorporates significant modifications and additions, including frequency modulation and a complete FPGA experimental setup, to advance the system’s performance and verification capabilities.

The novelty of the proposed FM-ACSK system lies in its effective combination of frequency modulation with the unique properties of chaotic signals, which is an underexplored area in science. Implemented on an FPGA platform, the system delivers high-speed processing and flexibility for reconfiguration. Additionally, a validated Simulink mathematical model of the system’s digital components was developed to facilitate performance comparisons between the FPGA prototype and the system’s simulation. The proposed system is designed as a proof-of-concept, demonstrating its feasibility for enhancing the security of the physical layer in IoT and wireless communication networks. The performance of the prototype and Simulink model is evaluated, with the system’s noise immunity assessed in an additive white Gaussian noise (AWGN) channel using bit error rate (BER) analysis. The key contributions of this study include the following:

• Development of a digital FM-ACSK communication system featuring a modified Chua circuit chaos generator, error-feedback chaotic synchronization, and an FM-ACSK modulation scheme, all tailored for FPGA hardware implementation.
• Creation of a precise and verified Simulink mathematical model for the digital components of the communication system.
• Successful implementation and testing of the FPGA-based communication system, demonstrating practical feasibility and advancing the state of chaotic secure communication systems.

The remainder of the paper is organized as follows. Section 2 provides a detailed description of the FM-ACSK communication system, including its architecture and operational principles, as well as the FPGA implementation. Section 3 discusses the experimental setup for the system’s study and the results of the tests, demonstrating the system’s noise performance and robustness. In Section 4, the system’s performance and security aspects are discussed in a broader context, along with key conclusions and directions for future research. Finally, Section 5 provides brief conclusions.

2. FM-ACSK Communication System

This section describes the structure of the FM-ACSK communication system with the focus on the key parts of the transmitter and receiver. As this work is essentially a continuation of the previous research involving ACSK communication system development and evaluation, some core elements, namely, the chaos generator, chaotic synchronization method, and the ACSK modulation part, are similar to the ones used in the previous prototype described in [21]. Hence, these parts of the communication system will only be described here briefly.

The overall structure of FM-ACSK, which consists of a transmitter and a receiver, is shown in Figure 1. In the transmitter, binary data modulate the chaotic output “R_out” by passing it through directly or inversely, depending on the data bit value (the switch is regulated by a multiplexer with a register). This is why the ACSK modulation has “antipodal” in its name. The frequency modulation and demodulation ensure viable passband transmission of the ACSK-modulated signal and are discussed in more detail in Section 2.2. Once the retrieved ACSK signal is filtered from the channel noise, the chaotic demodulation begins. The signal is passed to both slave chaos generators in direct and inverted form. Depending on the prior inversion state of the ACSK signal, only one of the slave generators achieves chaotic synchronization. The synchronization errors, obtained by comparing the input and output of the slave chaos generators, are averaged and compared among themselves. The result signal of this comparison, which will be further referred to as “Δsync”, is used to decide the transmitted data bit value. Additionally, the symbol phase synchronization module ensures timing recovery for the transmitted bits.

To illustrate the ACSK detection principle, both the slave chaos generator’s synchronization errors are shown on Figure 2 for the “10101010” data bit transmission example, where the Δsync signal’s sign correlates with the values of the transmitted data bits.

2.1. Chaos Generator and Chaotic Synchronization

For the core element of the proposed communication system, the chaos generator, a fourth-order modified Chua’s circuit model is used. It is a relatively simple chaos generator, but it is rarely used. As we have investigated its properties in past studies [23], we chose to use it for this prototype as a well-known foundation that suits the present task.

The chaotic system is defined by the following ODE system:

$$\left\{\begin{array}{c}{\displaystyle \frac{d{p}_1}{dt}}=-g(p_1,p_3)-p_2\\ {\displaystyle \frac{d{p}_2}{dt}}=p_1+{\gamma p}_2\\ {\displaystyle \frac{d{p}_3}{dt}}=\theta \left(g(p_1,p_3)-p_4\right)\\ {\displaystyle \frac{d{p}_4}{dt}}=\sigma p_3\end{array}\right.,$$

(1)

where γ = 0.5, σ = 1.5, and θ = 10 are system parameters; p₁ … p₄ are the system state variables; and g(p₁, p₃) is a piecewise linear function, which is defined as follows:

$$g\left(p_1,p_3\right)=\left\{\begin{array}{ll}c\left(p_1-p_3-d\right)& \left(p_1-p_3\right)>d\\ 0& \left(p_1-p_3\right)\le d\end{array}\right.,$$

(2)

where c = 3 and d = 1. With such parameters, the present system exhibits chaotic behavior, which can be illustrated by the projections of the chaotic attractor (see Figure 3).

For digital implementation of this chaos generator in the FPGA, the forward Euler discrete integration method was used, which provides a simple, stable, converging solution of acceptable precision and low FPGA hardware resource usage. The chaos generator is implemented on a 14-bit singed fixed point numeric basis with 8 bits used for the fractional number part. This way, digital nets can represent numeric values from −2⁵ = −32 to 2⁵−2⁻⁸ = 31.99609375, with a precision of 2⁻⁸ = 0.00390625. For the chosen chaos generator, these limits are more than enough to represent all chaotic signal values within the generator. The precision is limited due to the limited number of DAC and ADC bits (14) by which the signal is transmitted and received.

After applying the forward Euler discrete integration method, the chaos generator equation system (1) can be rewritten as follows:

$$\left\{\begin{array}{c}{p}_{1_{n+1}}=p_{1_n}+h\left(-g(p_{1_n},p_{3_n})-p_{2_n}\right)\\ p_{2_{n+1}}=p_{2_n}+h\left(p_{1_n}+{\gamma p}_{2_n}\right) \\ p_{3_{n+1}}=p_{3_n}+h\theta \left(g(p_{1_n},p_{3_n})-p_{4_n}\right)\\ p_{4_{n+1}}=p_{4_n}+h\sigma p_{3_n}\end{array}\right.,$$

(3)

where h = (20 × 50 × 10⁶)/1024 is the discrete integration step size, which provides acceptable precision, and is suitable for simple FPGA implementation.

The chaotic output from the generator (see Figure 4) is composed of a weighted sum of all system state variables and the following piecewise linear function:

$$R_{out}={\mathrm{k}}_1{\mathrm{p}}_1+{\mathrm{k}}_2{\mathrm{p}}_2+{\mathrm{k}}_3{\mathrm{p}}_3+{\mathrm{k}}_4{\mathrm{p}}_4+g\left(p_1,p_3\right),$$

(4)

where k₁ = −2.6302, k₂ = −0.6054, k₃ = 0.5870, and k₄ = 0.7763.

The chaotic synchronization between the two modified Chua chaos generators is achieved using an error linear feedback method combined with a substitution of the piecewise linear function in the slave system. As shown in Figure 5, the master chaos generator outputs the weighted sum of all four state variables and the piecewise linear function, while the slave chaos generator uses only the sum of its four state variables, which is subtracted from the input. This way, the piecewise linear function information is reconstructed at the slave system and used to synchronize the state variables. The slave chaos generator outputs the weighted sum of the state variables and the absolute value of the recovered piecewise linear function. As per the nature of g(p₁, p₃), its values are above or equal to zero. Only when the inverted ACSK is passed to the slave generator is the recovered version of the piecewise linear function also inverted, with values below or equal to zero. If the piecewise linear function was recovered inversely, then the absolute value of such a signal will invert it again. When the input of the slave generator is subtracted from its output, the synchronization error signal is obtained.

2.2. Frequency Modulation

The ACSK-modulated signal is frequency-modulated using a digital modulator based on a numerically controlled oscillator (NCO) (see Figure 6). A Simulink-assisted design is used for fixed-point VHDL implementation using an HDL Coder toolbox. The passband frequency is 10.7 MHz, which is a typical FM intermediate frequency, and is sufficient for the prototype system’s testing purposes without the introduction of an actual wireless communication part. The chosen frequency can be easily combined with existing broadband FM radio modules and designs, which can be used for further tests in wireless connectivity. Also, this frequency is in a range that is well suited for generation on an FPGA with a 50 MHz clock, as it is close to half of the Nyquist frequency. With a frequency modulation index of 3 and an ACSK signal maximum noteworthy frequency of 215 kHz, the bandwidth of the FM-ACSK signal (according to Carson’s Rule) is 1720 kHz.

This digital FM system was specifically designed for working with a 50 MHz sampling clock, since the frequencies of all system signals are relative to the sampling frequency. The NCO uses 26 bits for the accumulator, 13 bits for phase quantization, and 13 bits for phase dithering. It ensures an output frequency resolution of about 1 Hz and a spurious free dynamic range (SFDR) of approximately 90 dB. The carrier increment sets the 10.7 MHz carrier output, while the deviation increment is used for scaling the ACSK output signal to achieve the desired deviation of 645 kHz.

The digital FM demodulator (see Figure 7) uses a 30-tap FIR Hilbert filter and a delay of corresponding length (half of the Hilber filter’s length plus its latency) to obtain the analytic signal from the noisy FM-ACSK input. Then, it is multiplied by a carrier generated by a similar NCO as the one used in the FM modulator. As a result, one part of the signal is shifted to the baseband, while the other is shifted to the double carrier frequency. A lowpass 100-tap FIR filter with an 860 kHz cutoff frequency removes the signal copy at double the carrier frequency, as well as part of the channel noise. The retrieval of the angle of the complex baseband analytic signal recovers the instantaneous phase of the modulated signal. The recovery of the modulating ACSK signal (instantaneous frequency) is performed using a simple two-tap difference filter, which additionally removes any DC bias (which depends on the carrier phase offset). Right after that, phase unwrapping is performed (when necessary) by adding or subtracting 2π if the signal value is below –π or above π, respectively. Hard clipping for signal amplitudes above the expected range (defined by the frequency deviation) is performed to protect the data from overflows in the presence of strong noise. At the end, the signal is amplified to the power level, which is close to the ACSK output power in the transmitter. Before passing the recovered ACSK signal to the ACSK demodulator, additional filtering is performed with a 215 kHz lowpass FIR filter to further reduce the impact of the channel noise.

2.3. Timing Recovery

Since the communication between the transmitter and receiver in real-world scenarios will have an undefined delay (depending on distance and other factors), the receiver cannot immediately know where a single transmitted symbol begins and ends (in the current system, there is one data bit per symbol). This problem is usually solved using a timing error detector (TED). TEDs detect and correct timing mismatches by evaluating the incoming signal and adjusting the receiver’s timing to align with the transmitted signal. Most common TEDs [24] include such decision-directed methods as Zero-Crossing and Mueller–Muller, and such non-data-aided feedback methods as Gardner and early–late gate. While decision-directed TEDs rely on estimated symbols and prior knowledge about data content, non-data-aided TEDs do not require any knowledge of the transmitted data; hence, they are more versatile for initial or blind synchronization.

These TED methods are mainly designed for conventional digital communication schemes. In the present chaotic digital communication system, the receiver can use information on the fixed symbol length (8192 samples at 50 MHz clock) and the nature of the Δsync (see Figure 2) signal at the output of the ACSK demodulator, which correlates with the values of transmitted data bits. This information is sufficient to implement blind synchronization of the bit timing phase using the simple early–late gate method.

The early–late gate TED method application principle in the context of the Δsync signal example is shown in Figure 8. Two gates are accumulators, which integrate the first and second halves of the Δsync signal relative to the half-periods of the assumed clock. The assumed clock’s period, without any phase adjustments, is equal to the symbol length of 8192 samples. If the assumed clock timing matches the symbol bit timing in the Δsync signal, the difference between both accumulators will be close to zero; therefore, symbol timing phase synchronization is established. However, if the phase of the assumed clock does not match the symbol timing, there will be a notable difference between the values accumulated in both gates. The sign of this difference shows the direction of the timing shift, and the absolute value of this difference can be correlated to the magnitude of the correction shift that should be applied to the assumed clock timing phase. The obtained timing error is used in a controlled feedback loop to modify the assumed clock phase and, with each cycle iteration, bring it closer to the actual symbol timing. After achieving the symbol phase synchronization, the early–late gate synchronizer will continue to track and slightly adjust the timing phase during the entire duration of the data transmission. The example is shown for the specific case, when bit “1” is between bits “0”. As the absolute values of gate’s accumulated signal are compared, in the case of opposite bit values, this TED will work the same way. The early–late gate TED will also work in cases when data transition from “0” to “1”, or the opposite, occurs only on one side of the gates’ period, but with less efficiency. And finally, when there is no data bit transition (where a sequential “1” or “0” is transmitted), the early–late gate synchronizer will not be able to obtain information about the timing error and the assumed clock will not be significantly shifted. For this reason, communication in such a system should start with alternating bits, which speeds up symbol phase synchronization and, therefore, reduces the bit error rate probability.

A conventional early–late gate symbol timing synchronizer design [25] was adapted, considering the requirements of the FM-ACSK communication system and the FPGA implementation. The symbol phase synchronizer was initially built in the Simulink environment, using a fixed-point approach, and implemented into the VHDL code with the assistance of the HDL Coder toolbox. The developed design is explained further.

At first (see Figure 9), the Δsync (“err_delta_in”) signal is logically shifted left by 3 bits (multiplied by 2³ = 8) to increase its amplitude variation, after which it is integrated over the first and second half of the assumed clock timing (the early and late gate, respectively). The signal SYNC_CLK is the assumed clock, which forces the accumulator to reset each half-period. Digital integration in the simplest design consists of two parts—the N bit accumulator and the division by 2^N. The accumulator in the present design accumulates approximately 2¹² samples (this may slightly vary due to the SYNC_CLK phase adjustments in the feedback loop); hence, the accumulated signal is arithmetically (keeping the sign) right-shifted by 12. The operation of bit shifting takes practically no hardware resources, while division with a variable number would require quite a lot of hardware resources, so accuracy in this case has been slightly subdued for the sake of efficient usage of FPGA resources.

A simple, but partial way of obtaining the timing error would be as follows:

$$partial timing error=\left|E\right|-\left|L\right|,$$

(5)

where E is the early gate’s registered value and L is the late gate’s value. However, when applied to the Δsync signal, (5) will only give useful results for timing phase errors below 25% of the symbol length. Meanwhile, the maximum timing error occurs at a shift equal to 50% of the symbol length—if such a shift occurs on the region where Δsync changes its sign, (5) results in a near-zero value. To make this TED implementation viable across all possible timing shifts, the timing error is obtained in two steps, calculating the timing phase shift magnitude and direction separately:

$$timing error=\left|E-L\right|\times sign\left(\left|E\right|-\left|L\right|\right).$$

(6)

When both gate integration results are being registered and compared, a slightly modified approach than that of (6) is used to turn the timing error into phase adjustment information, as well as scale the magnitude of the required phase adjustment step:

$$PHASE\_ADJUST=2^6\times \left|E-L\right|\times sign\left(\left|L\right|-\left|E\right|\right).$$

(7)

The scaling (2⁶) directly affects the performance of the early–late gate timing synchronizer, as it defines the magnitude of the phase adjustments for each SYNC_CLK period. Too large a scaling number could “jump over” the desired phase, resulting in timing error oscillation and increases in gate integration inaccuracies. On the other side, too small a scaling number would make the timing recovery too slow. The chosen number empirically shows a better-balanced performance than other bit shift values.

The PHASE_ADJUST signal is used to adjust the output phase of a free-running 12-bit counter, which is responsible for SYNC_CLK signal generation. Another 13-bit counter is used to prevent SYNC_CLK from alternating too soon in cases when the phase jumps forward, but fewer than 2048 samples have passed since the last alteration. The obtained phase clock is passed along to the bit detector module, which is described next.

2.4. Decision-Making Device (Bit Detector)

The decision-making device uses the Δsync signal to decide the values of the received bits using the timing obtained by the symbol phase synchronization module. As Figure 10 shows, the Δsync signal (“err_delta_in”) is integrated across the length of the whole symbol, according to the retrieved bit timing (“sync_clk_in”). The accuracy of the integration is of low importance here, as only the sign of the result is used for decision making. Positive integration results return bit “1”, negative—bit “0”.

3. Study of the Communication System

This section explains the experimental setup used to conduct tests on the FM-ACSK FPGA prototype and the results of the tests.

3.1. Experimental Setup

The prototype was tested for additive white Gaussian noise (AWGN) resistance in direct channel and in two-path signal propagation emulation scenario. Both mathematical model simulations and FPGA experiments of FM-ACSK system were conducted. Simulation was performed using Matlab script using Simulink model with Bernoulli random bit generator, AWGN channel, and bit error ratio (BER) counting function, saving BER and SNR data into the text file with each iteration of simulation. Experiment on the FPGA prototype, however, required some more preparation, which is explained further.

Cyclone V has more capabilities than FPGA itself, as it is System-on-Chip (SoC) device which has Hard Processing System (HPS) with Arm Cortex-A9 Microprocessor Unit (MPU) and peripheral controllers. This extends operating possibilities for Cyclone V employment and allows us to interconnect FPGA signal processing and software program that uses MPU and runs in the dedicated Linux environment. Additionally, as the prototype is designed using Arrow SocKit Development Board, Cyclone V has access to all the connected peripherals, such as clocks, buttons, switches, LEDs, SDRAM memory, and USB-to-UART bridge, used in the experimental setup.

An overview of the experimental setup is shown in Figure 11. Green blocks refer to specifically designed FPGA modules for the FM-ACSK prototype BER testing experiment, while blue modules are FPGA Altera/Intel Intellectual Property (IP) cores from the Quartus library. Red blocks are HPS modules integrated into Cyclone V SoC, while yellow blocks are external Integrated Circuits (ICs) on the Arrow SocKit Development Board and Highspeed AD/DA Daughter Card. White blocks refer to various unclassified external units.

Overall, FM-ACSK transmitter module generates chaotic symbols (8192 samples long for 1 modulating data bit) according to the pseudorandom input data sequence. This output is transformed into analog signal by DAC, sent over a 62 cm long coaxial cable to ADC, and transformed back to digital 14-bit signal. As converters do not support signed alternating signal, most significant bit (MSB) is inverted before the DAC input and after ADC output, thus transforming common Binary Two’s Complement (BTC) bit coding schemes into Bipolar Offset Binary (BOB) coding scheme and back. Delay between DAC input and ADC output is equal to 10 samples (at 50 MHz clock) and gain is 0.3506703 (these values are used in Simulink model in place of ADC-DAC for approximate consistency). After ADC, the received signal gets white noise applied to it and processed in the FM-ACSK receiver module. Recovered data bits are used for BER estimation, as explained further.

In addition to the previously described FM-ACSK base system (essentially, transmitter and receiver modules), the following FPGA modules (see Figure 11) were designed for experimental setup: Data Bit Timing, LFSR (Linear Feedback Shift Register), AWGN Controller, BER Controller, and BER-to-DMA.

Data Bit Timing module is a simple 13-bit free-running counter that outputs “1” once per 2¹³ = 8192 clocks, which is equal to the desired timing of the data bit/symbol (T_b) that is getting transmitted using FM-ACSK digital communication system.

The LFSR (Linear Feedback Shift Register) module generates a pseudorandom bit sequence, using a 16-bit Maximum Length Fibonacci LFSR, with the feedback polynomial x¹⁶ + x¹⁴ + x¹³ + x¹¹. It ensures good approximation of the average random data transmission scenario, and this sequence is also used for BER counting, as explained further.

AWGN Controller module has two main functions: adding noise to the received signal and controlling the signal-to-noise ratio (SNR). The digital white noise here emulates the averaged real noises in the wireless transmission channel which allows us to perform series of uniformed noise impact experimental measurements required for BER analysis. For AWGN generation, a model provided by MathWorks, “HDL Implementation of AWGN Generator” [26], was used with slight modifications (such as data bus width adjustments and changing complex output into real). It provides AWGN output for various SNR input values relative to 1 W (0 dBW) signal power with 0.1 dB step. Real SNR for the experimental data is corrected in accordance with the average power of the input FM-ACSK signal (−12.1112642 dBW) and its bandwidth (1.72 MHz) relative to the Nyquist frequency (25 MHz). SNR is controlled in real time using onboard switches and buttons, which allow us to select one of the 127 pre-mapped SNR states, or turn off the noise addition to the signal. Usage of 14-bit signed fixed point data bus with 12 fractional bits on both input and output of AWGN Controller implies limitation on SNR values that are too low, as the noise overflows the numeric range that this format can represent; thus, such low values were not used in experimental tests.

BER controller unit processes received data bits and counts bit errors. It is identical to the transmitter’s 16-bit LFSR pseudorandom sequence module, as well as two simple Linear Shift Registers (LSRs): 16-bit LSR that takes input from LFSR output and 32-bit LSR that takes input from FM-ACSK receiver output (see Figure 12). When received data sequence, uploaded to 32-bit LSR, exactly matches known pre-loaded 32-bit sequence key in the 16-bit LFSR and 16-bit LSR taken together, BER controller’s state switches from “INITIAL” to “LOCKED”. It indicates this event by lighting up an LED on the development board, and enables the remaining two shift registers, after which LFSR begins to continuously produce the next values of the pseudorandom sequence. From this moment, two counters are activated: one counts bit errors, while another counts the amount of received bits. Values of these counters are later used for BER value estimation. Bit error fact is determined by comparing internally generated pseudorandom sequence bit values with received bit values.

The BER controller module also has a “soft” reset signal input, attached to an onboard button key (separately from global FPGA “hard” reset signal), which can be used to clear counters and reset BER controller to the “INITIAL” state. It is notable that this controller will only recognize received 32-bit key sequence as valid if no bit detection errors occurred during the reception of key bits, which makes the locking hard to achieve at lower SNRs. If any bit errors occurred during the first key reception attempt, locking with higher probability may happen on one of the next attempts, as the whole pseudo-random bit sequence is cyclic and repeats after 2¹⁶ − 1 = 65,535 values, which takes 65,535 × Tb/Fs = 65,535 × 8192/(50 × 10⁶) = 10.737 s on FPGA. This cycle time being relatively short is one of the reasons for choosing LFSR to be 16 bits long. However, the key length of 32 bits was selected mainly to reduce probability of random noise input decoding as a valid key. For 16-bit key, such probability (assuming noise input generates statistically equal number of zeros and ones) is (1 − 0.5)¹⁶ = 1.526 × 10⁻⁵, but for 32-bit key, it is (1 − 0.5)³² = 2.328 × 10⁻¹⁰. Another reason for choosing the 32-bit key over the 16-bit one is the key correlation statistics with the whole pseudorandom sequence. For the 16-bit keys, all 16 bits fully correlate with the pseudo-random sequence only once (as it should be), but 15 of 16 key bits will correlate 16 times, and 14 of 16 key bits will correlate 120 times. These partial correlations are additional risk factors of false-positive key locking event probability, if the few non-correlated bits were to be flipped due to the noise impact on the transmission. The 32-bit keys have exactly 0 partial correlations with 31, 30, 29, and 28 key bits, with only 14 partial correlations with 27 of 32 bits, thus greatly reducing probability of this possible error. This is not critical for BER counting purposes, but it will enhance the security of the transmission with key-coded packets that will be used in future design.

At the BER-to-DMA module, simple data bus is bridged for Avalon Streaming interface [27] and passed to the DMA Write Master IP core module with the goal of sending the obtained bit count and bit error values to the SDRAM memory. Further data processing is performed by the Altera IP cores and the HPS modules which ensure interconnection in accordance with the defined settings and internal design of SoC. Finally, obtained BER data are retrieved, processed, and displayed on PC monitor by a simple custom program (written in C), running on Linux.

Comparing processing speed between Matlab Simulink simulation and FPGA prototype of FM-ACSC communication system, it takes about 10 h to simulate transmission of 20,000 data bits on an average PC, while on FPGA, it takes exactly 3.2768 s. That makes FPGA prototype transmission speed about 11,000 times faster, which gives a significant advantage for BER estimation on relatively high SNR values and allows us to improve the overall BER precision by significantly increasing the number of transmitted bits per SNR point. The data rate on the FPGA is constant as it is defined by the used system clock speed of 50 MHz and the chosen symbol length of 8192 samples, resulting in 6.1 kbps.

Figure 13 shows FPGA resource usage summary for all main FM-ACSK modules in the form of Quartus Prime 20.1 software report. For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all its sub-entities in the hierarchy. Most resource-consuming modules are FIR filters (inside of the FM demodulator, and after it), because their performance quality correlates with the number of filter taps used in the design. Higher precision of the filtering increases the system’s immunity to the channel noise, but this effect has minimal impact on the BER analysis, where SNR considers only noise that is within unfiltered signal band. Block memory is used in two application scenarios—delay lines (e.g., accumulator) and signal generation (e.g., AWGN). Using the DSP blocks is necessary when multiplication of two variable signals is required, which happens mainly in filters. Fortunately, despite the limited number of DSP blocks, Quartus can effectively reuse the same processing blocks multiple times, which is defined during late stages of compilation. Overall, resource usage would scale relatively to the chosen bit widths of data buses. This number varies within modules, but the base value at the transmitter is 14 bits, but at the receiver it is raised to 17 bits. The 14-bit bus width is chosen for compatibility with the 14-bit ADC and DAC units used in the prototype, which limits the precision of chaotic signals but is sufficient for communication system application tests.

3.2. Noise Resistance

Both Matlab simulation and FPGA prototype testing results for the FM-ACSK digital chaotic communication system are shown in Figure 14. In the case of simulation, the BER curve pattern is smoother and shows slightly better noise resistance (for approximately 1 dB SNR) than BER curve obtained from the FPGA prototype tests. The fact that the prototype showed less noise resistance than the mathematical model is fully within expectations, as it is a more complex design, which also includes analog part. The irregular pattern observed in the FPGA BER curve is challenging to explain and requires further study. As the irregularities have repeating pattern, it is possible that they are related to the noise value distribution on fixed-point data bus taking one less or one more data bit and being constrained by the absolute limits of the data bus. It is an effect that is barely noticeable with large number of errors per test (several thousands) and more noticeable when there are few bit errors per test (hundreds). At the very least, it can be definitively stated that this irregularity is not due to limited statistics in the BER calculations. In the mathematical model simulations performed in Matlab Simulink, only 2000 data bits were used for most BER points, and 20,000 data bits for the four lowest BER points. In contrast, during the FPGA prototype tests, where performance speed is significantly higher, most BER points were calculated using approximately 1,563,000 transmitted data bits, with the number increasing to 473 billion data bits per point for higher SNR values and some BER points that initially raised concerns regarding accuracy. Further investigation might reveal these irregularities in Simulink model tests as well, if more dense SNR values with many more data bits per test to be taken.

The first turning point of the FPGA prototype’s BER curve from the FPGA prototype testing results (see Figure 14), at approximately 1.3 dB SNR, is most likely related to the FM demodulation threshold, where noise impact on the instantaneous phase is too strong for even partial recovery of information to be possible. With higher SNR values, the BER curve of the prototype mostly follows a trend where it drops with an increasing rate from more than 2 dB per decade to less than 1 dB per decade at highest SNR values. The data obtained allow us to predict the noise performance of the developed communication system.

4. Discussion

This system integrates an FPGA-based implementation of a chaotic communication system utilizing a modified Chua chaos generator, an error feedback chaotic synchronization method, and FM-ACSK modulation. Within the broader domain of chaotic communication systems, this design distinguishes itself through its unique configuration and innovative approach.

The proposed FM-ACSK system, while limited to a modest data rate of 6.1 kbps (with a 50 MHz clock, 8192 clock cycles per symbol, and 1 data bit per symbol), serves as a proof-of-concept for an alternative approach to chaotic communication, specifically tailored for FPGA implementation. The ACSK modulation part employs coherent detection and an error feedback chaotic synchronization technique, which holds potential for establishing secure and reliable communication links. Meanwhile, the use of FM enables stable passband operation, simplifies carrier frequency and bandwidth management compared to chaotic carriers, and eliminates the need for carrier phase synchronization. Additionally, the constant power envelope of the FM transmitter minimizes the peak-to-average power ratio (PAPR), a common limitation in other communication systems that can hinder transmitter efficiency.

A Simulink-based mathematical model was developed alongside the FPGA prototype to simulate the digital components of the communication system. Leveraging the FPGA for key system functionalities provides significant flexibility, enabling iterative enhancements and modifications without the need for hardware re-fabrication. This model streamlines the design and validation, allowing for performance evaluation under a range of conditions, and substantially reducing the complexity and time investment typically associated with FPGA-based prototyping.

As is common with coherent chaotic communication systems, noise immunity remains a challenge, with system performance closely tied to the quality of chaotic synchronization during demodulation. This trade-off underscores the inherent balance between achieving enhanced physical layer security and managing sensitivity to noise.

The performance of the FM-ACSK system was evaluated in an AWGN channel, achieving a BER of 10⁻⁴ at an SNR of approximately 5.6 dB in simulation. This performance surpasses that of the previously studied ACSK system, where a similar BER for the simulation was achieved at an SNR of 8 dB under comparable conditions. For the FPGA prototype, a BER of 10⁻⁴ is observed at an SNR of around 6.3 dB, which aligns with expectations when transitioning from a simulation to real hardware. The observed irregularities in the BER curves for the prototype highlight additional areas for further investigation and refinement of the system.

When comparing the BER performance of the FM-ACSK system with other chaotic communication systems, a few relevant examples stand out, though such comparisons are approximate due to differences in design and application. For instance, Berber and Feng [28] demonstrated an offset quadrature phase shift keying (OQPSK) modulation scheme with a chaos generator, achieving 10⁻⁴ BER at an SNR of 8.2 dB. In another study, Abdullah and Valenzuela [29] proposed a non-coherent modified COOK scheme, achieving 10⁻⁴ BER at an SNR of 12 dB. Tayebi et al. [30] observed an SNR of 8.8 dB at 10⁻⁴ BER in a chaos-based direct sequence spread spectrum (DSSS) system, while Abdullah [31] reported an enhanced frequency-modulated quadrature chaos shift keying (FM-QCSK) system achieving 10⁻⁴ BER at a 10 dB SNR. For reference, a conventional non-chaotic binary phase shift keying (BPSK) scheme theoretically achieves 10⁻⁴ BER at an SNR of around 8.2 dB. These results indicate that the FM-ACSK system’s noise performance is competitive with other systems and has potential for improvement as the technology matures.

In terms of physical layer security, the FM-ACSK system demonstrates several traits that can be discussed, although proper assessment would require an additional study dedicated to this subject. While the system transmits digital information and employs a digital foundation, its modulation and transmission are analog, limiting the scope of potential attacks. For example, eavesdropping would require knowledge of the modulation scheme. Although FM demodulation is straightforward and can be performed, for example, using software-defined radio (SDR), decoding the ACSK signal would ideally require replicating the system’s exact setup, including the precise configuration of the slave chaos generators. If channel noise is low, distinguishing between direct and inverted “R_out” signals might allow an attacker to decode the ACSK signal by observing its properties. However, this vulnerability can be mitigated by using a chaos generator with output signal properties that make such distinctions more difficult while maintaining reliable synchronization.

Potential attack scenarios such as jamming and man-in-the-middle attacks are also considered. The FM-ACSK system benefits from spread-spectrum properties, which offer some level of resistance to interference. However, deliberate jamming is possible if the attacker exploits the FM receiver’s capture effect [32] by transmitting a higher-power carrier signal on the same frequency. The exact power differential required for successful jamming varies by FM demodulator and should be studied further. Resistance to jamming also depends on the design of the communication system’s radio components, which were outside the scope of the present prototype.

For a man-in-the-middle attack, the attacker would first need to successfully eavesdrop the communication and then replicate the FM-ACSK modulation in real time while altering the transmitted data. Although SDR could replicate the FM-ACSK signal using pre-recorded segments, real-time replication is challenging due to the FPGA’s higher processing speed compared to SDR. Furthermore, the use of transmission packets with code keys, which can be updated at will, complicates the attacker’s task of replicating and modifying the FM-ACSK transmission.

Overall, the security features of the FM-ACSK system prototype warrant further experimental analysis and comparative testing with other communication systems. The chaotic coherent detection scheme offers a significant advantage over more popular non-coherent chaotic systems, which are more susceptible to eavesdropping. Compared to non-chaotic communication systems, where modulation techniques are well-documented and pose minimal theoretical challenges to interception, the FM-ACSK system benefits from a more intricate design that enhances its security potential.

Future research will focus on further evaluating the system’s performance, including its resistance to multipath propagation. Over time, key performance bottlenecks will be identified and optimized to achieve greater noise immunity, higher data rates, and improved overall efficiency, enhancing the system’s robustness and adaptability for practical secure communication applications.

5. Conclusions

In this work, a prototype of a novel digital chaotic communication system utilizing FM-ACSK modulation was successfully developed on an FPGA platform. By integrating frequency modulation with ACSK, the system improved resilience against channel nonlinearities and carrier frequency offsets, while retaining the benefits of a coherent-detection chaotic communication scheme.

This study demonstrates the feasibility of and serves as a proof-of-concept for the proposed FM-ACSK chaotic communication system, which holds potential for applications in IoT and wireless networks. Although the current prototype is not fully optimized, it provides a flexible framework for future advancements. The findings lay a foundation for further research aimed at enhancing system performance, increasing noise immunity, and expanding functionality in subsequent iterations.