A Low-Cost Evaluation Tool for Synchronization Methods in Three-Phase Power Systems

Abstract

The use of renewable energy sources (RESs) together with energy storage systems (ESSs) allows for smoothing power variations, thus improving power backup capabilities and power quality in the electric power grid. These applications require power converters to transfer energy between the renewable generator or energy storage and the power grid. In any case, the control algorithm of the power converter requires the synchronization method to provide a correct estimation of the instantaneous voltage of the power grid. This work provides engineers and researchers with an accessible platform at a low cost (less than USD 100) and a methodology for the experimental validation of digital synchronization algorithms as a step before their implementation in grid-connected equipment. The methodology evaluates the performance of the digital algorithms when there are variations in amplitude, frequency, phase, and harmonic content in the emulated three-phase power grid, as well as the execution times (t_ex), while a digital platform emulates the electrical signals and generates reference signals for the evaluation. To illustrate this proposal, two synchronization algorithms—SRF-PLL and DSOGI-PLL with a low-pass filter—are implemented in a digital controller and tested. The evaluation tool confirms the algorithms’ performance and shows that the execution time of DSOGI-PLL is 91% longer than that of SRF-PLL, which is well known in the literature.

1. Introduction

The integration of renewable energy sources (RESs) such as photovoltaic and wind power in electric power systems is an alternative that can lead to reductions in green-house gas emissions and, at the same time, to reduced energy costs [1,2,3]. Moreover, the implementation of RESs such as distributed energy resources (DERs) in facilities near electricity consumption, or in customer facilities, reduces transmission losses, grid congestion, and maintenance costs [4] and can achieve a more reliable electrical grid [5].

One drawback of RESs is the power fluctuations due to climatic factors, such as changes in irradiance and wind speed. As a solution, RESs can be implemented together with energy storage systems (ESSs), achieving (i) smooth short-term energy fluctuations and (ii) improved backup power capabilities [6].

The RES and ESS group uses power converters based on power electronics devices, allowing for energy control, injection, or storage. The implementation of power converters requires the connection of power devices between the energy generator, the storage system, and the electric grid. Due to the requirements of their control systems, the design and implementation of digital synchronization methods are a relevant step for adequate electric power injection into the grid. In addition, the synchronization methods are used in other applications, such as the control systems of electric generators and the energy measurement systems of the electric grid [7].

The synchronization methods allow for the estimation of several values of the grid voltage, such as (i) the phase, (ii) the frequency, and (iii) the amplitude of the positive sequence component [8]. The three-phase synchronization methods can be classified as open-loop [9,10,11,12,13] and closed-loop [14,15,16] (Figure 1). One of the most documented closed-loop methods is the phase-locked loop (PLL) [17,18]. The PLL-based methods include (i) synchronous reference frame PLL (SRF-PLL), (ii) moving average filter PLL (MAF-PLL) [19], (iii) adaptive cascaded delayed signal cancellation PLL (CDSC-PLL) [20], and (iv) dual second-order generalized integrator PLL (DSOGI-PLL) with a low-pass filter (LPF) [21].

In the development stage of a control strategy for power converters, the implementation of a synchronization method needs to be experimentally validated before it can be used in the electrical power system. In addition, the validation stage allows for the evaluation of the algorithm’s performance under different scenarios or grid voltage disturbances, such as (i) sag, (ii) swell, (iii) harmonics, (iv) frequency variations, and (iv) unbalance between phases.

Previous works have used different tools to validate the synchronization algorithms experimentally. These tools can be classified into (i) emulated digital processing systems (EDPSs) and (ii) acquisition from the electrical system (AES) (Figure 2). Works that use EDPSs can emulate electrical signals using computational simulations. In [22], the authors simulated the power grid voltages and implemented the synchronization algorithms using MATLAB/Simulink. Their work analyzed the synchronization capability of the algorithms in distributed generation systems during balanced and unbalanced conditions by comparing the overshoot (OS) of the frequency step changes. In [23], the synchronization algorithms were implemented externally using an electronic board to acquire the simulated signals and to execute the algorithms, a concept known as a processor in the loop (PIL). With the above, the authors evaluated the performance of a photovoltaic inverter connected to the grid where the electrical system and the photovoltaic inverter were simulated in MATLAB/Simulink, and the synchronization systems were implemented on the STM32F407-based board. In [24], several algorithms were evaluated by connecting two electronic devices based on micro-computerized systems: one for the emulation of the electrical grid and the second for the execution of the synchronization algorithms. The work compared the response time, the accuracy, and the computational efficiency in an ideal electrical system and a grid with harmonics distortion. The grid emulation and execution methods were implemented in digital systems with real-time simulation capability using a compact development environment based on a field-programmable gate array (FPGA) and/or digital signal processors. The platform also generated emulated signals for an external platform. In [25], an unbalanced electrical system with voltage harmonics was experimentally evaluated considering the OS and steady-state (ST) estimation of frequency ripple. Moreover, the work evaluated the algorithms using computational simulations, considering balanced and unbalanced grid and voltage variations such as sag, phase step change, and direct current (DC) offset. In [26], several algorithms used in distributed generation systems were evaluated for disturbances such as amplitude and frequency variations, unbalance, and harmonics. In [27], due to their hardware and software characteristics, these platforms were also used to evaluate distributed systems.

The works that use AES require the equipment to acquire, process, and generate three-phase alternating current voltages. In [28], a converter connected to a single-phase electrical system was used. In [29], disturbances such as unbalance and harmonics, frequency and phase changes, and sag voltage were programmed in the output voltages of a three-phase inverter. The algorithms were implemented on the Infineon XMC 4500-based platform and were evaluated by analyzing the root-mean-square error (RMSE), mean error (ME), OS, settling time (t_s), and process time. In [30], a programmable alternating current source was used. The paper evaluated the performance of synchronization algorithms when changing the phase in a grid with the presence of sag, frequency deviations, and DC offset. The work compared the frequency ripple, t_s, and implementation complexity. Finally, Ref. [31] emulated the voltages with an inverter converter connected to a programmable DC source and used frequency estimation, phase estimation, and t_s to compare the algorithms used.

The cost of implementing the different evaluation tools depends on the prices of the equipment or devices used (

Table 1. Prices of the equipment used to validate synchronization methods.

Type of Tool	Equipment or Device	Price [USD]	Price Level
Emulated on Digital Processing Systems (EDPS)	Academic MATLAB per year	275	Upper Low
	Startups MATLAB and Simulink Suite per year	3950	Medium
	STM32F4 Discovery, digital platform	20	Low
	LAUNCHXL-F28379D, C2000 Family TI, digital platform	50	Low
	PLECS RT Box CE + RT Box LaunchPad-Nucleo Interface	7000	Medium
	PLECS RT Box 2 + RT Box LaunchPad-Nucleo Interface	24,000	High
Acquisition from Electrical Systems (AES)	GW Instek APS-1102 Programmable AC/DC Power Supply	2490	Medium
	GW Instek PSU 6-200 Programmable DC Power Supply	1970	Medium
	ITECH IT7909-350-90 Regenerative Grid Simulator	31,000	High
	Programmable inverter TPI8032 22 kW, Imperix	20,130	High
	Inverter 30A, 400VAC, MTL-Series, GUASCH	1920	Medium

). In particular, the cost of the tools based on computational simulation is in the upper-low (from USD 100 to USD 1000) to medium (from USD 1000 to USD 10,000) price range, depending on the type of software license. The micro-computerized systems have a low price range of implementation (less than USD 100). The cost of implementation of the real-time simulation systems and the AES tools is in the range of medium to high (over USD 10,000).

The real-time simulation systems stand out from other methods without grid connection of their computational capacity. Examples of real-time simulation systems include PLECS RT Box, Typhon HIL404, RT-LAB, and Micro-LabBox. However, when considering accessibility, the methods based on computational simulation and micro-computerized systems stand out for their versatility and lower cost (see Table 1). This way, microcontroller-based systems allow for the implementation of an accessible experimental tool for evaluating and validating synchronization methods.

This work proposes a new evaluation tool for synchronization algorithms implemented in digital devices. The proposal is based on the emulation of the electrical grid using the Texas Instruments LAUNCHXL-F28379D development platform, and it describes the required peripherals and the methodology of its use for both validation and performance evaluation. The main objective is to provide a tool for engineers and researchers for the experimental validation and evaluation of digital synchronization algorithms before their implementation in grid-connected equipment.

The main contributions of this work are (i) to propose a low-cost and versatile digital platform for the experimental evaluation of synchronization techniques, (ii) to present a methodology of its use for the experimental evaluation of synchronization techniques, and (iii) to illustrate the uses and advantages of the proposal via the experimental validation of synchronization techniques based on PLL. All of these contributions focus on power converters based on RESs for electric power injection.

The remainder of this document is organized as follows: Section 2 presents the evaluation tool and methodology for the validation and evaluation of digital synchronization algorithms. Section 3 presents the main results when implementing the evaluation tool and evaluating two digital synchronization techniques based on PLL. Finally, Section 4 presents the main conclusions.

2. Evaluation Tool and Methodology of Use

The evaluation tool has three elements: (i) the emulator, (ii) a digital controller, and (iii) the methodology of use (Figure 3):

• The emulator is a low-cost digital platform where the voltages of a three-phase grid are emulated and where reference signals such as amplitude, phase, and frequency are generated to evaluate the synchronization algorithms. These signals must be visualized with an oscilloscope. The emulator can generate disturbances such as voltage harmonics and frequency variations and, also, generate unbalance between phases.
• The digital controller is a second digital platform that implements synchronization algorithms and, therefore, implements the controller for the power converter. The digital controller acquires the emulated grid voltages, processes them, and generates the estimated signals for the synchronization algorithms.
• The methodology of use is the action to be executed for the correct connection between the emulator and the digital controller; it includes actions to evaluate and compare the performance of the synchronization algorithms. Additionally, the methodology indicates the configuration of an oscilloscope for applying the methods.

The voltage grid generated by the emulator can be configured according to the test to be performed, allowing us to set the (i) amplitude, (ii) phase, (iii) frequency, and (iv) harmonic content of the grid. Different case studies can be predefined and selected through a simple interface built from switches.

The algorithm implemented in the digital controller will estimate the frequency, phase, and amplitude of the acquired grid voltages. The digital controller must generate the following analog signals using the estimated values computed by the synchronization algorithm: (i) synchronized grid voltages, (ii) amplitude, (iii) phase, and (iv) frequency. In the event that several methods or configurations need to be evaluated, external switches allow for the selection of these methods or configurations, allowing different estimated signals to be shown with the limited digital-to-analog converters (DACs) that are typically available.

The evaluation and validation of the synchronization algorithms are performed by comparing and analyzing the emulated grid voltages, the reference signals, and the signals estimated in the digital controller. A digital oscilloscope is required to display the signals and compute some numeric indicators. Moreover, the execution time (t_ex) of the algorithms is evaluated through a digital output on the digital controller. The emulator generates a synchronization signal to be used as a trigger for the correct visualization of the signals in the oscilloscope.

For the performance analysis of the algorithms, the reference and the estimated signals are compared using the (i) overshoot (OS), (ii) settling time (t_s), (iii) root-mean-square error (RMSE), and (iv) mean error (ME). The performance evaluation also considers the (v) execution time of the algorithm in the digital controller.

The implementation requires that the digital platform must have at least three (DACs) or pulse-width modulated (PWM) outputs with low-pass, which will be used for the three-phase signals. Furthermore, the digital platform requires at least one DAC to generate the fundamental voltage, amplitude, phase, or frequency references, which will be displayed in the oscilloscope and used as references for the evaluation. Finally, the digital controller requires three analog-to-digital converters (ADCs) and at least one DAC to display the estimated signals. The emulator and the digital controller require each one to have at least one digital output and two digital inputs.

The following subsections present (i) the emulator’s implementation using the Texas Instruments digital development platform and (ii) the methodology of use. The methodology presents the stages to be executed, from the connection of the digital platforms up to the methods for evaluating the synchronization algorithms.

2.1. The Evaluation Tool

Figure 4 shows a schematic of the proposed evaluation tool using the Texas Instruments C2000-based board as the emulator. The cost of this board is close to USD 50, which is in the lower price range (Table 1). The board is a digital platform used in the field of motor control, power converters, and digital signal processing. The emulator generates the (i) emulated voltages of a three-phase system, $v_{sa}\left(t\right)$, $v_{sb}\left(t\right)$, and $v_{sc}\left(t\right)$, (ii) the reference voltage $v_{sa1,ref}\left(t\right)$, (iii) the synchronization signal $sync\left(t\right)$ and (iv) the analog output signals $ou{t}_A\left(t\right)$ and $ou{t}_B\left(t\right)$.

The digital input signal ${sw}_{outAB}\left(t\right)$ allows for assigning to the outputs ${out}_1\left(t\right)$ and ${out}_2\left(t\right)$ the internal reference signals of (i) amplitude $A_{1,ref}\left(t\right)$, (ii) phase ${\theta }_{1,ref}\left(t\right)$, and (iii) frequency $f_{1,ref}\left(t\right)$. Additionally, the digital input signals $s{w}_H\left(t\right)$ and ${sw}_{case}\left(t\right)$ allow us to modify the previously configured content and reference signals.

Table 2. Description of the emulator signals.

Variable	Description
$Emulator$	LAUNCHXL-F28379D C2000 Delfino LaunchPad
$v_{sx}\left(t\right), x=a,b,c$	Voltage a, b, or c
$v_{sa1,ref}\left(t\right)$	Fundamental voltage a
$sync\left(t\right)$	Synchronization signal
${out}_A\left(t\right)$$\mathrm{and} {out}_B\left(t\right)$	Analog output
${sw}_H\left(t\right)$	To select the case of the harmonic
${sw}_{mode}\left(t\right)$	To select the case study
${sw}_{outAB}\left(t\right)$	To select the outputs for DACOUTA and DACOUTB
$A_{1,ref}(t)$	Reference of the fundamental amplitude
${\theta }_{1,ref} (t)$	Reference of the fundamental phase
$f_{1,ref} (t)$	Reference of the fundamental frequency

shows a summary of the signals in the emulator.

The digital controller requires four ADCs, two DACs, and five digital inputs/outputs (DIOs). The digital controller specified in Figure 3 uses the input signal $s{w}_{out01,ab}\left(t\right)$ to select the estimated signals and generate them at the outputs $ou{t}_0\left(t\right)$ and $ou{t}_1\left(t\right)$. The estimated signals correspond to the (i) grid voltage $v_{sa,o}\left(t\right)$, (ii) amplitude $A_{1,o}\left(t\right)$, (iii) phase ${\theta }_{1,o}\left(t\right)$, and (iv) frequency $f_{1,o}\left(t\right)$. A second digital input signal $s{w}_{tec,ab}\left(t\right)$ allows the synchronization technique to be selected when evaluating multiple algorithms. On the other hand, the digital output enables the $DT\left(t\right)$ signal to be obtained for the calculation of the execution time.

Table 3. Selections of harmonic content, case studies, and DAC signals in the emulator.

Variable	Description
Digital Controller	Arduino Due
$ou{t}_0\left(t\right)$	Analog output
$ou{t}_1\left(t\right)$	Analog output
$s{w}_{tec,a}\left(t\right)$	Digital input, assign synchronization technique
$s{w}_{tec,b}\left(t\right)$	Digital input, assign synchronization technique
$s{w}_{out01,a}\left(t\right)$	$\mathrm{To} \mathrm{select} \mathrm{the} \mathrm{outputs} \mathrm{to} ou{t}_0\left(t\right)$$\mathrm{and} ou{t}_1\left(t\right)$
$s{w}_{out01,b}\left(t\right)$	$\mathrm{To} \mathrm{select} \mathrm{the} \mathrm{outputs} \mathrm{to} ou{t}_0\left(t\right)$$\mathrm{and} ou{t}_1\left(t\right)$
$DT\left(t\right)$	Duty cycle for execution time
$A_{1,o}\left(t\right)$	Amplitude of the fundamental voltage estimated.
${\theta }_{1,o} \left(t\right)$	Phase of the fundamental voltage estimated.
$f_{1,o} (t)$	Frequency of the fundamental voltage estimated

shows a summary of the signals in the digital controller.

2.2. The Methodology of Use

The procedure to implement the evaluation tool considers five stages, from the connection of the emulator and digital controller to the evaluation of the synchronization techniques (Figure 5).

2.2.1. Connection of the Emulator to the Digital Controller

To avoid electrical damage to the board, the connection must consider the operating voltage ranges of the DACs in the emulator and the ADCs in the digital controller. The DACs and ADCs shown in Figure 4 operate in the [0, 3.3] V range, which enables the direct connection between the emulator and digital controller in the 3.3 V CMOS standard. In particular, the analog outputs of the emulator, identified as DACx, are obtained through PWM outputs with a low-pass filter and, also, operate in the range of [0, 3.3] V.

If the ADCs and DACs do not operate in the same range, it is possible (i) to program the internal signals of the emulator and digital controller to operate in an allowed voltage range or (ii) to use a conditioning circuit. An example of this type of circuit is shown in Figure 6 [32].

2.2.2. Signal Scale in the Emulator and the Digital Controller

The grid voltages generated on the emulator’s DACs are scaled from [0, 4095] counts to [0, 3.3] V when a 12-bit resolution is used (Figure 7), generating a voltage within [0.825, 2.475] V when the internal voltage of the emulator varies within [−1, 1] p.u. or within [1023, 3071] counts. The emulated voltages have a zero average value at 2047 counts or 1.65 V at the output of the DACs. The emulated voltages are acquired by the 12-bit ADCs of the digital controller and scaled in the same digital range. However, the 12-bit DACs of the digital controller consider a different conversion of the voltage signals, from [−1, 1] p.u. to [1, 2] V due to a smaller output voltage range.

Table 4. Summary of the signals scaled in DACs.

Signal	Digital-to-Analog Converter (DAC)
	From	To
$v_{sa1,ref}\left(t\right)$$\mathrm{and} v_{sa1,o}\left(t\right)$	[−1, 1] p.u.	[1, 2] V
$A_{1,ref}\left(t\right)$$\mathrm{and} A_{1,o}\left(t\right)$	[0, 1] p.u.	[1, 2] V
${\theta }_{1,ref}\left(t\right)$$\mathrm{and} {\theta }_{1,o}\left(t\right)$	[0, 360] °	[1, 2] V
$f_{1,ref}\left(t\right)$$\mathrm{and} f_{1,o}\left(t\right)$	[45, 60] Hz	[1, 2] V

proposes the conversions to be used in the DACs of the emulator and digital controller to evaluate the estimated and reference signals on an oscilloscope.

2.2.3. Emulator: How to Define a Case Study

The grid voltage can be emulated mathematically by the emulator. The mathematical expression of these signals is shown in Equation (1) where the (i) amplitude, (ii) frequency, and (iii) phase can be modified to evaluate different variations in a balanced three-phase system. The emulator allows for setting the voltage ranges determined by electrical standards and regulations. In particular, the emulator considers two case studies: (i) response to amplitude changes and (ii) response to frequency changes. Both cases can be implemented in an emulated grid without harmonics and with a set of harmonics, including the 5th, 7th, and 11th components, each with 10% of the amplitude at the fundamental frequency.

Table 5. Case study 1: amplitude changes.

Time	Description	Variation
$t_0$	Amplitude step down	1.0 p.u. to 0.5 p.u.
$t_1$	Amplitude step up	0.5 p.u. to 1.0 p.u.
$t_2$	Amplitude step up	1.0 p.u. to 1.5 p.u.
$t_3$	Amplitude step down	1.5 p.u. to 0.1 p.u.
$t_4$	Amplitude step up	0.1 p.u. to 1.0 p.u.
$t_5$	Amplitude step down + Phase step change	1.0 p.u. to 0.5 p.u. 0° to 20°.

shows the references of case study 1 for amplitude and phase, considering a null initial phase shift and a fixed frequency of 50 Hz.

Table 6. Case study 2: frequency changes.

Time	Description	Variation
$t_0$	Frequency step up	50 Hz to 55 Hz
$t_1$	Frequency step down	55 Hz to 50 Hz
$t_2$	Frequency step down	50 Hz to 48 Hz
$t_3$	Frequency step up + phase step change	48 Hz to 50 Hz 0° to 20°
$t_4$	Phase step change	20° to 0°

shows the references for case study 2 with a fixed amplitude of 1 p.u. and a null initial phase shift. The reference signals for both cases are shown in Figure 8. To change the case study, such as the harmonic content, and to select the emulator reference signals (Figure 4), digital inputs can be used, as shown in

Table 7. Selection of harmonics, case study, and DAC output signals in the evaluation tool.

Variable	Value	Description
$s{w}_H\left(t\right)$	0 1	Case with harmonics Case without harmonics
${sw}_{case}\left(t\right)$	0 1	Case 1 Case 2
${sw}_{outAB}\left(t\right)$	0 1	$ou{t}_A\left(t\right)=A_{1,ref}\left(t\right)$$\mathrm{and} ou{t}_B\left(t\right)={\theta }_{1,ref}$ $ou{t}_A\left(t\right)=f_{1,ref}\left(t\right)$$\mathrm{and} ou{t}_B\left(t\right)=0.0$

.

$$\begin{array}{c}{v}_{sa}\left(t\right)=A_{a1}\cos \left(2\pi f_{1}t+{\theta }_{a1}\right) +{\sum }_n{A}_{an}\cos \left(n(2\pi f_{1}t+{\theta }_{a1})\right) \\ v_{sb}\left(t\right)=A_{b1}\cos \left(2\pi f_{1}t-{\displaystyle \frac{2}{3}}\pi +{\theta }_{b1}\right)+{\sum }_n{A}_{bn}\cos \left(n\left(2\pi f_{1}t-{\displaystyle \frac{2}{3}}\pi +{\theta }_{b1}\right)\right)\\ v_{sc}\left(t\right)=A_{c1}\cos \left(2\pi f_{1}t+{\displaystyle \frac{2}{3}}\pi +{\theta }_{c1}\right)+{\sum }_n{A}_{cn}\cos \left(n\left(2\pi f_{1}t+{\displaystyle \frac{2}{3}}\pi +{\theta }_{c1}\right)\right)\end{array}$$

(1)

2.2.4. Digital Controller: Define Synchronization Technique

The synchronization techniques can be set by the digital signal $s{w}_{tec,ab}\left(t\right)$ when multiple methods are programmed in the digital controller. For example,

Table 8. Synchronization technique selection.

Variable	Value	Description
$s{w}_{tec,a}\left(t\right) s{w}_{tec,b}\left(t\right)$	0 0	SRF-PLL
	0 1	MAF-PLL *
	1 0	CDSC-PLL *
	1 1	DSOGI-PLL with LPF

* Not tested in Section 3.2.

shows four combinations for PLL-based synchronization techniques.

2.2.5. Methods and Evaluation of Synchronization Algorithms

The evaluation tool considers the evaluation of the synchronization algorithms using indicators such as the (i) mean error (ME) and (ii) root-mean-square error (RMSE) between the reference and estimated steady-state (SS) signals, as well as the (iii) settling time ($t_s$), (iv) overshoot (OS) at step change, and (v) execution time ($t_{ex}$).

The evaluation process considers the following steps after connecting the digital controller to the emulator, selecting the algorithm and the case study to be implemented:

1.

To evaluate the emulated and estimated signals from the three-phase grid:

• Display the next signals in the oscilloscope: $v_{sa1,ref}\left(t\right)$, $v_{sa1,o}\left(t\right)$, and $v_{sa,in}\left(t\right)$;
• Obtain the instantaneous error ${∆v}_{sa1}\left(t\right)$ between $v_{sa1,o}\left(t\right)$ and $v_{sa1,ref}\left(t\right)$, and compute the steady-state ME and RMSE; ${∆v}_{sa1}\left(t\right)$ can be computed using the mathematical function of the scope (${∆v}_{sa1}\left(t\right)=v_{sa1,o}\left(t\right)-v_{sa1,ref}\left(t\right)$), while the ME and RMSE can be computed using the average value and the rms value of the channel of the mathematical function.

2.

To evaluate the reference and estimated amplitude and frequency:

• Display the next signals in the oscilloscope: $A_{1,ref}\left(t\right)$, $A_{1,o}\left(t\right)$, $f_{1,ref}\left(t\right)$, and $f_{1,o}\left(t\right)$;
• Compute $t_s$ and OS in a transient state (TS); it is possible to obtain the instantaneous error of the frequency ${∆f}_1\left(t\right)$ and/or amplitude ${∆A}_1\left(t\right)$, and to calculate the steady-state EM; ${∆f}_1\left(t\right)$ and ${∆A}_1\left(t\right)$ can be computed using the mathematical function of the scope (${∆f}_1\left(t\right)=f_{1,o}\left(t\right)-f_{1,ref}\left(t\right)$, ${∆A}_1\left(t\right)=A_{1,o}\left(t\right)-A_{1,ref}\left(t\right)$), while the ME can be computed using the average value of the channel of the mathematical function.

3.

To evaluate the reference and the estimated phase:

• Display the next signals in the oscilloscope: ${\theta }_{1,ref}\left(t\right)$, ${\theta }_{1,o}\left(t\right)$;
• Calculate the phase angle between signals; the signals ${\theta }_{1,ref}\left(t\right)$ and ${\theta }_{1,o}\left(t\right)$ vary as a sawtooth signal within the range [0, 360] °; the phase angle can be computed using the phase measurement of the oscilloscope.

4.

Evaluate the $t_{ex}$ of the synchronization algorithms:

• Display the signal in the oscilloscope: $DT\left(t\right)$;
• Use the calculation method proposed in [33], which uses a digital output to determine $t_{ex}$, keeping the output in a high state during the algorithm execution; measures the time of the high state ($t_{high}$); and subtracts the execution time from the previously determined high–low state change ($t_{down}$) (Equation (2) and Figure 9); $t_{high}$ can be computed using the positive pulse-width measurement of the oscilloscope.

$$t_{ex}=t_{high}-t_{down}$$

(2)

The oscilloscope must be configured considering the voltage range of the output signals, the methods of analysis selected, and the position of the emulated, reference, and estimated signals to be displayed.

Table 9. Proposed configurations for oscilloscope channels.

Configuration	Signal	Description	Oscilloscope Channel	V/div, Position *
always	$sync\left(t\right)$	Synchronization (trigger)	Digital input	5, div +3
I	$v_{sa1,ref}(t)$	$v_{sa1}\left(t\right)$$\mathrm{reference}, ou{t}_0\left(t\right)$	CH1	500 m, div −2
	$v_{sa1,o}\left(t\right)$	$v_{sa}\left(t\right)$$\mathrm{synchronized}, ou{t}_1\left(t\right)$	CH2
	$v_{sa}\left(t\right)$	Emulated and acquired voltage signal	CH3
II	$ou{t}_0\left(t\right)$	$v_{sa1,ref}\left(t\right)$$, A_{1,o}\left(t\right)$$, {\theta }_{1,o}\left(t\right)$	CH1	500 m, div −2
	$ou{t}_1\left(t\right)$	$v_{sa1,o}\left(t\right)$$, f_{1,o}\left(t\right)$	CH2	500 m, div −4
	$ou{t}_A\left(t\right)$	$A_{1,ref}\left(t\right)$$, {\theta }_{1,ref}\left(t\right)$	CH3	500 m, div −2
	$ou{t}_B\left(t\right)$	$f_{1,ref}\left(t\right)$	CH4	500 m, div −4
III	$DT\left(t\right)$	Execution time of synchronization technique	CH4	1.00, div −2

* The positions of each channel refer to the central horizontal axis.

proposes three configurations for a four-channel oscilloscope with digital inputs:

• Configuration I: Evaluation of the emulated and estimated signals of the three-phase grid, $v_{sa1,ref}\left(t\right)$, $v_{sa1,o}\left(t\right)$, and $v_{sa}\left(t\right)$;
• Configuration II: Evaluation of the reference and estimated amplitude, phase, and frequency;
• Configuration III: Evaluation of the execution time of the synchronization algorithms.

3. Results

To demonstrate the feasibility of the proposal, the following stages are presented: (i) the experimental implementation of the evaluation tool and (ii) the evaluation of two synchronization methods considering the proposed case studies for ideal three-phase electric systems and electrical systems with harmonic content.

3.1. Experimental Implementation of the Evaluation Tool

The evaluation tool presented in Section 2.1 (Figure 4) is implemented using the steps of the proposed methodology (Figure 5). Figure 10 shows the connection between the emulator and the digital controller, while Figure 11 shows the experimental setup used.

The digital controller is implemented on an Arduino Due board, which is an accessible platform and can be used as a digital control platform for three-phase power converters [32]. In particular, Figure 10 shows the emulated voltages $v_{sa}\left(t\right)$, $v_{sb}\left(t\right)$, and $v_{sc}\left(t\right)$ generated by the emulator, along with the output signals of the synchronization algorithms implemented in the digital controller.

In order to illustrate the performance of the proposal, Figure 12 and Figure 13 show the emulated grid signals and the reference signals generated by the emulator for different case studies. In particular, Figure 12a,b shows the emulated grid voltage $v_{sa}\left(t\right)$ and the fundamental reference voltage $v_{sa1,ref}\left(t\right)$ with amplitude 1 p.u. and a frequency of 50 Hz, without harmonic and with the presence of harmonics, respectively. Figure 12c,d shows the amplitude and frequency references for case studies 1 and 2, respectively. In case study 1, the references are programmed to change at $t_0$ in the falling edge of the signal $sync\left(t\right)$ and at $t_5$ in the rising edge. References from case study 2 are synchronized with the falling edge of $sync\left(t\right)$ at change $t_0$. Figure 12e shows the variations in the emulated voltage and reference voltage of case study 1 generated by the emulator.

Figure 13 shows the signals $v_{sa}\left(t\right)$, $v_{sa1,ref}\left(t\right)$, and ${\theta }_{1,ref}\left(t\right)$ generated in the emulator for the change $t_5$ in case study 1 and for the change $t_o$ in case study 2 (Table 5 and Table 6). The signals of case study 1 in Figure 13a show the voltage variation from a reference amplitude of 1 p.u. to 0.5 p.u. and a phase jump from 0° to 20°. On the other hand, the voltage signals in case study 2 vary in frequency from 50 Hz to 55 Hz, maintaining their amplitude at 1 p.u. and phase zero (Figure 13b).

The phase reference ${\theta }_{1,ref}\left(t\right)$ for case studies 1 and 2 is shown in Figure 13c,d, respectively. Phase ${\theta }_{1,ref}\left(t\right)$ varies as a sawtooth signal between 0° to 360°, considering frequency changes and not phase jump. The period of the signal ${\theta }_{1,ref}\left(t\right)$ varies with the change in the reference frequency from 50 Hz to 55 Hz at a time $t_0$ in case study 2.

3.2. Evaluation of Synchronization Algorithms

The results of evaluating two PLL-based synchronization techniques using the proposed evaluation tool and method are presented as examples of use. The synchronization algorithms were (a) SRF-PLL and (b) DSOGI-PLL with LPF. Figure 14 shows the operation diagrams of the synchronization algorithms implemented based on [18,21]. The algorithms were programmed using the Arduino Due board and configured according to [21]. The ADCs of the digital controller are 12-bit and work with 96 samples per cycle of the fundamental frequency. The parameters of the synchronization algorithms are $f_{grid}=50 \mathrm{H}\mathrm{z}$, $\zeta =1/\sqrt{2}$, $t_s=40 \mathrm{m}\mathrm{s}$, and a maximum grid amplitude of 1.5 p.u.

Table A1. Parameters for the digital controller.

Variable	Description	Value
n	Number of samples per fundamental cycle	96
$f_{grid}$	Fundamental grid frequency	50 Hz
PLL
$k_v$	LPF constant	222.1441
$k_i$	Integral constant	13,337
$k_p$	Proportional constant	133.3333
DSOGI-PLL with LPF
$k$	Constant	$\sqrt{2}$
$k_{v,DSOGI}$	LPF constant	157.0796

in Appendix A shows the parameters used in the digital controller.

3.2.1. Case Study 1: Amplitude Changes

Figure 15 and Figure 16 show the results of implementing the SRF-PLL and DSOGI-PLL with LPF synchronization algorithms under a power grid with amplitude changes (Table 5). Figure 15 shows the performance of the algorithms in a grid without harmonic content, allowing us (i) to evaluate the dynamic response of the estimated amplitude $A_{1,o}\left(t\right)$ and estimated frequency $f_{1,o}\left(t\right)$ when the amplitude reference $A_{1,ref}\left(t\right)$ changes in step forms (Figure 15a), (ii) to observe the instantaneous error of the estimated voltage ${∆v}_{sa1}\left(t\right)$ when the reference amplitude $v_{sa1,ref}\left(t\right)$ decreases from 1.0 p.u. to 0.5 p.u. with a phase jump of 20° a $t_5$ (Figure 15b), (iii) to compute the ME and RMSE between the reference voltage $v_{sa1,ref}\left(t\right)$ and estimated voltage $v_{sa1,o}\left(t\right)$ at SS (Figure 15c), and (iv) to determine the OS and $t_s$ from the dynamic response of the amplitude $A_{1,o}\left(t\right)$ to a step change (Figure 15d).

Figure 16 shows the performance of the algorithms in a grid with harmonic content, allowing us (i) to observe the dynamics of the amplitude and frequency (Figure 16a). In particular, for the frequency variation at $t_5\left(t\right)$, Figure 16b shows the transient response of the frequency where the OS and $t_s$ are obtained, (ii) the estimated phase ${\theta }_{1,o}\left(t\right)$, and fundamental reference ${\theta }_{1,ref}\left(t\right)$ (Figure 16c), and (iii) the signal $DT\left(t\right)$ for calculating the execution time $t_{ex}$ of the algorithms implemented in the digital controller. The execution time considers the time $t_{down}$ equal to 2.1 µs [34].

The implementation of the evaluation methods shown in Figure 15 and Figure 16 and

Table 10. Summary of evaluation methods for case 1, change in $t_0$.

Variable	Measure	SRF-PLL		DSOGI-PLL with LPF		Measure Unit
		Without Harmonics (See Figure 15)	With Harmonics (See Figure 16)	Without Harmonics (See Figure 15)	With Harmonics (See Figure 16)
$v_{sa1,o}\left(t\right)$ in a steady state (SS)	ME	11.7	10.3	12.5	12.8	mV
	RMSE	60.4	53.2	32.6	33.1	mV
$A_{1,o}\left(t\right)$ in the transient state (TS)	OS	-	-	-	-	p.u.
	$t_s$	20.2	18.2	21.8	13.2	ms
	Phase angle	16.29		20.54		°
	$t_{ex}$	33.17		63.61		µs

allows us (i) to verify the operation of the synchronization algorithms implemented in the digital controller and (ii) to know the response of the algorithms to variations in amplitude and harmonic content of 5th, 7th and 11th order. In particular, the results show (i) how the harmonic content affects the estimated frequency when using SRF-PLL (Figure 16a), (ii) a lower error of the estimated voltage in SS of time $t_5$ when using DSOGI-PLL with LPF (see the RMSE values in Table 10), and (iii) an $t_{ex}$ of the DSOGI-PLL algorithm being 91% higher than that of the SRF-PLL algorithm. The results confirm the behavior of the SRF-PLL algorithm under distorted grid conditions reported in [8].

3.2.2. Case Study 2: Frequency Changes

The dynamics of the estimated amplitude and frequency when varying the reference frequency are shown in Figure 17 and Figure 18. Figure 17 shows the results for a grid without harmonics, and Figure 18 shows the results for a grid with the harmonics content. In particular, for the variation in $t_0$, the estimated frequency can be evaluated by obtaining the OS and $t_s$ from the dynamic response (Figure 17b and Figure 18b).

Table 11. Evaluation methods in the transient state for case 2, change in $t_0$.

Variable	Measure	SRF-PLL		DSOGI-PLL with LPF		Measure Unit
		Without Harmonics (See Figure 17)	With Harmonics (See Figure 18)	Without Harmonics (See Figure 17)	With Harmonics (See Figure 18)
$f_{1,o}\left(t\right)$ in TS	OS	-	-	0.6	0.6	p.u.
	$t_s$	28.2	33.0	42.4	45.6	ms

shows ${ t}_s$ for DSOGI-PLL with LPF. The results confirm the behavior of the SRF-PLL algorithm under distorted grid conditions and the dynamics of the estimated frequency of the DSOGI-PLL algorithm reported in [8,29], respectively.

4. Conclusions

This work presents a low-cost and versatile digital evaluation tool for the experimental evaluation of synchronization techniques. The evaluation tool emulates the voltage signals of an electric grid to be acquired and processed by any digital controller capable of implementing a synchronization algorithm. The emulator also generates reference signals to evaluate the synchronization algorithms implemented in a digital controller. The cost of the evaluation tool, considering the emulator platform, is in the low range compared to other tools (Table 1), at less than USD 100.

The methodology of use presented here allows for the correct tool to be implemented and the algorithms to be evaluated when digital platforms are used. The evaluation considers steady-state and transient analyses of the voltage, frequency, and amplitude estimated by the synchronization algorithms using the OS, $t_s$, ME, and RMSE. The calculated execution time is another indicator considered in the evaluation of algorithms. The methodology is replicable on different digital platforms and allows different disturbance ranges to be set, including those defined by electrical standards and regulations.

The proposal was validated through an experimental implementation of the evaluation tool through the LAUNCHXL-F28379D platform. The emulator allows for the validation of digital synchronization algorithms such as SRF-PLL and DSOGI-PLL with LPF by implementing them in a digital controller (Arduino Due platform), varying the amplitude and the frequency and considering the harmonic content. The experimental results confirmed the performance of the algorithms reported in [8,29]. In particular, the high impact of harmonics on SRF-PLL (Figure 16a and Figure 18b) and the longer execution time of DSOGI-PPL (Table 10) were verified. The execution time of DSOGI with LPF was 91% longer than that of SRF-PLL (63.61 µs vs. 33.17 µs).