Bridgeless Buck-Boost PFC Rectifier with Positive Output Voltage

Round 1

Reviewer 1 Report

The proposed bridgeless Buck-Bust PFC rectifier with positive output voltage was designed based on the reference paper [17]. Hence, it is strongly recommended in section 5 that the performance comparison of the proposed work should be made with those of [17]. Based on these comparisons, the excellence of the proposed work can be emphasized in section 6. In this manner, the strength and weakness of the proposed work will be clearly demonstrated. The proposed work insists the excellent stable operation of the circuit. It would be very nice in section 3 to describe the stability issue on the proposed circuit, namely why the proposed circuit operates with stable conditions. In Fig. 2, there are three block diagrams of voltage divider, ADC, and FPGA. Descriptions of three block diagrams should be made in terms of some specifications, such as sampling frequency, a number of bits, voltage ratio of the voltage divider, and power consumption, and etc.

Some typos are found. For example, in the 76 line, PFGA should be corrected to FPGA. Please go through the manuscripts thoroughly to get rid of typo errors.

Author Response

Q1: The proposed bridgeless Buck-Bust PFC rectifier with positive output voltage was designed based on the reference paper [17]. Hence, it is strongly recommended in section 5 that the performance comparison of the proposed work should be made with those of [17]. Based on these comparisons, the excellence of the proposed work can be emphasized in section 6. In this manner, the strength and weakness of the proposed work will be clearly demonstrated.

Response:

Basically, there is the difference in specifications between the proposed circuit and the circuit shown in [17], the comparison is not easy. But, from the point of view of voltage gain, the former has the value of D/(1-D), locating between zero and infinity, where D is the duty cycle, and the latter has the value of 2D, locating between zero and two. This means that the former has relatively low zero crossover distortion as compared to the latter.

The above description can be seen on the last paragraph in Sec. 1 in the revised paper.

Q2: The proposed work insists the excellent stable operation of the circuit. It would be very nice in section 3 to describe the stability issue on the proposed circuit, namely why the proposed circuit operates with stable conditions.

Response:

The proportional-integral (PI) controller embedded in FPGA can make the proposed converter operated stably. The parameters of this controller are obtained by the industrial try-and-error tuning method as follows.

Step 1: Under the input nominal voltage of 110V_rms and rated output power, the integral gain k_i is first set to zero, and then the proportional gain k_p is gradually increased, so that the value of k_p stops being increased until the output voltage reaches 75% of the desired value.

Step 2: Under the same conditions, the value of k_p obtained from step 1 is fixed, and then the value of k_i is gradually increased, so that the output voltage is stabilized at the desired value.

Step 3: Under the input nominal voltage of 110V_rms but different output powers, the values of k_p and k_i are finely tuned, so that the output voltage is stabilized at the desired value for all the output power range.

Step 4: Change the input voltage levels, and repeat step 3, so that the output voltage is stabilized at the desired value for all the input voltage range and all the output power range.

The above description can be seen on the last paragraph in Sec. 1 in the revised paper.

Q3: In Fig. 2, there are three block diagrams of voltage divider, ADC, and FPGA. Descriptions of three block diagrams should be made in terms of some specifications, such as sampling frequency, a number of bits, voltage ratio of the voltage divider, and power consumption, and etc.

Response:

Figure 2 is changed to Figure 1 in the revised paper. The sampling frequency is 100kHz, synchronous with the switching frequency. The number of sampling bits out of the ADC is 10bits. The voltage ratio of the voltage divider is 3 over 80. The number of PWM signal bits out of the FPGA is 10bits. Since the power consumption of the ADC and FPGA is hard to estimate, it is not taken into consideration.

The above description can be seen on the second paragraph in Sec. 4 in the revised paper.

Q4: Some typos are found. For example, in the 76 line, PFGA should be corrected to FPGA. Please go through the manuscripts thoroughly to get rid of typo errors.

Response:

This has been corrected, and we have double checked this paper carefully.

Reviewer 2 Report

* A figure should be added showing the experimental prototype circuit with all the value of inductor, and capacitors shown, and parts name/number shown for switch, FPGA, diodes. 

*What is the output power range for this converter? Compared to ref [17], this design seem to have a much smaller range?

*Figures 10, 11, 12 should be improved. Especially the x-axis scale is very rough.  

*Measurement waveforms are shown for only one input voltage. What is the input voltage range that this circuit works? Please add more experimental results for wider range of input/output voltages. 

*Meeting the harmonic distortion requirements (IEC6100-3-2 Class C harmonics) should also be reported for wider input ranges.

* Please be more specific on the conditions and ranges where the proposed scheme works. 

Author Response

Q1: A figure should be added showing the experimental prototype circuit with all the value of inductor, and capacitors shown, and parts name/number shown for switches, diodes. 

Response:

A photo of the proposed converter is added to the revised paper. The product name for the switches S₁ and S₂ and is IXTQ88N28T. The product name for the switch S₃ is STP120NF10. The product name for the diodes D₁, D₂, D₃ and D₄ is APT30D30BCT. The product name for the diode D_o is MBR40100PT. The inductor L has a value of 59.5uH based on a CM270125 core with 18 turns. The capacitor is constructed by two paralleled Nippon Chemi-Con capacitors, 650uF//650uF.

A prototype photo can be seen in Figure 22 and the other description above can be seen on the third paragraph in Sec. 4, in the revised paper.

Q2: What is the output power range for this converter? Compared to ref [17], this design seems to have a much smaller range?

Response:

The output power range is from 22.5W to 90W. Since the output power level of the proposed rectifier is desired to drive high-power LED strings, the corresponding rated output power is lower than that of the circuit shown in [17].

Portion of the above description can be seen on the first paragraph in Sec. 4 in the revised paper.

Q3: Figures 10, 11, 12 should be improved. Especially the x-axis scale is very rough. 

Response: 

Figures 10, 11 and 12 have been changed to Figures 19, 20 and 21 in the revised paper. The four values in the x-axis correspond to four output power levels, which are 25%, 50%, 75% and 100% of the rated output power created by Microsoft Excel.

This can be seen in Figures 19, 20 and 21 in the revised paper.

Q4: Measurement waveforms are shown for only one input voltage. What is the input voltage range that this circuit works? Please add more experimental results for wider range of input/output voltages.

Response:

The input voltage range is from 90V_rms to 130V_rms with a nominal value of 110V_rms, and the output voltage is set at 80V. In addition, Figures 9 to 13 in the revised paper are measured under the input voltage of 90V_rms, whereas Figures 14 to 18 in the revised paper are measured under the input voltage of 130V_rms.

This can be seen on the first paragraph in Sec. 4, on the second paragraph in Sec. 5, and Figures 9 to 18, in the revised paper.

Q5: Meeting the harmonic distortion requirements (IEC6100-3-2 Class C harmonics) should also be reported for wider input ranges.

Response:

From Figures 5, 10 and 15 in the revised paper, it can be seen that the proposed circuit meets the requirements of IEC6100-3-2 Class C harmonics standard.

Q6: Please be more specific on the conditions and ranges where the proposed scheme works.

Response:

This can be seen on the first paragraph in Sec. 4 in the revised paper.

Round 2

Reviewer 2 Report

The questions are answered well, and the manuscript is updated as requested. 

The quality of graphs Fig. 19,20,21 can be improved. The x-axis and y-axis resolution can be more regular. 

Minor English correction is required.  

Author Response

Reponses to the Comments of Reviewer 2

Q1: The quality of graphs Fig. 19,20,21 can be improved. The x-axis and y-axis resolution can be more regular.

Response:

The axis resolution has been improved. Please see Fig. 19, 20, and 21 in the revised paper.

Q2: Minor English correction is required.

Response:

English correction has been done. Please see some text with a yellow background in the revised paper.