Inner Spacer Engineering to Improve Mechanical Stability in Channel-Release Process of Nanosheet FETs
Abstract
:1. Introduction
2. Materials and Methods
3. Results
4. Conclusions
Author Contributions
Funding
Conflicts of Interest
References
- Zhang, S. Review of Modern Field Effect Transistor Technologies for Scaling. J. Phys. Conf. Ser. 2020, 1617, 012054. [Google Scholar] [CrossRef]
- Ng, R.M.Y.; Wang, T.; Liu, F.; Zuo, X.; He, J.; Chan, M. Vertically Stacked Silicon Nanowire Transistors Fabricated by Inductive Plasma Etching and Stress-Limited Oxidation. IEEE Electron Device Lett. 2009, 30, 520–522. [Google Scholar] [CrossRef]
- Lee, S.-Y.; Kim, S.-M.; Yoon, E.-J.; Oh, C.-W.; Chung, I.; Park, D.; Kim, K. A novel multibridge-channel MOSFET (MBCFET): Fabrication technologies and characteristics. IEEE Trans. Nanotechnol. 2003, 2, 253–257. [Google Scholar] [CrossRef]
- Thomas, S. Nanosheet FETs at 3 nm. Nat. Electron. 2018, 1, 613–614. [Google Scholar] [CrossRef]
- Colinge, J.; Gao, M.; Romano-Rodriguez, A.; Maes, H.; Claeys, C. Silicon-on-insulator “gate-all-around device”. In Proceedings of the 1990 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 9–12 December 1990; pp. 595–598. [Google Scholar]
- Bera, L.K.; Nguyen, H.S.; Singh, N.; Liow, T.Y.; Huang, D.X.; Hoe, K.M.; Tung, C.H.; Fang, W.W.; Rustagi, S.C.; Jiang, Y.; et al. Three Dimensionally Stacked SiGe Nanowire Array and Gate-All-Around p-MOSFETs. In Proceedings of the 2006 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 9–13 December 2006; pp. 551–554. [Google Scholar]
- Lee, S.-Y.; Kim, S.-M.; Yoon, E.-J.; Oh, C.W.; Chung, I.; Park, D.; Kim, K. Three-Dimensional MBCFET as an Ultimate Transistor. IEEE Electron Device Lett. 2004, 25, 217–219. [Google Scholar] [CrossRef]
- Sacchetio, D.; Ben-Jamaal, M.H.; de Michelil, G.; Leblebici, Y. Fabrication and Characterization of Vertically Stacked Gate-All-Around Si Nanowire FET Arrays. In Proceedings of the 2009 Proceedings of the European Solid State Device Research Conference, Athens, Greece, 14–18 September 2009; pp. 245–248. [Google Scholar]
- Bustillo, J.; Howe, R.; Muller, R. Surface micromachining for microelectromechanical systems. Proc. IEEE 1998, 86, 1552–1574. [Google Scholar] [CrossRef] [Green Version]
- Mertens, H.; Ritzenthaler, R.; Pena, V.; Santoro, G.; Kenis, K.; Schulze, A.; Litta, E.D.; Chew, S.A.; Devriendt, K.; Demuynck, S.; et al. Vertically Stacked Gate-All-Around Si Nanowire Transistors: Key Process Optimizations and Ring Oscillator Demonstration. In Proceedings of the 2017 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2–6 December 2017; pp. 828–831. [Google Scholar]
- Loubet, N.; Kal, S.; Alix, C.; Pancharatnam, S.; Zhou, H.; Durfee, C.; Belyansky, M.; Haller, N.; Watanabe, K.; Devarajan, T.; et al. A Novel Dry Selective Etch of SiGe for the Enablement of High Performance Logic Stacked Gate-All-Around NanoSheet Devices. In Proceedings of the 2019 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 7–11 December 2019. [Google Scholar]
- Lee, B.-H.; Kang, M.-H.; Ahn, D.-C.; Park, J.-Y.; Bang, T.; Jeon, S.-B.; Hur, J.; Lee, D.; Choi, Y.-K. Vertically integrated multiple nanowire field effect transistor. Nano Lett. 2015, 15, 8056–8061. [Google Scholar] [CrossRef] [PubMed]
- Hwang, K.-M.; Park, J.-Y.; Bae, H.; Lee, S.-W.; Kim, C.-K.; Seo, M.; Im, H.; Kim, D.-H.; Kim, S.-Y.; Lee, G.-B.; et al. Nano-electromechanical Switch Based on a Physical Unclonable Function for Highly Robust and Stable Performance in Harsh Environments. ACS Nano 2016, 11, 12547–12552. [Google Scholar] [CrossRef] [PubMed]
- Loubet, N.; Hook, T.; Montanini, P.; Yeung, C.-W.; Kanakasabapathy, S.; Guillom, M.; Yamashita, T.; Zhang, J.; Miao, X.; Wang, J.; et al. Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET. In Proceedings of the 2017 Symposium on VLSI Technology, Kyoto, Japan, 5–8 June 2017; pp. T230–T231. [Google Scholar]
- Bae, G.; Bae, D.-I.; Kang, M.; Hwang, S.M.; Kim, S.S.; Seo, B.; Kwon, T.Y.; Lee, T.J.; Moon, C.; Choi, Y.M.; et al. 3 nm GAA Technology Featuring Multi-Bridge-Channel FET for Low Power and High Performance Applications. In Proceedings of the 2018 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 1–5 December 2018; pp. 28.7.1–28.7.4. [Google Scholar]
- Li, J.; Li, Y.; Zhou, N.; Xiong, W.; Wang, G.; Zhang, Q.; Du, A.; Gao, J.; Kong, Z.; Lin, H.; et al. Study of Silicon Nitride Inner Spacer Formation in Process of Gate-all-around Nano-Transistors. Nanomaterials 2020, 10, 703. [Google Scholar] [CrossRef] [PubMed]
- Kal, S.; Pereira, C.; Oniki, Y.; Holsteyns, F.; Smith, J.; Mosden, A.; Kumar, K.; Biolsi, P.; Hurd, T. Selective isotropic etching of Group IV semiconductors to enable gate all around device architectures. In Proceedings of the Surface Preparation and Cleaning Conference (SPCC), Cambridge, MA, USA, 10–11 April 2018. [Google Scholar]
- Barraud, S.; Previtali, B.; Vizioz, C.; Hartmann, J.M.; Sturm, J.; Lassarre, J.; Perrot, C.; Rodriguez, P.; Loup, V.; Magalhaes-Lucas, A.; et al. 7-Levels-Stacked Nanosheet GAA Transistors for High Performance Computing. In Proceedings of the 2020 IEEE Symposium on VLSI Technology, Honolulu, HI, USA, 16–19 June 2020; pp. 1–2. [Google Scholar]
- Zheng, X.; Wang, Q.; Zhang, R.; Ma, L.; Luan, J. Effects of aspect ratio and metal layer thickness on demoulding of metal/polymer bi-layer gratings during nanoimprinting. Sci. Rep. 2018, 8, 12720. [Google Scholar] [CrossRef] [PubMed]
- Ryu, D.; Myeong, I.; Lee, J.K.; Kang, M.; Jeon, J.; Shin, H. Investigation of Gate Sidewall Spacer Optimization From OFF-State Leakage Current Perspective in 3-nm Node Device. IEEE Trans. Electron Devices 2019, 66, 2532–2537. [Google Scholar] [CrossRef]
- Kim, S.; Kim, M.; Ryu, D.; Lee, K.; Kim, S.; Lee, J.; Lee, R.; Kim, S.; Lee, J.H.; Park, B.G. Investigation of Electrical Characteristic Behavior Induced by Channel-Release Process in Stacked Nanosheet Gate-All-Around MOSFETs. IEEE Trans. Electron Devices 2020, 67, 2648–2652. [Google Scholar] [CrossRef]
- Ryu, D.; Kim, M.; Kim, S.; Choi, Y.; Donghyun, R.; Lee, J.-H.; Park, B.-G. Design and Optimization of Triple-k Spacer Structure in Two-Stack Nanosheet FET from OFF-State Leakage Perspective. IEEE Trans. Electron Devices 2020, 67, 1317–1322. [Google Scholar] [CrossRef]
- Shen, T.; Watanabe, K.; Zhou, H.; Belyansky, M.; Struckert, E.; Zhang, J.; Greene, A.; Basker, V.; Wang, M. A new tech-nique for evaluating stacked nanosheet inner spacer TDDB reliability. In Proceedings of the 2020 IEEE International Reliability Physics Symposium (IRPS), Dallas, TX, USA, 28 April–30 May 2020; pp. 1–5. [Google Scholar]
- Yoon, J.-S.; Baek, R.-H. Device Design Guideline of 5-nm-Node FinFETs and Nanosheet FETs for Analog/RF Applications. IEEE Access 2020, 8, 189395–189403. [Google Scholar] [CrossRef]
Parameter | Value | Material |
---|---|---|
Gate Length, LG | 12 nm | Vacuum |
Channel Width, WCH | 30 nm | Si |
Channel-to-Channel Vertical Space, VSPC | 10 nm | Vacuum |
Nanosheet Thickness, TNS | 5 nm | Si |
Inner Spacer Thickness, TINN | 3 nm | Si3N4 |
Source/Drain Length, LSD | 12 nm | Si |
Source/Drain Height, HSD | 45 nm | Si |
Substrate | 100 nm× 100 nm× 30 nm | Si |
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Lee, K.-S.; Park, J.-Y. Inner Spacer Engineering to Improve Mechanical Stability in Channel-Release Process of Nanosheet FETs. Electronics 2021, 10, 1395. https://doi.org/10.3390/electronics10121395
Lee K-S, Park J-Y. Inner Spacer Engineering to Improve Mechanical Stability in Channel-Release Process of Nanosheet FETs. Electronics. 2021; 10(12):1395. https://doi.org/10.3390/electronics10121395
Chicago/Turabian StyleLee, Khwang-Sun, and Jun-Young Park. 2021. "Inner Spacer Engineering to Improve Mechanical Stability in Channel-Release Process of Nanosheet FETs" Electronics 10, no. 12: 1395. https://doi.org/10.3390/electronics10121395
APA StyleLee, K. -S., & Park, J. -Y. (2021). Inner Spacer Engineering to Improve Mechanical Stability in Channel-Release Process of Nanosheet FETs. Electronics, 10(12), 1395. https://doi.org/10.3390/electronics10121395