A Hybrid Control Scheme with Fast Transient and Low Harmonic for Boost PFC Converter

Abstract

In this study, a new control strategy was proposed to improve transient response and the input current harmonic distortion of power factor correction (PFC) regulators operating in an average current mode. The proposed technique required only two additional gain selectors and a peak detector circuit on the feedforward voltage loop and output voltage feedback loops. It provided a direct reading for the average voltage value of feedback control loops and the peak voltage of feedforward control loops, producing PFC boost regulators with fast dynamic responses and low-input current harmonic distortion. The use of digital potentiometers for directly changing the gain of control loops did not require any divider or squarer to reduce the complexity of control circuits. The operating principles and control strategies of 300 W boost PFC with the new control strategy are presented with detailed analysis and discussion. The experimental results were satisfactory.

1. Introduction

Currently, mainstream power supplies on the market are designed and developed using high-frequency switching technologies to achieve compactness and high performance. However, power switching is affected by nonlinear resistance, which leads to harmonic pollution of electrical devices and even increases the loss of transmission lines [1]. Therefore, the International Electrotechnical Commission (IEC) stipulated relevant standards for power harmonics such as the IEC 61000-3-2 standard [2].

In order for the problem of harmonic pollution to be solved, the active power factor correction (PFC) technique is the most suitable method because it increases the input power factor (PF) and reduces input current harmonic distortion [3]. Common current mode control methods include peak current control and average current control methods. Because the peak current control method is likely to be affected by noise [4] and requires slope compensation [5], the average current control method is extensively applied in switching power supply industries. As shown in Figure 1, the average current control method features current and voltage control loops [6,7]. The current control loop controls the phase difference between input current and voltages, whereas the voltage control loop regulates the direct current (DC) output voltage. Both control loops contain twice-line frequency ripples; therefore, the input currents generate second harmonic distortion. The increase in the ripple voltage increases input current harmonic distortion (total harmonic distortion; THDi). Commonly, to reduce the second harmonic effect, the voltage and current loop bandwidth are limited. However, this design drags the system transient response. In applications for light-emitting diode drivers or adapters, fast dynamic responses must be considered because, when load currents change, the output voltage frequently generates oscillation.

To achieve THDi with a fast dynamic response and reduced input current, researchers have proposed many methods [8,9,10,11,12,13,14]. Studies [8,9,10] have adopted a two-stage scheme, with the front-end and back-end schemes serving to reduce THDi and improve transient responses, respectively. In addition, increasing additional circuits in the control loop is an effective improvement method. For example, the studies [11,12,13] used a sample-and-hold (S/H) circuit to sample output feedback voltage at the zero crossing point of input voltage. Digital control technologies are other common solutions [5,14,15,16,17] because digital controllers have the advantages of accurate time control and easily increased system flexibility. For example, the average sliding control technique can be used to determine the relationship between the sliding surface and the input voltage and current and to further reduce input current harmonics [17,18,19,20]. The digital signal processors can be used as the control core and combined with the reference commands provided by phase-locked loops to avoid voltage loops from being affected by twice-line frequency. Subsequently, the voltage loop bandwidth can be increased, and PFC transient responses improved [21].

The described methods can prevent voltage loops from being affected by twice-line frequency and increase voltage loop bandwidths, addressing the defects of conventional techniques. However, the complexity of the controllers will increase, and complex algorithms and high-cost microcontrollers are required.

Moreover, one cycle control method is also a novel technique. It does not need a multiplier and the rectifying signal from input voltage; consequently, high power factor can be achieved easier with fewer components. This method will not be influenced by 120 Hz ripple from the rectified input voltage, and this benefit helps PFC to operate in wider range of the bandwidth. However, this technique requires a resettable integrator and a comparator. The switching noise will be a major concern and impact for the comparator [22].

Therefore, in this study, a new control technique was proposed that requires only two additional digital potentiometers, two analog-to-digital converters (ADCs), and a zero-point detection circuit. When the zero-point detection circuit detected input voltage zero points, ADCs are employed to sample input voltage peaks and feedback error signals. The sampling results inform the adjustment of digital circuits to change the system loop gains and complete PFC operations. This prevents the system from being affected by twice-line frequency ripples and subsequently increased the system bandwidths. In this system, the controller requires no dividers or squarer, thereby reducing the overall circuit complexity.

This paper comprises six sections. Section 2 illustrates the operating principles. Section 3 explains the control circuit design. Section 4 describes the stability analysis and compensator design. Section 5 provides the experimental results, which were verified for the 300 W boost power PFC prototype. Section 6 provides the conclusions of this study.

2. Description of the Proposed Scheme

Figure 1 shows the control circuit block diagram conventionally operating in the average current mode. In the circuit scheme, the boost converter is adopted. In terms of the simplification of the analysis, all components are assumed to be ideal. The current command i_mo decides the waveform of the input current i_in, which is composed of three main parameters, namely, rectified input current i_vac, feedforward voltage v_FF, and feedback voltage V_eao. In a steady state, the current control command i_mo can be expressed as follows:

$$i_{mo}\left(t\right)=i_{vac}\left(t\right)\times \frac{{\mathrm{V}}_{eao}}{v_{FF}^2}$$

(1)

The input voltage is a sinusoidal wave rectified through a bridge full-wave rectifier, and filter capacitors are added at the feedforward loop; therefore, V_eao and v_FF simultaneously feature DC and low-frequency 120 Hz alternating current (AC) components, as shown in Figure 2 [21]. To avoid PFC-induced input current harmonic distortion, the conventional method uses narrow bandwidth filters to inhibit low-frequency components; however, the PFC transient response speed is limited.

Figure 2 shows that, when the input voltage v_ac is at the peak or zero point, the values for the voltage error signal V_eao and the voltage feedforward signal v_FF are their respective means. Therefore, the input voltage peak and feedforward means are proportionally related. When the input voltage peak increases, the feedforward signal means increase. Conversely, when the input voltage peak decreases, the feedforward signal means decrease. In summary, the feedforward loops in this study use no filter capacitors; instead, they use peak detectors to read the feedforward signal peak voltage as the feedforward command v_FF to improve the input transient responses. For the output feedback, a 120 Hz S/H device is employed to sample the voltage error signal V_eao. This method maintains the signal V_eao at the mean value between sample intervals.

A new control scheme was proposed, as shown in Figure 3, with two gain control circuits (k_FF, k_FB), two ADCs, a peak detector, a transconductance amplifier, and an S/H circuit. The core of the controller consists of two adjustable gain modulators, which are separately located at the feedforward loop (dotted blue line) and the voltage feedback loop (dotted red line). On the feedforward loop, the voltage v_FF is generated by the input voltage v_ac through a bridge rectifier. Peak detectors sample voltage v_FF results to adjust the gain k_FF size. In addition, to eliminate the effect of output voltage ripples on voltage feedback loops, the error signals V_eao for controlling the gain k_FB size are determined by the S/H circuit with a 120-Hz sampling frequency and an ADC. Through the aforementioned analysis, the input current reference command i_mo can be rewritten as follows:

$$i_{mo}\left(t\right)=k_{\mathrm{FF}}\left(k\right)k_{\mathrm{FB}}\left(k\right)i_{vac}\left(t\right)$$

(2)

where k_FF(k) and k_FB(k) are respectively the kth feedforward gain and feedback gain. The comparison results of (1) and (2) reveal that, when $k_{\mathrm{FF}}\left(k\right)=1/v_{FF}^2$ and $k_{\mathrm{FB}}\left(k\right)=V_{eao}$, the size of the two gains can be adequately adjusted for PFC control.

According to (2), the current control command is determined by the output of the rectified line voltage peak and the voltage error amplifier. Therefore, the command can simultaneously control the converter input impedance, demonstrating resistance and stable output voltage. Subsequently, the roles of the gains k_FF(k) and k_FB(k) in this study are explained.

The gain k_FF(k) provides an open-loop modification that maintains voltage loop gain at a constant value. For example, when the output power remains unchanged (fixed k_FB) and the input voltage doubles, the peak detector readjusts the gain controller size as follows:

$$k_{\mathrm{FF}}\left(k+1\right)=\frac{1}{4}{k}_{\mathrm{FF}}\left(k\right)$$

(3)

The results reveal that, although the current i_vac is doubled, the current command i_mo(t) is halved, maintaining input power identical to that in the previous state.

The gain k_FB(k) is controlled using the voltage error amplifier. When the output power increases, the output voltage V_eao of the voltage error amplifier increases. Through the digital output of the ADC, the gain k_FB(k) is increased to change the value of the root mean square of the current command i_mo(t) to stabilize the output voltage. By contrast, when the output power decreases, the gain k_FB(k) decreases the root mean square value of the current command i_mo(t). Notably, on the basis of the twice-line frequency, sampling of the S/H circuit is conducted to obtain a point within a half-wave cycle of the supply mains to ensure that the gain k_FB(k) is unaffected by the 120 Hz output ripple voltage.

3. Control Circuit

3.1. Feedforward Loop Control Circuit

Figure 4a shows the feedforward loop control circuit scheme of the proposed new control strategy, which uses digital potentiometers and an operational amplifier to adjust the k_FF. The digital potentiometers play key roles in the circuits because they adjust the command of the gain k_FF according to the feedforward voltage v_FF peak. General digital potentiometers comprise resistor ladder and wiper. The resistor ladder is composed of equivalent series resistances, and the wiper uses digital signals to control the conduction of analog switches and set series resistance [23].

The square of feedforward voltage v_FF is used to determine the gain k_FF; therefore, the resistor ladder of the first digital potentiometer is not composed of equivalent series resistance but has an appropriate design. Figure 4b illustrates the process of feedforward control circuit adjustment for k_FF when the input voltage varies. Next, Figure 4a,b illustrates Case I, Case II, and Case III to demonstrate the operating principles of the feedforward loop control circuit. To simplify the analysis of operating principles, all components are assumed to be ideal:

Case I:

In this interval, the peak detectors begin to sample the voltage peak for v_FF as shown in Figure 4b. When the voltage peak V_m1 is determined, the ADC converts analog signals into a certain proportion of digital signals. The n-bit decoder is then used to generate D(0) to D(2ⁿ−1) outputs to set the wiper and adjust the resistance value to determine the size of the gain k_FF. The gain k_FF is calculated using the following equation.

$$k_{\mathrm{FF}}=\frac{{\mathrm{R}}_{\mathrm{WY}\text{\_}1}}{{\mathrm{R}}_{\mathrm{WX}\text{\_}1}}$$

(4)

where ${\mathrm{R}}_{\mathrm{WX}\text{\_}1}$ and ${\mathrm{R}}_{\mathrm{WY}\text{\_}1}$ respectively represent the sums of series resistance between terminals W and X and between terminals W and Y. Equation (4) indicates that the gain k_FF contains no 120-Hz ripple component subject to steady-state operation; accordingly, the input current harmonic distortion can be reduced.

Case II:

This interval is the transient region (t₁–t₄) of input voltage variation, as shown in Figure 4b. At t₁, the voltage peak begins to increase from V_m1 to V_m4, and the peak detector output voltage increases accordingly. According to the ADC output value, the decoder then controls the analog switch of the digital potentiometer to move terminal W toward terminal Y, thereby completing the operation of reducing gain k_FF. Notably, the ADC samples only at t₂, t₃, and t₄. Therefore, the gain k_FF changes once in a cycle (8.33 ms). For example, in the interval $t_1<t \le t_2$, the peak detector output voltage increases with time, but the gain k_FF only changes from k_FF1 to k_FF2.

Case III:

At t₄, the output voltage again reaches a steady state, and the input voltage peak remains identical. The digital potentiometer maintains the feedforward gain k_FF4 according to the ADC digital data, as shown in Figure 4b. Although the input voltage varies with time, the proposed control strategy enables the feedforward loop gain to be maintained at a fixed value, simplifying the design of the loop compensator.

The analysis results indicate the role of gain k_FF in PFC feedforward loop control. Subsequently, the design for gain k_FF is described. The general grid specification is between 90 and 265 V_rms. For the facilitation of the PFC operation in the specification, the gain k_FF is designed accordingly. First, the resolution of the digital potentiometer is considered. Higher resolution increases the accuracy of signals. However, each piece of data requires increasing numbers of bits, and the ADC price increases.

In this study, the ADC is only required to sample the input peak voltage; thus, the resolution has the minimum bit requirement, which can be expressed using the following equation:

$$n\ge \frac{\log \left(\frac{v_{ac\left(peak\text{\_}max\right)}-v_{ac\left(peak\text{\_}min\right)}}{\mathrm{Minimum} \mathrm{resolution} \mathrm{of} \mathrm{voltage}}\right)}{\log \left(2\right)}$$

(5)

where $v_{ac\left(peak\text{\_}max\right)}$ and $v_{ac\left(peak\text{\_}min\right)}$ respectively represent the maximum input voltage peak and minimum voltage peak. For the proposed specification, the maximum input voltage peak was 375 V, and the minimum resolution unit was 4 V. Equation (5) can be used to determine the resolution bit for $n\ge 5.90$. A 6-bit resolution ADC and a digital potentiometer with 6-bit resolution are adopted to satisfy the varying input voltage peaks corresponding to various gain k_FF sizes.

Equation (2) indicates that, in fixed output power conditions, the current command can be determined through k_FFi_vac. Figure 5 shows the proposed feedforward loop circuit scheme, which uses a 6-to-64 line decoder to decode input voltage peak results and control the conduction position of analog switches, thereby changing the current command size.

Table 1. TO-64 line decoder corresponding to input peak voltage.

VFF(p)	Inputs						Outputs
	A5	A4	A3	A2	A1	A0	D63	D62	D61	…	D1	D0
Vm64	0	0	0	0	0	0	0	0	0	…	0	1
Vm63	0	0	0	0	0	1	0	0	0	…	1	0
· · ·	· · ·	· · ·	· · ·	· · ·	· · ·	· · ·	· · ·	· · ·	· · ·	· · ·	· · ·	· · ·
Vm3	1	1	1	1	0	1	0	0	1	…	0	0
Vm2	1	1	1	1	1	0	0	1	0	…	0	0
Vm1	1	1	1	1	1	1	1	0	0	…	0	0

shows the truth table of the 6-to-64 line decoder corresponding to input peak voltage. When the input peak voltage V_FF(p) = V_mB is decoded as ((B)₁₀ = (A₅A₄A₃A₂A₁A₀)₂), D_(B) = 1 is output to drive conduction of the analog switch. The current command k_FFi_vac can be expressed as follows:

$$k_{\mathrm{FF}}{i}_{vac}=v_{FF}\left(\frac{{\mathrm{R}}_{\mathrm{S}2}+{{\displaystyle \sum }}_{\mathrm{n}=1}^{\mathrm{B}}{\mathrm{R}}_{\mathrm{n}-1}}{{\mathrm{R}}_{\mathrm{S}1}+{{\displaystyle \sum }}_{\mathrm{n}=0}^{62}{\mathrm{R}}_{\mathrm{n}}+{\mathrm{R}}_{\mathrm{S}2}}\right)$$

(6)

where B is a constant ranging from 1 to 63.

In particular, when B = 0, the current command can be expressed as follows:

$$k_{\mathrm{FF}}{i}_{vac}=v_{FF}\left(\frac{{\mathrm{R}}_{\mathrm{S}2}}{{\mathrm{R}}_{\mathrm{S}1}+{{\displaystyle \sum }}_{\mathrm{n}=0}^{62}{\mathrm{R}}_{\mathrm{n}}+{\mathrm{R}}_{\mathrm{S}2}}\right)$$

(7)

3.2. Voltage Feedback Loop Control Circuit

The main function of the voltage feedback loop is to regulate PFC and maintain a stable output voltage. In the conventional design method, the rectified input voltage is multiplied by the voltage error signal V_eao and the product divided by squared feedforward voltage v_FF. Subsequently, a current control command i_mo is generated to regulate the input current size and achieve stable output voltage control. As such, the voltage V_eao and current control command i_mo are in direct proportional relationship. Moreover, the bandwidth of voltage loops must be set far lower than that of the input line voltage because excessively wide bandwidth may cause severe input current harmonic distortion [24]. Therefore, the conventional method cannot simultaneously improve the voltage transient response and input current harmonic distortion.

To improve the shortcoming of the conventional PFC control strategy caused by the voltage loop, we adopted a digital potentiometer, an ADC, and an S/H circuit in the voltage loop, as shown in Figure 6a. When the input load varies, the voltage feedback control circuit adjusts k_FB through the process in Figure 6b. To simplify the analysis of operating principles, we assumed all components to be ideal.

State 1 (t₀–t₁):

Before t₁, PFC is performed at a steady state. The second digital potentiometer adjusts the wiper W to a suitable position according to the V_eao decoded using the ADC, as shown in Figure 6b. Because the ADC sampling time is determined by the twice-line frequency, PFC can avoid from the effect of voltage V_eao ripples.

According to Figure 6a, the resistor ladder structure of the second digital potentiometer is different from that of the first. It is composed of equivalent series resistance R_S, where a total of 2ⁿ series resistances is observed between terminal X and terminal Y. The wiper of the second potentiometer has identical functions to that of the first, namely, to set any of the 2ⁿ − 1 resistances through conduction of the analog switch.

Because the terminals X and Y of the digital potentiometer are respectively connected to the feedforward loop control command signal k_FFi_vac and the operational amplifier output end, the circuit output is expressed as follows:

$$i_{mo}\left(t\right)=k_{\mathrm{FF}}{k}_{\mathrm{FB}}{i}_{vac}\left(t\right)$$

(8)

where

$$k_{\mathrm{FB}}=\frac{{\mathrm{R}}_{\mathrm{WY}\text{\_}2}\left(\mathrm{D}\right)}{{\mathrm{R}}_{\mathrm{WX}\text{\_}2}\left(\mathrm{D}\right)}$$

$${\mathrm{R}}_{\mathrm{WX}\text{\_}2}\left(\mathrm{D}\right)=\frac{\mathrm{D}}{2^n-1}{\mathrm{R}}_{\mathrm{XY}}$$

$${\mathrm{R}}_{\mathrm{WY}\text{\_}2}\left(\mathrm{D}\right)=\frac{\left(2^n-1\right)-\mathrm{D}}{2^n-1}{\mathrm{R}}_{\mathrm{XY}}$$

Equation (8) indicates that the adjustment of gain $k_{\mathrm{FB}}$ can facilitate a proportional relationship between voltage V_eao and current control command i_mo without any 120 Hz ripple component in k_FB.

State 2 (t1~t4):

When the PFC output load is instantaneously switched from a light load (10%) to a heavy load (100%), the potential of the output voltage decreases suddenly, as shown in the dotted red line in Figure 6b. The error amplifier then compares the feedback voltage v_FB and reference voltage V_REF to obtain the required error signal V_eao. Through the error signal, the wiper of the potentiometer is adjusted to increase k_FB, thereby facilitating the rapid restoration of PFC output voltage from a lower value to the normal voltage range. Consequently, the goal of stable output voltage is achieved, as shown in Figure 6a.

In this state, although ADC sampling is conducted only at t₂, t₃, and t₄, the voltage loop bandwidth—without the effect of the output voltage ripple—can be set at a larger value compared with for the conventional method.

In addition, the output power specification must be considered in the resolution of the second digital potentiometer. Theoretically, higher ADC resolutions entail more accurate sampling results for the output power. However, due to cost limits, this study used 2% output power as the minimum resolution unit. The minimum resolution bit can be determined using (9):

$$n\ge \frac{log\left(\frac{P_{o\left(max\right)}}{P_{o\left(max\right)\times 0.02}}\right)}{log\left(2\right)}$$

(9)

where $P_{\mathrm{O}\left(max\right)}$ is the maximum output power. This study set a specification of 300 W for the maximum output power. Equation (9) indicates that the ADC resolution and the resolution of the second digital potentiometer must be 6 bits. The ADCs with 50-kHz sampling frequencies are currently common on the market. This sampling frequency is enough to increase voltage loop bandwidth. Thus, this study adopted the ADC with said sampling frequency.

Table 2. Comparison of predictive ccm average current control technology and proposed ccm average current control technology for boost pfc converter.

	Computational Complexity	Difficulty of IC Integration	PI Controller Design Requirements	Cost
Predictive CCM average current controller [25,26]	Medium	Large	No	High
Proposed CCM average current controller	Small	Small	Yes	Low

provides a comparison between the predictive CCM average current control technique and the proposed technique. It is worth noticing that the predictive CCM average current control technique performs better, but it requires a DSP to achieve the algorithm. This is much more complex, and the cost of circuit is higher. In this paper, the proposed control technique can be integrated as an IC by using the ADC and the digital potential meter structure. The cost is much lower than the control technique with DSP controller.

4. Design Criteria

Two adjustable gain modulators are used to resolve the defects of poor conventional PFC transient response. Therefore, the settings of the two digital variable resistances are critical. The selection of a compensator, digital potentiometer resolution, and gain range require consideration as well as the inductors, power switch, and diode voltage and current-withstand capacities. For the proposed PFC, we applied the following circuit parameter settings.

• Input AC voltage: v_ac = 110 V_rms~220 V_rms;
• Output DC voltage: V_O = 385 V_DC;
• Output maximum power: P_O(max) = 300 W;
• Switching frequency: f_S = 70 k_HZ.

4.1. Digital Potentiometer

In (6), the current command k_FFi_vac and feedforward voltage v_FF are crucial parameters for determining the series resistance of the first digital potentiometer. If maximum output power is set as a condition, when the input voltage reaches the maximum peak, the feedforward voltage v_FF maximum peak is V_m(max). Table 1 indicates that, D₀ = 1 for the decoder when the voltage peak is at its maximum. The minimum peak of the current command k_FFi_vac can be predicted because its peak value depends on the input current. The relationship for resistance R_S2 can be expressed as follows:

$${\mathrm{R}}_{\mathrm{S}2}=\left(\frac{k_{\mathrm{FF}}{i}_{vac\left(min\right)}}{{\mathrm{V}}_{m\left(max\right)}-k_{\mathrm{FF}}{i}_{vac\left(min\right)}}\right)\left({\mathrm{R}}_{\mathrm{S}1}+{\displaystyle \sum }_{\mathrm{n}=0}^{62}{\mathrm{R}}_{\mathrm{n}}\right)$$

(10)

By contrast, when the feedforward voltage v_FF is at the minimum peak V_m(min), the decoder D₆₃ = 1. The relationship for resistance R_S1 is expressed as follows:

$${\mathrm{R}}_{\mathrm{S}1}=\left(\frac{{\mathrm{V}}_{m\left(min\right)}-k_{\mathrm{FF}}{i}_{vac\left(max\right)}}{k_{\mathrm{FF}}{i}_{vac\left(max\right)}}\right)\left({\mathrm{R}}_{\mathrm{S}2}+{\displaystyle \sum }_{\mathrm{n}=0}^{62}{\mathrm{R}}_{\mathrm{n}}\right)$$

(11)

Reorganization of (10) and (11) yields the following relationship between the resistances R_S2 and R_S1:

$${\mathrm{R}}_{\mathrm{S}1}=\left(\frac{{\mathrm{V}}_{m\left(max\right)}}{k_{\mathrm{FF}}{i}_{vac\left(min\right)}}-\frac{{\mathrm{V}}_{m\left(max\right)}{k}_{\mathrm{FF}}{i}_{vac\left(max\right)}}{{\mathrm{V}}_{m\left(min\right)}{k}_{\mathrm{FF}}{i}_{vac\left(min\right)}}\right){\mathrm{R}}_{\mathrm{S}2}$$

(12)

Per the aforementioned specification, the maximum peak range of the input current is between 1.60 and 4.88 A. Therefore, the current command $k_{\mathrm{FF}}{i}_{vac\left(min\right)}=1.60$ A and $k_{\mathrm{FF}}{i}_{vac\left(max\right)}=4.88$ A. V_m(max) = 15 V and V_m(min) = 4.92 V. Equation (11) yields the resistance R_S2 = 10 k Ω and R_S1 = 827 Ω. In summary, the resistance of the first digital potentiometer can be determined; ${{\displaystyle \sum }}_{\mathrm{n}=0}^{62}{\mathrm{R}}_{\mathrm{n}}=82.923 \mathrm{k}\mathsf{\Omega }$.

When the input voltage v_ac peak decreases to 371 V, the feedforward voltage peak is v_FF(peak) = 14.84 V, and D₁ = 1 for the decoder. The current command peak $k_{\mathrm{FF}}{i}_{vac1}=1.617$ A, and the resistance R₀ is expressed as follows:

$${\mathrm{R}}_0=\left(\frac{k_{\mathrm{FF}}{i}_{vac1}}{v_{FF\left(peak\right)}}\right)\left({\mathrm{R}}_{\mathrm{S}1}+{\displaystyle \sum }_{\mathrm{n}=0}^{62}{\mathrm{R}}_{\mathrm{n}}+{\mathrm{R}}_{\mathrm{S}2}\right)-{\mathrm{R}}_{\mathrm{S}2}=214 \mathsf{\Omega }$$

(13)

Following this inference, we find that different input voltage peaks correspond to different resistance values, which can be plotted as shown in Figure 7. Figure 7 shows that the resistances R₀ to R₆₂ are nonlinear. Therefore, the first digital potentiometer cannot use the equivalent series resistance scheme.

The second digital potentiometer has the main function of stabilizing the output voltage. Changes in the output power of a converter generally cause output voltage errors. To enable precise adjustment of the output power, this study adopted 6-bit digital potentiometers (10 kΩ).

4.2. Inductor

For the setting of inductors, when switching frequency is 100 kHz, the duty cycle of the converter at a low voltage input is represented as D = (V_O − V_in)/V_O = 0.59. The inductor current ripple peak-to-peak value is set as 20% of the maximum line current peak. Thus, the inductance relationship is expressed as follows [17]:

$$L=\left(\frac{{\mathrm{V}}_{peak\left(min\right)}\times \mathrm{D}}{f_S\times \Delta \mathrm{I}}\right)=367 \mathsf{\mu }\mathrm{H}$$

(14)

This study set the inductance at 380 μH.

4.3. Capacitor

A crucial consideration in the selection of output capacitors is the hold-up time of the output voltage when the input energy is withdrawn. Hold-up time is typically approximately 10 ms. Although ripple current and output ripple voltage are factors that require consideration, the capacitance set with the two factors is low. Generally, the hold-up time is the main factor for consideration.

$$C_O=\left(\frac{2\times {\mathrm{P}}_{\mathrm{O}\left(max\right)}\times \Delta \mathrm{t}}{{\mathrm{V}}_{\mathrm{O}}^2-{\mathrm{V}}_{\mathrm{O}\left(min\right)}^2 }\right)=183 \mathsf{\mu }\mathrm{F}$$

(15)

where the hold-up time Δt = 10 ms and the minimum output voltage V_O(min) = 340 V.

4.4. Power Switch and Diode

The withstand current of the power switch selected must be higher than the maximum peak current of the inductor. Therefore, the withstand current of the power switch must be at least 5.36 A, and the withstand voltage must be higher than the 400-V output voltage. Diodes must feature the same level rating values as the power switch.

4.5. Design Consideration of the Compensator

Many studies have analyzed boost PFC power transfer functions [24,27]. Relevant literature has revealed that, when boost PFC is operated with resistive load, the control-to-output transfer function of the boost PFC is a one-order system. Hence, the compensator adopts PI controller for providing the phase margin for 45° to 60° and high cross-over frequency [28]. The bandwidth for the voltage loop of conventional PFC is set for 5 HZ to 10 HZ. In this paper, the proposed method can avoid the influence from the 120 HZ ripple voltage. The maximum bandwidth can be designed for 60 HZ.

5. Experimental Results

The following experimental parameters were used: input voltage 110 V_rms, output voltage V_O = 400 V, output power P_O = 40–300 W, switching frequency f = 70 kHz, output inductance L = 382 μH, and output capacitor C_O = 220 μF.

Figure 8a,b respectively represent the grid waveforms for output power P_O = 40 W and P_O = 300 W at an input voltage v_ac = 110 V_rms. The waveforms suggest that the proposed control strategy generates input line current waveforms that achieve phases almost perfectly consistent with that of the input line voltage waveforms. The results reveal that the boost PFC converter used according to the proposed method increases the system PF.

According to the experimental data, the proposed technique not only prevents effects on the PF but also resolves the ripple components of the twice-line frequency, improving the input line current THDi. These effects are obtained by measuring the input voltage in the following conditions: v_ac = 110 V_rms (P_O = 40 W) and v_ac = 110 V_rms (P_O = 300 W). The line current THDi values of both conditions were lower than 5.9%. In particular, the THDi at 300 W was 0.95%, as shown in Figure 9a,b.

The proposed method requires no additional capacitor on the feedforward loop to attenuate second harmonic waves, and the bandwidth settings of the voltage loops are higher than in conventional methods. Therefore, the proposed control strategy realizes greater input transient response than conventional methods do, as shown in Figure 10 and Figure 11. Figure 10a depicts the input transient response measured in the conditions of input current THDi = 4% and output power P_O = 300 W. According to Figure 10a, when the input voltage increased from 110 V_rms to 220 V_rm, the time for the output voltage to transfer from a transient state to a steady state was approximately 200 ms, and voltage maximum overshoot was approximately 32 V in the conventional method. The proposed method reduced the transient time by approximately 170 ms and voltage maximum overshoot by approximately 24 V, respectively, as depicted in Figure 10b. By contrast, in the same conditions, when the input voltage changed from 220 to 110 V_rms, the steady-state time and voltage maximum overshoot respectively exhibited 260-ms and 5-V differences, as shown in Figure 11a,b.

The output voltage transient responses for PFC with the use of conventional and proposed methods were compared. Figure 12a depicts the conventional PFC output voltage transient response (for output power conditions of light load 40 W and heavy load 300 W); Figure 12b depicts the new control strategy–based PFC output voltage transient response. The experimental data revealed that the conventional PFC output voltage transient response required approximately 400 ms to achieve a steady state, whereas the new PFC required approximately 200 ms. The proposed PFC was superior to the conventional one. The experimental data verified that the proposed method reduced input voltage and load transient response time.

Table 3. Newly structured pf value and Thdi.

Vin (Vrms)	VO (V)	IO (A)	PF (%)	THDi (%)
110	385	0.100	0.939	5.91
110	385	0.175	0.977	3.24
110	385	0.260	0.989	1.92
110	385	0.340	0.993	1.37
110	385	0.420	0.996	1.14
110	385	0.500	0.997	1.06
110	385	0.573	0.998	1.01
110	385	0.650	0.999	0.97
110	385	0.723	0.999	0.98

demonstrates the relevant PFC measurement data yielded by the new control technique, including the PF value and input current THDi. The optimal input current THDi was approximately 0.9%. Finally, the testing condition was set for 110 V input voltage and 300 W output power. The standard of IEC 61000-3-2 (Class-D) was applied to compare with the proposed scheme, as shown in Figure 13. From this figure, the current harmonic for odd-harmonic of the proposed structure was much lower than the standard. Hence, the proposed scheme of this paper is feasible.

6. Conclusions

The paper proposed a control technique for PFC regulator operated in average current mode. The operation principle of the control technique has been discussed in detailed. A control technique for a 300 W Boost PFC regulator was developed, and it also performed very well. The paper has two advantages from the proposed control techniques. The first is that two sets of ADC and digital potential meter are placed at the feed forward voltage loop and the output voltage loop, respectively. There is no need to place extra multiplier and square circuit for lowering the complexity. The second is that the peak voltage detector and S/H circuit can sample the average value from the feed forward voltage loop and the output voltage loop; hence, there is no influence for 120 H_Z ripple voltage. It helps to reduce the input current harmonic distortion. After that, a low frequency bandwidth filter is unnecessary. This will speed up the transient response from input voltage to the output load.