Kumar, T.M.; Reddy, K.S.; Rinaldi, S.; Parameshachari, B.D.; Arunachalam, K.
A Low Area High Speed FPGA Implementation of AES Architecture for Cryptography Application. Electronics 2021, 10, 2023.
https://doi.org/10.3390/electronics10162023
AMA Style
Kumar TM, Reddy KS, Rinaldi S, Parameshachari BD, Arunachalam K.
A Low Area High Speed FPGA Implementation of AES Architecture for Cryptography Application. Electronics. 2021; 10(16):2023.
https://doi.org/10.3390/electronics10162023
Chicago/Turabian Style
Kumar, Thanikodi Manoj, Kasarla Satish Reddy, Stefano Rinaldi, Bidare Divakarachari Parameshachari, and Kavitha Arunachalam.
2021. "A Low Area High Speed FPGA Implementation of AES Architecture for Cryptography Application" Electronics 10, no. 16: 2023.
https://doi.org/10.3390/electronics10162023
APA Style
Kumar, T. M., Reddy, K. S., Rinaldi, S., Parameshachari, B. D., & Arunachalam, K.
(2021). A Low Area High Speed FPGA Implementation of AES Architecture for Cryptography Application. Electronics, 10(16), 2023.
https://doi.org/10.3390/electronics10162023