A Five-Level Converter in a Three-Level Mode for Common-Mode Leakage Current Suppression in PV-Generation Systems

Abstract

Power generation systems (PGSs) based on renewable energy sources are finding ever-widening applications, and many researchers work on this problem. Many papers address the problem of transformerless PGSs, but few of them aimed at conducting research on structures with multilevel converter topologies as part of a PGS. In this paper a grid-tied transformerless PV-generation system based on a multilevel converter is discussed. There are common-mode leakage currents (CMLCs), which act as a parasitic factor. It is also known that common-mode voltage is the main cause of the common-mode leakage current in grid-tied PV-generation systems. This paper considers the space vector pulse-width modulation (PWM) technique, which is used to suppress or reduce common-mode leakage current. The proposed PWM technique with the reduction of common-mode leakage current for a generation system based on the multilevel converter controlled with a PWM technique was verified experimentally. The experimental results accurately confirmed the mathematical model and the compensation achieved without errors. In the experiment, there was an approximately six-fold decrease in the common-mode leakage current (10.3 mA in rejection mode and 61 mA in non-rejection current). This can lead to the elimination of CMLC in a multilevel semiconductor converter only by changing the modulation mode. This suggests the possibility of using these devices as part of transformerless generation systems. Suppression of CMLC can only be carried out by changing the PWM algorithm. Both considered topologies can implement this mode of operation. The proposed converter has a higher efficiency up to a frequency multiplicity of 2000.

1. Introduction

Today, renewable energy sources (RESs) are widespread and are becoming more attractive compared with systems based on fossil fuels such as oil, coal and gas [1]. RESs have some advantages such as harmless emissions into the environment and close location to the consumer. The use of RES technologies leads to saving conventional fossil fuels. RES technologies can be primarily attributed to photovoltaic energy production [2,3]. Power electronic systems (PESs) are the key state-of-the-art development in these RES technologies. The most important part of a PES is the power semiconductor converter. Increasing the installed power of a PV power generation system (PVPGS) leads to increased power of the semiconductor converter, which is an integral part of the system [2,3,4,5,6,7,8,9,10]. For these reasons, multilevel semiconductor converters are typically used. A PV power generation system usually has a transformer in its structure for voltage level conversion and galvanic isolation from the grid, but the use of a transformer makes the system less efficient and increases the weight and size parameters. References [11,12,13] include some research papers on transformerless PVPGSs. The elimination of the transformer leads to the following negative phenomena. The main negative phenomenon is the presence of the so-called common-mode leakage current. This current is a flow through the loops made by the parasitic elements (capacitances and inductances) [14]. The leakage current worsens the power quality and creates emergency situations, for example faults of thin-film PV panels and, as a result, a system failure. It also creates unsafe operating conditions for the personnel [15].

There are various methods of CMLC suppression: schematic and algorithmic or both. Different types of converters and their modifications can suppress CMLC for schematic methods [16], and there are various pulse-width modulation (PWM) techniques and predictive control systems for algorithmic methods [15,17]. Predictive control systems do not allow the elimination of CLMC in transformerless grid-tied PV-generation systems. Predictive control systems only reduce leakage currents and in some cases deteriorate converter efficiency.

Thus, in [18], the use of a filtering Cleack capacitor is proposed, which, if L is not taken into account, can lead to voltage resonance and nullify its introduction. A PWM technique also proposed, which can balance the capacitors of the DC link; however, it does not completely suppress the common-mode current but reduces its surges [19]. There is a technique for suppressing the common-mode leakage current in a multilevel FC converter, which has more disadvantages compared to the NPC, which is proposed in the current work [20]. Variants with the use of two-level inverters with low efficiency are proposed [21]. In addition, other works have proposed new topologies of converters [22].

The authors developed a possible solution to eliminate leakage currents in a single-phase system based on a multilevel power semiconductor converter. A schematic and algorithmic solution was reviewed in [23,24].

The paper is organized as follows. Section 2 gives a brief description of the leakage current in the PVPGS. Section 3 presents the developed converter for the PVPGS with the reduction of the leakage current. Section 4 presents the results of experimental research.

2. Leakage Current

The structure of the considered single-phase grid-tied transformerless PVPGS with the considered parasitic capacitances is illustrated in Figure 1. The elements of the PVPGS are discussed in [14,23]. The proposed converter was chosen as the one most characteristic of this problem, the solution of which this study addressed; this is discussed in more detail in Section 3. The PVPGS consists of several parts. The most important are PV modules and the voltage source converter (VSC).

The voltage source converter has two components of output voltage, $v_{dif}^{}$ and $v_{cm}$—terminals 1 and 2, as shown in Figure 1. $v_{dif}^{}$ is differential mode voltage, and $v_{cm}$ is common-mode voltage. VSC voltage components $v_{dif}^{*}$ and $v_{cm}$ are the main cause of the CMLC presence. The $v_{dif}^{*}$ component is eliminated by equalizing the parameters of output filter inductances.

Therefore, the $v_{cm}$ component produces CMLC $i_{cm}$. The circuit diagram in Figure 1 can be simplified as shown in [23,24].

The common-mode leakage current in this circuit diagram is found by Kirchhoff’s voltage law as:

$${\displaystyle \sum _{n=0}^{\infty }{\stackrel{.}{{\displaystyle I}}}_{CMLC(n)}}={\displaystyle \sum _{n=0}^{\infty }\frac{V_{cm(n)}}{\frac{1}{j{\omega }_n{C}_{pg}}+X_{L_{12}}+\frac{Z_p}{j{\omega }_{n}2C_{\lg }{Z}_p+1}}},$$

(1)

where $V_{cm(n)}$ is the common-mode voltage of the $n$-th harmonic, ${\omega }_n=2\pi fn$ is the angular frequency of the $n$-th harmonic, $f$ is the frequency of PWM and $C_{pg}$ is the equivalent parasitic capacitance (EPC) of the PV module. An average value of EPC is estimated as 100 nF per 1 kW of the power of the PV module, $Z_p$ is the parasitic loop impedance, $C_{\lg }$ is the capacitance of the EMC filter relative to the ground line and $X_{L_{12}}=j{\omega }_n\frac{L_1{L}_2}{L_1+L_2}$ is the equivalent reactance of the output inductors.

As can be seen in Equation (1), the common-mode leakage current has a polyharmonic character with different frequency content. It is defined by the spectral composition of the common-mode voltage. It is obvious that the common-mode voltage acquires the character of a constant signal and takes into account the capacitive character of the common-mode leakage current that provide a CMLC value equal to zero. This condition is achieved when the current frequency is equal to zero. The idea of synthesizing a single-phase multilevel semiconductor converter to eliminate the CMLC suppression is presented based on this condition.

Another method of common-mode leakage current suppression is achieved when $Z_p=\infty$, i.e., when breaking the leakage loop. This parameter depends on the type of grounding of the circuit, and in some cases it can be neglected. The emergence of this parasitic factor is caused by the PVPGS area, soil specific resistance, etc. It becomes clear that an elegant way to provide PVPGS operation and suppress CMLC is to achieve a zero frequency of $v_{cm}$.

The magnitude of voltage pulsation is estimated by the expression $\Delta v_{cm}=\frac{V_{dc}}{m\cdot \left(N-1\right)}$, where $V_{dc}$ is the DC-link voltage, m is number of phase legs and $N$ is the number of voltage levels. The following assumptions are made:

(a)

The common-mode voltage is calculated as a mean value of all phase to ground inverter voltages.

(b)

The voltage level of $v_{cm}$ is defined by a voltage step of the multilevel semiconductor VSI, that is $\frac{V_{dc}}{N-1}$.

3. A Single-Phase Multilevel Converter with Current Cancelation

Low-power systems (3–5 kW) usually work in single-phase AC grids. Thus, a PVPGS has a single-phase power converter. Currently, a promising direction is the use of multilevel semiconductor converters as part of the PVPGS. These topologies have a number of advantages in comparison with two-level inverters, since they can improve the quality of the generated electrical energy as part of the PVPGS without increasing the PWM frequency. By obtaining a more accurate approximation of the shape of the generated signals, it is possible to achieve a reduction in the weight, size and cost of the filters used. Multilevel converters are often used in different power generation systems. A three-level NPC converter a common type of single-phase multilevel voltage source converter (Figure 2). Neutral-point clamped (NPC) and flying capacitor (FC) multilevel converters are equivalent to each other in the quality of the generated voltage and current; however, the FC has a larger number of capacitors, which worsens its price performance. From this point of view, it is preferable to use an NPC inverter. In these multilevel VSCs, several types of PWM are usually used, namely space vector (SV) and carrier-based or hysteresis PWM. To reduce the common-mode leakage current, it is possible to use vector PWM as a way to control power converter, as proposed in [23].

In this topology the differential voltage $v_{dif}$ can take five voltage levels depending on the switching states of the multilevel semiconductor converter: $v_{dif}=\left\{V_{DC};\hspace{0.17em}\frac{V_{DC}}{2};\hspace{0.17em}0;\hspace{0.17em}-\frac{V_{DC}}{2};\hspace{0.17em}{V}_{DC}\right\}$. Common-mode voltage takes the following values: $v_{cm}=\left\{\hspace{0.17em}0;\frac{V_{DC}}{4};\hspace{0.17em}\hspace{0.17em}\frac{V_{DC}}{2};\frac{3V_{DC}}{4};V_{DC}\right\}$.

In order to eliminate CMLC common-mode voltage must be maintained at any value of $v_{cm}$ proposed previously. In [16], a three-level NPC converter operates in a two-level mode.

To work in the $N$ level output voltage mode, a $\left(2N-1\right)$ level converter is needed.

It is clear that a five-level converter is needed for three-level output voltage generation with CLMC suppression. There are two types of NPC converters that allow CLMC suppression and three-level output voltage generation [23,24]. The diagram of SV PWM state switching for both converters is shown in Figure 3. The five-level NPC converter is shown in Figure 4. A modified five-level NPC converter proposed in [23] is shown in Figure 5.

Although the modified NPC converter has a five-level topology, it still operates in the three-level mode to maintain the leakage current suppression.

In the case of the DC-link unbalance, choppers providing the voltage balancing must be implemented.

The efficiency of MOSFET transistors and SV PWM of the same switching pattern was calculated as a percentage for both converters. The results of efficiency calculation for the modified single-phase five-level semiconductor converter and for a single-phase five-level semiconductor converter were obtained for them to operate in the CMLC suppression mode (Figure 6) for different $A$ values. $A$ is the ratio between grid frequency and PWM frequency. As can be seen in Figure 6, the modified converter has an advantage in efficiency up to $A$ more than 2000.

This is explained by the fact that the modified semiconductor converter has fewer static power losses than the converter (Figure 6), and dynamic power losses are higher, up to a given frequency multiplicity. Static power losses prevail over dynamic power losses up to the range of 2000. Thus, the range up to the frequency multiplicity is the range of energy-efficient operation of the modified single-phase semiconductor converter.

4. Experiment Results

Figure 7 presents an experimental model of a single-phase PVPGS with the function of reducing the leakage current presented in Figure 8. The control system was implemented on the Discovery kit with MCU STM32F407VG. A galvanic isolated power system for drive power was made on the International Rectifier IR2153. MOSFET IRF740S was used as power transistors.

The experimental model has the following parameters:

• Rated power: 1.2 kW;
• DC-link voltage: 400 V;
• Filter inductances: L_f1 = 65 uH;
• Filter inductances: L_f2 = 72 uH;
• PV leakage capacitance: $C_{pg}=240 \mathrm{nF}$;
• Parasitic loop impedance: $Z_p=100 \Omega$;
• Capacitors $C1=C2=C3=C4=4700 \mathsf{u}\mathrm{F}$.

Figure 8 and Figure 9 represent experimental results of PVPGS operation with the modified converter.

As shown, the main common-mode current source is a common-mode voltage source. Figure 9 shows the voltage oscillograms of a five-level inverter, where it can be seen that there is an alternating common-mode voltage. As seen from Figure 8, the common-mode voltage has the character of a constant signal. This was achieved through the use of the proposed converter and control algorithm.

A new topology of a five-level semiconductor converter was synthesized, and a vector pulse-width modulation algorithm to control this converter was proposed. The experimental results confirmed the possibility of forming a common-mode voltage having a character of a constant signal and, consequently, eliminating common-mode leakage current. This in turn gives reasons to believe that the implementation of autonomous power generation systems using the proposed type of the semiconductor converter will improve the functional and operational characteristics of PVPGSs, such as electrical safety and reliability.

5. Conclusions

The structure of the PVPGS, which includes a multilevel semiconductor converter proposed by the authors, as well as the control algorithm was tested. This is the main contribution of the authors. A vector-based PWM strategy to be used in this type of multi-level semiconductor converters was also developed, which allows the formation of the common-mode voltage having the character of a constant signal. In addition, a fundamental possibility of eliminating the transformer from the structure of the generating system while maintaining the quality of the output current and voltage was demonstrated. Experimental research aimed at verifying these results was also carried out. Nevertheless, in this work there were limitations associated with the choice of the converter topologies. Similar algorithms proposed in this work are applicable in more multilevel converters, the scope of which is currently being investigated and will be presented in future works.