Compact Continuous Time Common-Mode Feedback Circuit for Low-Power, Area-Constrained Neural Recording Amplifiers

Abstract

A continuous-time common-mode feedback (CMFB) circuit for low-power, area-constrained neural recording amplifiers is proposed. The proposed CMFB circuit is compact; it can be realized by simply replacing passive components with transistors in a low-noise folded cascode operational transconductance amplifier (FC-OTA) that is one of the most widely adopted OTAs for neural recording amplifiers. The proposed CMFB also consumes no additional power, i.e., no separate CMFB amplifier is required, thus, it fits well to low-power, area-constrained multichannel neural recording amplifiers. The proposed CMFB is analyzed in the implementation of a fully differential AC-coupled neural recording amplifier and compared with that of an identical neural recording amplifier using a conventional differential difference amplifier-based CMFB in 0.18 μm CMOS technology post-layout simulations. The AC-coupled neural recording amplifier with the proposed CMFB occupies ~37% less area and consumes ~11% smaller power, providing 2.67× larger output common mode (CM) range without CM bandwidth sacrifice in the comparison.

1. Introduction

Multichannel neural recording in vivo is an essential electrophysiology tool to understand brain activities [1,2]. To simultaneously record complex activities from multiple neurons in a designated small brain area, multichannel recording amplifiers must be integrated with area- and energy-efficient manners [3,4,5]. For the last decades, integrated circuit design techniques for multichannel neural recording amplifiers to reduce power and area consumptions have been significantly progressed, resulting in ultralow power consumption (a few μW to sub-μW power consumption per channel) and high-density integration (>1000 channels in a few mm² silicon areas).

In neural recording amplifiers, an operational transconductance amplifier (OTA) is a key building block. Except for a few demonstrations where neural signals are directly sampled in a variable MOS capacitor (a parametric amplifier) [6] or an on-chip passive capacitor to get passive voltage gain [7], most neural recording amplifiers require OTAs in their implementation [8,9,10,11,12,13,14,15,16]. In particular, an AC-coupled closed-loop amplifier that is one of the most widely used neural recording amplifiers must have a high-performance OTA inside because it mainly determines the overall performance necessary for neural recordings, such as low input-referred noise (IRN), large bandwidth, low power, and small area consumptions, acceptable input/output signal ranges, and low distortion. Recent state-of-the-art neural recording amplifiers have been extensively explored by adopting various OTA topologies, such as a current mirror [8], two-stage [4,5,16,17,18], and folded cascode (FC) OTAs [9,19,20,21], in addition to the novel circuit design techniques [13,20,21,22,23]. Among the aforementioned OTA topologies, the FC-OTA has demonstrated that it reached the theoretical noise efficiency factor (NEF) limit of roughly 2 (~2.67), without adding the special circuit design techniques such as pre-amplification, current-reuse, and body biasing, and with the simple adaptation of large current scaling ratio and source degeneration [9].

Fully differential operation of neural recording amplifiers exhibits superior performance to single-ended ones, particularly when the supply voltage is reduced to achieve low-power operations. It provides large output voltage excursion even with high gain and low supply voltage (those are common in neural recordings), as well as immunity for common-mode (CM) interference such as power line noise (50/60 Hz) and removal of even-order harmonics. However, to realize the fully differential operation in amplifiers, a dedicated common-mode feedback (CMFB) circuit to set a proper output bias voltage should be incorporated. Especially, for low-power neural recording amplifier implementations where some transistors reside in the subthreshold region to maximize transconductance efficiency (g_m/I_d), a CMFB circuit with decent performance is highly required to make sure that all transistors stay in the saturation region because the operating points of transistors are not far away from the linear region, resulting in performance degradation by small deviations from the desired values.

Since a CMFB circuit usually consists of a common-mode sensor and an OTA for feedback, it results in additional power and area consumption and it becomes an implementation overhead for multichannel neural recording amplifiers. Figure 1 shows one instantiation of a fully differential FC-OTA for neural recordings, where a conventional differential difference amplifier (DDA)-based CMFB is employed. As shown, a fully differential operation in an FC-OTA requires two additional differential pairs (M_C1−4) and load transistors (M_C6−7), which consume more power (2I_BIAS) and area as compared with a single-ended version. Careful design consideration for stability is also required when employing the CMFB OTA otherwise, differential operation exhibits instability.

In this work, a compact CMFB circuit that does not require an additional OTA is presented. It simply reuses the source degeneration resistors used in the conventional low-power, low-noise FC-OTA for neural recordings to realize a CMFB function, and therefore does not need additional power and area consumption. The operation mechanism of the proposed CMFB is generic, in other words, it can be applied for any OTAs that have a CMFB control knob in their tail (or head) current sources. All performance of the proposed work is fairly compared with a conventional DDA-based CMFB in the implementation of an AC-coupled neural recording amplifier based on the same FC-OTAs. According to our analysis, a designed OTA with the proposed CMFB saves 37% area and achieves 11% power consumption reduction as compared with the circuit in Figure 1 and shows 34% fewer process variations and 2.67× wider output CM range.

2. Proposed CMFB Scheme

The proposed CMFB with the same FC-OTA in Figure 1 is depicted in Figure 2a. The bias network, except for the essential part for the explanations, is not shown for simplicity. For the output CM regulation, the proposed circuit shares the same operating principle as the circuit in Figure 2b where M_C1 and M_C2 operating in the triode region increase or decrease output current to adjust the CM output. As shown in Figure 2a, the only difference is that the sources of M₅ and M₆ are not physically connected, unlike the node x in Figure 2b, but virtually shorted by connecting the positive (V_outp) and negative (V_outn) outputs via M_R1 and M_R2 (M_R3 and M_R4). Therefore, M_R1 and M_R2 (M_R3 and M_R4) can function as both a CM sensor and an input transconductor for CM regulation (V_x ≈ V_y for CM signals). This physical separation opens up the possibility to use M_R1−M_R4 for noise reduction in M₅ and M₆, like R_S in Figure 1. R_S in Figure 1 provide a source degeneration of M₅ and M₆ (by series-series feedback), enabling a reduction of effective transconductance seen in the drain of them [9]. The part of the source degeneration circuit is redrawn in Figure 2c. The power spectral density of channel current noise of M₅ without R_S (k, Boltzmann constant; T, absolute temperature in Kelvin; and γ, a constant accounting for channel noise in a FET) is known as 4 kTγg_m5 and it is proportional to the transconductance, g_m5. By degenerating the source terminal of M₅ with R_S, as shown in Figure 2c, the effective transconductance, G_{m5, eff}, becomes:

$$G_{m5,eff}=\frac{g_{m5}}{1+\left(g_{m5}+g_{ds5}\right)R_S},$$

(1)

where g_ds5 is the drain to source conductance of M₅ and the body effect is ignored. If selecting values of g_m5 and R_S properly to satisfy g_m5R_S >> 1 and assuming g_ds5 << g_m5, G_{m5, eff} reduces into:

$$G_{m5,eff}\approx \frac{1}{R_S},$$

(2)

The channel noise of M₅ with R_S is, therefore, modified and becomes 4 kTγ/R_S (scaled by a factor of ~1/g_m5R_S), contributing to the noise reduction in the FC-OTA (recall that 1/R_S << g_m5). Besides, 1/f noise at the gate of M₅: K/[C_ox(W/L)₅f] (K, a process dependent parameter for 1/f noise and C_ox, oxide capacitance) is similarly attenuated when being reflected in the drain current. In the simulation, the IRN reduction by R_S is ~26% (~5.2 μV_rms to 3.83 μV_rms) in the neural recording amplifier using the FC-OTA in Figure 1.

In this work, M_R1 and M_R2 (or M_R3 and M_R4) play the same role with R_S as V_x and V_y are physically separated and only virtually connected for CM signals, as shown in Figure 2a. In other words, by replacing R_S with two transistors operating in the triode region and applying the outputs as shown in Figure 2a, M_R1−M_R4 can serve CM stabilization and source degeneration for DM signals, respectively. In addition, unlike the CMFB in Figure 2b where the output CM value highly depends on the process parameters [24], a CMFB servo is designed in the existing bias current circuit to accurately adjust the output CM voltage, as suggested in [25]. The voltage V_XR and V_X are given as:

$$V_{XR}\approx \frac{I_{D16}}{{\mu }_n{C}_{ox}{\left(\frac{W}{L}\right)}_{RR}\left(V_{CM}-V_{TH}\right)},V_X\approx \frac{I_{D5}}{{\mu }_n{C}_{ox}{\left(\frac{W}{L}\right)}_{R_1,R_2}\left(V_{outp}+V_{outn}-2V_{TH}\right)}$$

(3)

where μ_n and C_ox are the electron mobility and oxide capacitance, respectively. In the design, M_R1−M_R4 has the same aspect ratio and the bias current I_D5 is N times larger than I_D16 in the CMFB servo, and (W/L)_R1−R4 = (N/2)(W/L)_RR. Since the gate voltages for M₅ (and M₆), and M₁₆ are set as V_B1 (by a bias network not shown in Figure 2a), V_XR = V_X therefore:

$$\frac{1}{2}\left(V_{outp}+V_{outn}\right)=V_{CM},$$

(4)

The average of the output voltage well follows V_CM without any apparent errors if all involved transistors are well-matched.

In addition to the compact implementation and no additional power consumption, the proposed CMFB demonstrates better matching than the conventional work. The resistors, R_S in Figure 1, play as a primary source of mismatch in the output current in the OTA [9,24]. When denoting the nominal value of I_D5 and I_D6 in Figure 1 as I_D, the mismatch of ΔI_D by ΔR_S to be:

$$\frac{\Delta I_D}{I_D}\approx -\frac{\left(g_m+g_{mb}\right)R_S}{1+\left(g_m+g_{mb}\right)R_S}\frac{\Delta R_S}{R_S}\approx -\frac{\Delta R_S}{R_S},$$

(5)

where g_m and g_mb represent the nominal transconductance and body transconductance of M₅ and M₆. Since it is known that matching of resistors is very poor (~±15%) in modern CMOS processes, the passive R_S was deliberately made three times the minimum required width to reduce random mismatches into 1–2% [9], resulting in large implementation overhead. In the proposed CMFB, a small mismatch (<±1%) can be easily obtained with a reasonable implementation area because R_S is implemented with a transistor that has better matching property than a resistor. When assuming the threshold voltage variation (ΔV_TH) is the largest contribution to mismatch of a transistor [24], the resistance mismatch (ΔR_ds) by the transistors (M_R1−M_R4) is given as:

$$\frac{\Delta R_{ds}}{R_{ds}}\approx -\frac{\Delta V_{TH}}{V_{GS}-V_{TH}},$$

(6)

where R_ds is the effective resistance formed by M_R1−M_R4 and V_GS is the CM output voltage in steady-state. Since ΔV_TH (in mV) is given as [26]:

$$\Delta V_{TH}\approx \frac{A_{VTH}}{\sqrt{WL}},$$

(7)

where A_VTH ≈ 3.96 mV/√μm in the given 0.18 μm technology and W and L are the width and length of a transistor, respectively, an aspect ratio of (W/L) = 6/16 (1.5/16 and 4 multiplication) providing an equivalent resistance of 550 kΩ for each M_R1−M_R4 can easily achieve <0.5% mismatch. For comparison, if the equivalent resistance is implemented with a passive p⁺ poly resistor without silicide that gives the highest resistivity and best matching in the given process technology, the minimum area of ~900 μm² should be used for a single R_S, that is >4 times larger than the equivalent implementation using transistors. In addition, the variation of the p⁺ poly resistor is roughly ±15% according to the process datasheet, which means that an even larger area is required to achieve a comparative matching of roughly 1%. Unlike the CMFB loop in Figure 1 or any other CMFB loops employing a separate OTA, the proposed CMFB has a single dominant pole in its loop. Figure 3 shows the CMFB loops for the conventional DDA-based CMFB (Figure 3a) and the proposed CMFB (Figure 3b). While the conventional one has two poles, i.e., a dominant pole at the output and a non-dominant pole at V_p (at the output of the CMFB OTA), the proposed CMFB has only one dominant pole at the output, thus, there is no stability concern.

One disadvantage of the proposed CMFB may be a low CMFB loop gain and bandwidth due to the low input transconductance formed by the transistors (M_R1−M_R4, M_RR) in the triode region. To partially compensate for the low bandwidth, the split output capacitor network consisting of C_L1 and C_L2 was developed, as shown in Figure 2a, instead of C_L in Figure 1. In the depicted capacitor network, differential signal sees ~2C_L1 (by Miller effect) + C_L2, while the CMFB operation only does 2C_L2. Therefore, the dominant pole at the output of the proposed CMFB becomes 1/2R_outC_L2 that locates at a higher frequency than the dominant pole of the conventional CMFB, 1/2R_outC_L (C_L >> C_L2). One more apparent disadvantage in the proposed CMFB is the 1/f noise contribution from M_R1−M_R4 as compared with R_S in Figure 1 that does not generate 1/f noise. However, since the 1/f noise from M_R1−M_R4 is scaled by the transconductance of M_R1−M_R4 that is small, the overall noise contribution of the 1/f noise from M_R1−M_R4 is negligible.

3. Results and Discussion

To fairly compare the performance, two identical AC-coupled neural recording amplifiers were implemented by using the circuits in Figure 1 and Figure 2b where the same FC-OTAs are used. The design criteria for the FC-OTA were followed in [8], i.e., g_m/I_d of the input transistors is maximized (~27 V⁻¹) and transconductance of other transistors are minimized to meet the specifications for neural recordings. The schematic of the AC-coupled neural recording is shown in Figure 4. This schematic is employed from [8,27], and implemented with a closed-loop gain of 40 dB, a bandwidth of 0.05 Hz to 7.5 kHz, and IRN of ~3.8 μVrms, which meet the specifications for neural recordings [28]. In addition, C_in = 12 pF and C_fb = 120 fF were used and R_fb is a high resistance pseudo-resistor, which is ~32 TΩ, which are the values used for a commercial neural recording amplifier [29]. In addition, to emulate the real operations, the noise and output impedance specifications of a commercial regulator (LT 3021−1.2) [30] were extracted and used for the power supply, and the lumped model of a bond-wire (assumed that it is an aluminum wire with 1 mil in diameter and 30 mil in length) and the parasitics of the pads were also carefully examined.

Figure 5 shows the simulated CM voltage excursions of the two AC-coupled amplifiers while sweeping V_CM from 0 to V_DD (1.2 V here). As shown, the output CM voltage varies almost rail-to-rail, 0.12–1.08 V, while the conventional DDA-based CMFB operates properly only within one-third of the power supply, 0.42–0.79 V. That is an apparent superiority of the proposed CMFB, which comes from the chosen circuit topology. On the one hand, the conventional DDA-based CMFB limits the output swing because the differential pairs for the CMFB have smaller voltage headroom than that in the FC-OTA output branch. On the other hand, the proposed CMFB stacks the transistors, i.e., M_R1−M_R4 in the triode region at the output branch in the FC-OTA, which requires only ~70 mV additional voltage headroom. As mentioned, one known disadvantage of the proposed CMFB is low CMFB dc gain and bandwidth due to the low input transconductance of M_R1−M_R4. The loop gains (LGs) of the conventional DDA-based CMFB, the proposed CMFB with and without the split capacitor network, and the open-loop gain of the FC-OTA are described in Figure 6. Even though the dc gain of the proposed CMFB is lower than the conventional CMFB by ~2 dB, it is roughly 100 dB, showing only 15 dB degradation as compared with the FC-OTA. The relatively high dc gains in the proposed CMFB may guarantee small output CM tracking errors. The smaller bandwidth of ~190 kHz than that of ~300 kHz in the conventional CMFB may be an issue when considering large CM voltage variations commonly observed in neural recording applications. However, when applying the proposed split capacitor network, the bandwidth extends to ~633 kHz. In the implementations, 3.3 and 0.15 pF are used for C_L1 and C_L2, respectively, while 6.8 pF is assigned for C_L, thereby achieving further area saving as well (6.8 pF → 3.6 pF for output capacitors). In addition, as explained in the previous section, the proposed CMFB does not show the second pole, while the conventional CMFB has it at a frequency of ~300 kHz.

To compare large-signal CM sensitivity, transient noise simulations have been performed. For the simulation, a 1 kHz sinewave of 4 mV_pp amplitude input with a 5 kHz CM signal of amplitudes from 50 to 500 mV is applied to both amplifiers, and signal-to-noise and distortion ratios (SNDRs) for both have been calculated, as shown in Figure 7. Considering the broadband neural signals, 1 kHz, 4 mV_pp differential input may be able to cover the expected largest amplitude and speed of neural signals [28]. The fast CM with the relatively larger amplitudes than the differential one mimics the artifacts by electrical stimulation. Due to the noise from the power supplies and their finite impedance, the SNDR is degraded by ~3 dB from the ideal value (indicated in the dotted line in Figure 7). The circuit noise limited SNDR (~3.83 μVrms IRN) of ~51.34 dB is also indicated in Figure 7. On the one hand, a relatively constant SNDR was observed, up to 250 mV CM variation in the amplifier with the conventional CMFB, however, it dropped significantly for the larger CM variations. On the other hand, the amplifier with the proposed CMFB shows relatively smooth SNDR degradation, exhibiting better performance when the amplitude of the input CM voltage is larger than 250 mV.

This is because the performance of the DDA-based CMFB highly depends on that of DDA in the CMFB loop, in other words, all the transistors in the DDA must be in the saturation region for the CMFB to work properly. However, the proposed CMFB does not need any specific amplifiers for the CMFB control and only depends on the region of operation of the transistors, i.e., M_R1–M_R4. As CM voltage grows up, some M_R1−M_R4 get out of the triode region and operate in the saturation region, resulting in relatively poor CM sensing. But this shift is not abrupt, thus, the proposed CMFB shows higher SNDR even if the CM voltage gets extremely large. The early SNDR degradation of the proposed CMFB comes from the fixed aspect ratio of M_R1−M_R4 for the fair comparison by realizing 275 kΩ, which can be retarded by adjusting the aspect ratio. To compare the process and mismatch variations of the two implementations, Monte Carlo (MC) simulations were also performed. Figure 8 shows a thousand run global and mismatch MC simulation of IRN from neural recording amplifiers with the DDA-based and proposed CMFBs. The variation of the IRN from the DDA-based CMFB is 1.4× larger than that from the proposed CMFB. This may not be a meaningful outcome, but we can guess the reason as follows. Since the amplifier with the conventional DDA-based CMFB exhibits more mismatches due to R_S, the mean IRN becomes larger in the statistical mismatch simulations. In addition, the mean of the IRN from the amplifier with the conventional DDA-based CFMB shifts higher. The noise from the CMFB OTA cannot play a role in ideal differential signal processing, however there may be a finite CM to DM gain (A_CM−DM) when considering mismatches. In other words, some mismatches in the output current (including noise) may convert the CM signal from the CMFB into the DM signal, resulting in the increased IRN. Figure 9 shows the layout of the two FC OTAs with the proposed and the conventional DDA-based CMFBs. Because the proposed CMFB does not require an additional OTA and passive source degeneration (R_S), it occupies a smaller area (from 45 × 788 μm² to 45 × 488 μm²).

Table 1. Performance comparison of the neural recording amplifiers with the conventional DDA-based and proposed CMFBs, and other recent standalone CMFBs.

	Tech. Node (nm)	Input Ref. Noise (μVrms)	Max. Vin@ 1 KHz for 1% THD (mV)	1 Out CM Var. Range (%)	2Ptot (μW)	PCMFB (μW)	3 Area (mm2)	4 FoM (μA/kHz)
Proposed CMFB	180	3.87 (σ ≈ 0.0177)	5.4	80	4.82	0	0.022	0
DDA-based CMFB	180	3.91 (σ ≈ 0.0242)	4.7	30	5.42	0.6	0.035	0.0026
[32]	250	2.3–2.9	>+15	5 35	23	3	-	-
[33]	180	-	-	56	-	187	0.156	0.0002
[34]	180	-	-	5 60	-	176	5 0.003	5 0.0041

¹ Output CM variation range is a percentile for the ratio of the output CM variation range to the supply voltage. ² P_tot includes the power consumption from all components in a neural recording amplifier, such as OTA, CMFB, and bias networks, ³ MIM capacitors are not included since the active circuit can be buried under the MIM capacitors. ⁴ FoM is defined by the ratio of current consumption to unity gain bandwidth in Hz. ⁵ Estimated.

summarizes and compares the key performance of the low-power, low-noise neural recording amplifiers implemented with the conventional DDA-based CMFB and the proposed CMFB. A neural recording amplifier (similar specifications with this work) with a modified DDA-based CMFB [31] is also compared in Table 1 [32]. Moreover, some important performance metrics, such as power and area consumptions and figure of merits (FoM) [29] from the recent standalone CMFBs are added in Table 1 [33,34]. The amplifier with the proposed CMFB consumes ~11% less power and requires ~37% smaller area for implementation because there is no dedicated amplifier for the CMFB and passives for R_S are replaced by transistors. The area occupied by the output capacitors is also reduced by almost half (6.8 to 3.6 pF) due to the split capacitors and the output CM range is extended from 0.64 to 0.96 V. One of the most outstanding feature of the proposed CMFB is the lowest FoM, thanks to zero power consumption for the common-mode regulation.

4. Conclusions

A compact continuous-time CMFB circuit for low-power, area-constrained neural recording amplifiers is proposed and the performance of the proposed CMFB is analyzed in the implementation of a fully differential AC-coupled neural recording amplifier and compared with that of an identical neural recording amplifier using a conventional DDA-based CMFB in 0.18 μm CMOS technology post-layout simulation. The proposed CMFB circuit exhibits superior performance to the conventional one. It requires smaller implementation area and no additional power, resulting in ~37% area and 11% power reductions when engaged in a FC-OTA for neural recording amplifiers. In addition, the proposed CMFB facilitates 2.67× larger output CM tuning range and shows ~27% less process variation. All of the advanced performances of the proposed CMFB are preferable for power and area-constrained multichannel neural recording amplifiers.