Technique for Profiling the Cycling-Induced Oxide Trapped Charge in NAND Flash Memories

Abstract

NAND Flash memories have gained tremendous attention owing to the increasing demand for storage capacity. This implies that NAND cells need to scale continuously to maintain the pace of technological evolution. Even though NAND Flash memory technology has evolved from a traditional 2D concept toward a 3D structure, the traditional reliability problems related to the tunnel oxide continue to persist. In this paper, we review several recent techniques for separating the effects of the oxide charge and tunneling current flow on the endurance characteristics, particularly the transconductance reduction ($\Delta G_{m,max}$) statistics. A detailed analysis allows us to obtain a model based on physical measurements that captures the main features of various endurance testing procedures. The investigated phenomena and results could be useful for the development of both conventional and emerging NAND Flash memories.

1. Introduction

The emergence of NAND Flash memories has revolutionized the data storage industry over the last few decades. NAND Flash devices are used in a wide range of applications in everyday consumer electronics such as laptops, tablets, and smart wearable devices. The first NAND-structured cell was invented in 1987 by Masuoka et al. [1] at Toshiba Corp. Since then, several improvements have been proposed to lower the power consumption of these cells and to enable the contents of the entire chip to be erased at once [2,3,4,5,6,7]. More recently, its application range has been expanded such that it has become the main storage element, in that solid-state drives (SSDs) are gradually replacing hard disk drives (HDDs) [8,9]. Furthermore, it is increasingly adopted for enterprise-class storage systems. As a result, the size of NAND cells has aggressively shrunk to continuously promote this evolution. However, the ever-shrinking dimensions of the NAND cell create additional challenges in terms of the endurance and retention characteristics, such as random telegraph noise (RTN) fluctuations of the threshold voltage ($V_T$) [10,11,12], charge trapping/detrapping mechanisms [13,14,15], electron injection statistics [16,17], and $V_T$ distribution widening due to parasitic coupling effects [18,19].

Three-dimensional (3D) NAND Flash memories can be considered as a breakthrough to continue to deliver increasing bit density and reduce the bit cost [20]. 3D NAND Flash technology can utilize either floating gate (FG)- or charge trapping (CT)-type cells. Most of the 3D NAND reported to date are CT-type, owing to the simpler fabrication process [21]. The 3D NAND array architecture can be categorized into the following two classes depending on the direction of channel, as schematically shown in Figure 1: vertical gate 3D NAND architecture, which was proposed by Samsung Electronics in 2009 [22]; and vertical channel 3D NAND architecture. There are two main cell structure types that use vertical channels, namely bit cost scalable (BiCS), which was proposed by Toshiba Corp. in 2007 [23,24], and terabit cell array transistor (TCAT), which was developed by Samsung Electronics in 2009 [25]. TCAT subsequently evolved into V-NAND architecture, which has 32-stacked word line (WL) layers [26,27,28]. The industry has moved beyond 12x-stacked WL layers and achieved a 17x-stacked V-NAND [29,30]. As the memory industry transitions from planar to 3D scaling, traditional device reliability issues must still be considered. The Fowler Nordheim (FN) tunneling mechanism is commonly used in both planar and 3D NAND cells during programming and erasing (P/E) operations [31]. This mechanism leads to the formation of trap states in the tunneling oxide, and thus degrades the oxide reliability. Therefore, overcoming the reliability problems related to the oxide trap is critically important for the development of future advanced NAND Flash memories.

2. Shift in the Midgap Voltage

Generally, the midgap voltage ($\Delta V_{MG}$) during P/E operations is described by a set of two components [32]: the first is the electrostatic shift (ES) that is caused by the creation of oxide trapped charges ($Q_T$), and the other is the tunneling shift (TS) that is related to the change in the number of floating-gate charges ($Q_{FG}$). Notably, these two components mutually influence each other. The former deforms the tunneling barrier for P/E operations and thus reduces the number of storage electrons. $\Delta V_{MG}$ can be expressed as the sum of these two components.

$$\Delta V_{MG}=\frac{Q_T}{C_i}+\frac{\Delta Q_{FG}}{C_{IPD}}$$

(1)

where $C_i$ and $C_{IPD}$ are the tunneling oxide and the interpoly dielectric capacitance, respectively.

Several approaches have been proposed to separate the ES and TS values from $\Delta V_{MG}$. The first category of methods is based on indirect measurements. For example, the $\Delta V_{MG}$ in the programming and erasing states combined with tunneling-based modeling is commonly monitored to extract the $Q_T$ distribution from $Q_{FG}$ in NAND Flash memories. $Q_T$ has been presented by a sheet charge located at fixed distance from the channel in the majority of the literature [32,33,34]. Under this assumption, the tunneling current is calculated straightforwardly along the direction perpendicular to the channel by using the Wentzel–Kramers–Brillouin (WKB) approximation, as schematically shown in Figure 2a. However, as the cell sizes are aggressively shrunk to the nanoscale regime, they are adversely affected by the discrete nature of $Q_T$. Thus, we must consider all possible tunneling paths across the defective oxide [35,36], as schematically shown in Figure 2b, which increases the computational time and complexity of the method.

The second category of methods is based on the direct extraction of $Q_T$ and $Q_{FG}$ using a special test device [37,38]. The cross-sectional view and equivalent circuit of the test structure are shown in Figure 3. The device is composed of two memory cells: one with a thick tunneling oxide, referred to as a high-voltage (HV) cell, and the other with a thin tunneling oxide, referred to as a low-voltage (LV) cell. Notably, these two cells have a common FG/common control gate (CG) configuration. During P/E operations, FN tunneling occurs only through the oxide of the LV cell, thus degrading the oxide of this cell. The ES resulting from $Q_T$ is expressed as [38]:

$$\begin{gathered} \mathrm{ES}=\mathsf{\gamma }\left[\Delta V_T\left(LV\right)-\Delta V_T\left(HV\right)\right] \\ =-\frac{1}{{\epsilon }_{ox}}{{\displaystyle \int }}_0^{T_{OX}}\rho ·xdx \end{gathered}$$

(2)

where $\mathsf{\gamma }$ is the coupling ratio between the FG and CG, $\rho$ is the density of $Q_T$, and $\Delta V_T\left(LV\right)$ and $\Delta V_T\left(HV\right)$ are the $V_T$ shifts of the LV and HV cells after P/E cycles, respectively. Unfortunately, the size of the test device (L = 4 µm) is relatively large compared to that of conventional NAND Flash memories, yet it is necessary to continuously evaluate these miniaturized and new device structures. Moreover, this approach can only provide average information for a relatively large sample region rather than statistical information.

3. ∆G_{m, max} Statistics

To overcome the limitations of the above-mentioned approaches, we proposed a statistical transconductance reduction ($\Delta G_{m,max}$) method [39], which enables the extraction of $Q_T$ from $Q_{FG}$ in both 2D and 3D NAND memories.

3.1. Experimental Setup

Experiments are carried out in 2D FG-type NAND Flash memory chip. In the NAND array, a string is composed of 32-unit cells, a source-select transistor, and a drain-select transistor, as schematically shown in Figure 4a. The control gates, source-select transistors, and drain-select transistors are connected across different strings to constitute the wordline (WL), source select line (SSL), and drain select (DSL), respectively. The strings are connected to a common sourceline (SL) and bitlines (BLs). The channel length (L) and width (W) are both 42 mm, and the tunneling oxide thickness ($T_{ox}$) is 8 nm. The measurement scheme was as follows: the program operation is performed by adopting the incremental step pulse programming (ISPP) technique [40] with a starting CG voltage ($V_{CG,0}$) in increments of 0.2 V with a duration of 10 µs, as schematically shown in Figure 4b, driving the selected cells to the desired $V_T$ level. The erase operation is performed on blocks by adopting the incremental step pulse erasing (ISPE; similar to the ISPP) technique. Because it is not possible to apply high negative voltages in NAND chips, a high positive voltage is applied to the p-well. As a result, all cells in the block were erased simultaneously. During the read operation, the CG gate voltage was swept from 0 V to 5 V to harvest the maximum transconductance reduction ($\Delta G_{m,max}$). Figure 5a shows the $I_D-V_{CG}$ characteristics of the 200 randomly selected cells on WL15 in NAND strings before cycling and after 1 k, 3 k, and 30 k P/E cycles, respectively. Then, the corresponding $\Delta G_{m,max}$ distribution can be obtained, as shown in Figure 5b. Notably, the endurance test and $\Delta G_{m,max}$ monitoring were performed at room temperature. The mean value of $\Delta G_{m,max}$ (${\overline{\Delta G}}_{m,max}$) is clearly observed to increase, and the distribution to become wider, as the number of cycles increases. This suggests that the $\Delta G_{m,max}$ distribution will be a good parameter for evaluating the oxide degradation.

3.2. Simulation Methodology

Monte Carlo simulations have been used in an attempt to extract information about $Q_T$ from the measured $\Delta G_{m,max}$ distribution. A NAND string can be modeled to have a selected cell with equivalent source and drain resistances ($R_S$ and $R_D$), as shown in Figure 6a. The equivalent $R_S$ and $R_D$ can be extracted from the monitoring of the transconductance of the read cells for different positions along the NAND string [41]. The equivalent $R_S$ and $R_D$ are 130 kΩ and 138.2 kΩ, respectively. The TCAD simulations used a 3D drift-diffusion equation and coupled with the Shockley–Read–Hall model for generation/recombination and mobility models (including the electric field dependence, doping-dependent modification, and surface mobility degradation). To determine the ${\overline{\Delta G}}_{m,max}$ statistics accurately, the simulated $I_D-V_{CG}$ characteristic of the fresh cell is calibrated with experimental data at a probability level $p=50\%$, as shown in Figure 6b. The simulation was in good agreement with the experimental results. After calibrating the equivalent resistances, the Monte-Carlo-based method was adopted to evaluate the concentration of $Q_T$ ($Q_T^C$) after P/E cycles, as schematically shown in Figure 7. The step-by-step procedure is as follows: First, discrete $Q_T$ is randomly generated following a uniform distribution in a cuboid volume $420 \mathrm{nm} \times 840 \mathrm{nm} \times 8 \mathrm{nm}$ in size (i.e., $20 \mathrm{L} \times 10 \mathrm{W} \times T_{ox}$), with an equivalent $Q_T^C$. Notably, the discrete $Q_T$ is treated as a negative point charge corresponding to one electron because the electron mobility is degraded by the Coulomb repulsion.

Second, the cuboid is partitioned into 200 sub-cuboids and then mapped into the tunneling oxide region. Thus, the numbers of discrete $Q_T$ in these 200 cases approximately follow a Poisson distribution, as shown in Figure 7. Finally, a comparison of the simulated and measured $\Delta G_{m,max}$ statistics allowed us to evaluate the $Q_T^C$ during P/E cycles.

Moreover, even though the simulation does not directly account for interface trap ($D_{it}$) generation, the effect thereof is reflected in the model. The measured $I_D-V_{CG}$ characteristics indicated that the transconductance reached a maximum when $V_{CG}$ slightly exceeded $V_T$; therefore, the occupied $D_{it}$ can be considered as a fixed $Q_T$ located at the silicon/oxide interface because the bending of the surface potential remains almost unchanged [42] (see Figure 8).

4. Endurance Characteristics

4.1. 𝑄𝑇 Extraction

Figure 9 indicates that simulations can reproduce the experimental results satisfactorily, where the extracted equivalent $Q_T^C$ for 1 k, 10 k, and 30 k P/E cycles are $2.6\times {10}^{18} {\mathrm{cm}}^{-3}$, $5\times {10}^{18} {\mathrm{cm}}^{-3}$, and $1.9\times {10}^{19} {\mathrm{cm}}^{-3}$, respectively. Furthermore, the proposed approach can be extended to include the array effect on $\Delta G_{m,max}$ statistics. Figure 10a shows the $\Delta G_{m,max}$ distribution as a function of the position of the WLs in a NAND string after 10 k P/E cycles. The simulations correspond well with the measurements when the following appropriate parameters are adopted: WL₁, $R_S=16.3 \mathrm{k}\mathsf{\Omega }$ and $R_D=251.9 \mathrm{k}\mathsf{\Omega }$; WL₁₅, $R_S=130 \mathrm{k}\mathsf{\Omega }$ and $R_D=138.1 \mathrm{k}\mathsf{\Omega }$; WL₃₀, $R_S=251.7 \mathrm{k}\mathsf{\Omega }$ and $R_D=16.3 \mathrm{k}\mathsf{\Omega }$. Clearly, $R_S$ increases as the position of the WLs changes from WL₀ to WL₃₁ owing to the increase in the number of pass cells. Figure 10b shows the $\Delta G_{m,max}$ distribution as a function of $V_{pass}$ after 10 k cycles. Again, a good agreement between the simulation and experimental results is found. The equivalent resistances of the pass cells are $8.2 \mathrm{k}\mathsf{\Omega }/\mathrm{cell}$, $6.5 \mathrm{k}\mathsf{\Omega }/\mathrm{cell}$, and $5.1 \mathrm{k}\mathsf{\Omega }/\mathrm{cell}$ for $V_{pass}$ of 4 V, 5 V, and 6 V, respectively. It is clear that the pass-cell bias with a higher $V_{pass}$ has a smaller equivalent resistance but a larger $\Delta G_{m,max}$. As a final verification, the $\Delta G_{m,max}$ statistics of two different $V_T$ levels of the read cells were compared under the same cycling conditions. As shown in Figure 10c, the $\Delta G_{m,max}$ distributions almost overlap, indicating that $Q_{FG}$ causes a simple parallel shift of the $I_D-V_{CG}$ curve.

4.2. Endurance Degradation Model

We start this section with a description of an endurance degradation model that captures the features of the measurement. The evolution of $Q_T^C$ can be conveniently described by the following modified power-law equation [39]:

$$Q_T^C=\frac{Q_0}{1+{\left(k·N\right)}^{-\alpha }}$$

(3)

$$k=k_0·\exp \left(-E_{A,G}/k_{B}T\right)$$

(4)

where $Q_0$ is the saturated value of $Q_T^C$, k is the reaction constant, N is the number of P/E cycles, $\mathsf{\alpha }$ is the exponential coefficient, $E_{A,G}$ is the activation energy of $Q_T$ creation, and $k_{B}T$ is the thermal energy. Figure 11 compares the results obtained with the endurance model and with the experimental results. The adopted parameters are as follows: $Q_0=1.5\times {10}^{20} {\mathrm{cm}}^{-3}$, $k=1.0\times {10}^{-6}$, and $\mathsf{\alpha }=0.58$. When N is small ($\le 30$k cycles), the exponential term in Equation (3) is much greater than 1, and Equation (3) can simply be expressed as a power law. On the other hand, when N is large ($>30 \mathrm{k}$ cycles), $Q_T^C$ gradually approaches the saturated value $Q_0$. Overall, the proposed model is able to successfully describe the endurance characteristics over a wide range of N (up to 100 k cycles). Notably, $Q_0$ is supposed to be related to the process condition, which determines the amount of weak Si-O or Si-H bonds that can be broken [43,44].

To evaluate $E_{A,G}$ in Equation (4), we performed the experiments at various cycling temperatures. Figure 12 shows that $\Delta G_{m,max}$ increases as the cycling temperature ($T_{cyc}$) increases, suggesting that a higher $T_{cyc}$ causes more oxide damage. The temperature-accelerated $Q_T$ evaluations can be derived by using Equations (3) and (4) as follows [39]:

$$Q_T^C\left(T_{cyc}\right)=Q_T^C\left(T_R\right)·exp\left[\alpha ·E_{A,G}\left(\frac{1}{k_B{T}_R}-\frac{1}{k_B{T}_H}\right)\right]$$

(5)

where $T_R$ is the cycling performed at room temperature. A good linear relationship between the logarithm of $Q_T^C$ and the reciprocal temperature was observed, and $E_{A,G}$ was evaluated, as shown in Figure 13. Ultimately, the theoretical result fitted the experimental results well, and the yield $E_{A,G}$ was approximately 100 mV, which agreed with that obtained by monitoring the stress-induced gate leakage current [13,45,46].

4.3. Effect of the Time Delay between P/E Cycles

Reportedly, the time delay ($t_{wait}$) between P/E cycles is an important factor that affects the endurance characteristics [47,48,49,50,51]. Figure 14 shows that the $\Delta G_{m,max}$ statistics become larger as $t_{wait}$ increases when the endurance test is performed at $T_R$; however, when $T_{cyc}$ increases to 85 $℃$, the trend is completely the opposite due to recovery from oxide damage through thermal excitation. This suggests that, at high $T_{cyc}$, the endurance model should not only take into consideration the creation of damage but also the recovery from damage. The time-dependent damage recovery during $t_{wait}$ can be described by a rate equation given by [52,53]

$$f=exp\left(-t_{wait}/\tau \right)$$

(6)

$$={\tau }_0·\exp \left(E_{A,R}/k_B{T}_{cyc}\right)$$

(7)

where $f$ is the occupation function, $\tau$ is the time constant, and $E_{A,R}$ is the activation energy for the recovery from the oxide damage. Therefore, Equation (3) can be rewritten as follows [37]:

$$Q_T^C=\frac{Q_0}{1+{\left(k·N\right)}^{-\alpha }}·f$$

(8)

when $t_{wait}$ is sufficiently short, for example, 0.1 s, Equation (8) tends to Equation (3) because the mechanism according to which recovery from oxide damage takes place plays a negligible role. Accordingly, we can extract the parameters (i.e.,$Q_0$, $\mathsf{\alpha }$, $k_0$, and $E_{A,G}$) by using the approach described in Section 4.2. However, when $t_{wait}$ becomes longer, the damage creation and recovery effects are mixed, which complicates the simultaneous extraction of $E_{A,G}$ and $E_{A,R}$. To simplify the situation, we assume that under the condition of $T_{cyc}=25 ℃$, Equation (8) approaches Equation (3) because the thermal excitation of $Q_T$ is not noticeable. This allows us to evaluate the $E_{A,G}$ for longer $t_{wait}$ values of 2 s and 4 s. Figure 15a shows that, by calibrating the $E_{A,G}$ values, Equation (3) can reproduce the characteristics of the extracted $Q_T^C$ with different $t_{wait}$ values. The relationship between the logarithm of $t_{wait}$ and $E_{A,G}$ is linear, as shown in Figure 15b. Moreover, $E_{A,G}$ is in the approximate range of 60–100 meV, which agrees with the results obtained by monitoring the $V_T$ transients after experiments at different $T_{cyc}$ [13]. Once the value of $E_{A,G}$ is determined for different values of $t_{wait}$, the remaining parameters $E_{A,R}$ can be determined by using the change rate of the celebrated $\tau$ at different $T_{cyc}$. Figure 16 shows the experimental measurements fit the curve calculated with Equation (8).

Clearly, if the damage-recovery mechanism is not taken into account, Equation (3) overestimates the experiment, and the discrepancy between them increases with $t_{wait}$. The optimized $\tau$ values were 150 s, 22 s, and 12 s for $T_{cyc}$ of 25 $℃$, 55 $℃$, and 85 $℃$, respectively. Figure 17 shows that the relationship between the logarithm of $\mathsf{\tau }$ and the reciprocal temperature is linear, and $E_{A,R}\simeq 0.4 eV$ is obtained. Notably, $E_{A,R}\simeq 0.4 eV$ is similar to the values reported in the literature for charge detrapping through thermal emission [54]. It is also easily verifiable that the assumption that $f$ approaches one under the condition of $T_{cyc}$ of 25 $℃$ and $t_{wait}$ of 0.1 s is satisfied.

Although the above-mentioned model successfully describes the endurance characteristics, it still does not account for certain features according to more recent research [55]. A comparative analysis of the respective influence of $t_{wait}$ from program to erase (P-to-E) and of that from erase to program (E-to-P) on the median $\Delta G_{m,max}$ (${\overline{\Delta G}}_{m,max}$) after 30 k P/E cycles was reported [55] and is plotted in Figure 18, normalized to its initial value ($G_{m0,max}$). The E-to-P $t_{wait}$ clearly had a more significant impact on the normalized ${\overline{\Delta G}}_{m,max}$ than P-to-E $t_{wait}$. Moreover, it is also shown that the normalized ${\overline{\Delta G}}_{m,max}$ increases as $V_{CG,0}$ increases. As a result, adopting ISPP with a lower $V_{CG,0}$ would be better for improving the oxide quality. The physical mechanism is graphically illustrated in Figure 19. Energetic electrons injected from the cathode result in anode hole injection during the P/E operations. During E-to-P $t_{wait}$, these holes drift near the silicon surface, where they recombine with channel electrons [48,56]. This could create additional trap states, and subsequently, these traps are occupied by electrons.

5. Conclusions

A method for characterizing the endurance characteristics of NAND Flash memories by monitoring the $\Delta G_{m,max}$ statistics is described. The discrete $Q_T$, gradually generated with P/E cycles, results in the reduction of $\Delta G_{m,max}$, and broadening of the distribution. Based on Monte Carlo simulations, an analytical model for the generation of $Q_T$, including the effects of $T_{cyc}$ and $t_{wait}$, is then described. The model represents a powerful tool for the investigation and predictive analysis of next-generation NAND Flash technologies.