A 3.95 ppm/°C 7.5 μW Second-Order Curvature Compensated Bandgap Reference in 0.11 μm CMOS

Abstract

In order to meet the requirements of modern portable electronics for high accuracy and low power consumption of bandgap reference circuits, a new low-voltage bandgap reference with a second-order compensated circuit at 1.8 V is proposed. It features a new self-biased fully symmetric differential operational amplifier circuit with the help of split transistors for achieving low power consumption and high accuracy; by adding a new sub-threshold compensated circuit. The results of simulation show that the temperature coefficient of the second-order circuit is 3.95 ppm/°C in the temperature range of −40 to 125 °C, and the power consumption is only 7.5 μW; this meets both the requirements of high precision and low power consumption. At the same time, the output noise voltage of the design is less than 30 μV/sqrt (Hz) at a frequency of 100 Hz, and the low-frequency supply voltage rejection ratio is −103 dB@100 Hz; these are acceptable for bandgap reference circuits.

1. Introduction

BGR circuits have recently seen increased use in analog integrated circuits, particularly in linear regulators (LDO), analog to digital converters (A/D), and digital to analog converters (D/A). The resolution and conversion speed of these circuit modules are significantly impacted by the precision of the BGR circuit; in addition, the life of these circuit modules is impacted by the power consumption. However, conventional BGR circuits have shortcomings in terms of accuracy and power consumption [1,2,3].

Firstly, in terms of power consumption, operational amplifiers are necessary for traditional BGR circuits; which account for the majority of the circuit’s power. There are a variety of second-order operational amplifiers that are used, including the traditional second-order CMOS operational amplifiers [4]; folding common-source and common-gate operational amplifiers [5]; and rail-to-rail operational amplifiers [6]. Unfortunately, they all share one thing in common: in order for the operational amplifier to function properly, they require a bias circuit to supply the bias voltage; this increases the excess power consumption.

Second, in terms of accuracy, various temperature compensation techniques for the BGR circuits have been developed in recent years; for example, the segmented temperature compensation circuit by compensating the curvature in different temperature ranges. The circuit structure is complex, so that it leads to the power consumption being increased [7,8]; while also causing the overall stability of the circuit to be affected by the external environment. The compensation using different temperature coefficient resistors is more influenced by the process and less stable [9,10]. The BGR circuit has an exponential compensation and converts by obtaining a compensation current related to the absolute temperature exponentially [11,12]. Then, the current is converted and superimposed on the first-order BGR circuit. Although a higher power supply rejection ratio (PSRR) can be obtained, the circuit power consumption is large.

By enhancing the traditional BGR circuit and simultaneously constructing a new sub-threshold kind of compensation circuit, this research addresses both power consumption and accuracy. In the proposed BGR circuit, the self-biased fully symmetric differential operational amplifier is elevated to do away with the requirement for a bias circuit that supplies the bias voltage. In the meantime, the NMOS transistor drain–source current is converted to the compensated voltage when the transistor is functioning in the sub-threshold region; this forms the new compensation circuit. By the way, the PSRR and noise are improved by using the negative feedback circuit structure; while the common-source and common-gate structures are employed to lessen the impact of power supply disturbances.

The rest of this paper is organized as follows: the proposed BGR circuit is discussed in Section 2; Section 3 shows the simulation and measurement results; and the conclusion is given in Section 4.

2. Proposed Design

A conventional first-order BGR circuit is shown in Figure 1: the difference between the base-emitter voltages of two triodes, Q1 and Q2 ($\Delta V_{BE}$), with a temperature coefficient that is positive; and the base-emitter voltage of a triode transistor ($V_{BE}$), with a temperature coefficient that is negative; these are superimposed with appropriate weights in the hope of obtaining a zero TC [13].

The base-emitter voltage of $V_{BE}$:

$$V_{BE}=Vgo-\frac{T}{T_o}(Vgo-V_{BE0})-(\eta -\delta )V_T\ln \frac{T}{T_O}$$

(1)

where $Vgo$ is the bandgap voltage of silicon at 0 K with a value of about 1.2 V [14]; $T_0$ is the specified reference temperature; $V_{BE0}$ represents the base-emitter voltage of the bipolar transistor ($V_{BE}$) at $T_0$; $\eta$ is the order of temperature dependence of the collector current; and $\delta$ is a temperature-independent and process-dependent constant.

To obtain a lower TC, the nonlinear term of Equation (1) must be compensated. A new principle of the second-order compensation is shown in Figure 2; the curve of the first-order output voltage ($Vref$) versus temperature is an open-down curve which means that the temperature coefficient has a positive value at low temperatures [15,16] and a negative value at high temperatures. The voltage $V_{CT}$ is then used to compensate for the high temperature region of the $Vref$. Therefore, the output voltage of the second-order circuit ($V_{REF}$) with a lower TC is obtained. The final formula for $V_{REF}$ is as follows:

$$V_{REF}=V_{\mathrm{ref}}+V_{CT}=VBE1+\frac{kT\ln 8}{\mathrm{q}{R}_1}(R_1+R_2)+VCT$$

(2)

where $k$ is Boltzmann’s constant; $T$ is thermodynamic temperature; $q$ is the electronic charge; and the effective area ratio of the emitters of the triode Q1 and Q2 is 8:1.

Based on the above principle of the compensation design, the proposed second-order BGR circuit consists of a first-order BGR, a compensated circuit, and a start-up circuit. The transistors MP21, MP22, MP25, and MP26 form a common-source and common-gate structure to improve the PSRR of the BGR circuit; this is shown in Figure 3. The power consumption of the temperature compensation circuit is reduced by adjusting the magnitude of the aspect ratio of MN12, MN13, and the resistance value of R5. At the same time, the transistors, MN12 and MN13, are operated in the sub-threshold region. Since the current flowing in the sub-threshold region is not in the same order of magnitude as the current flowing in the saturation region, the current flowing in the sub-threshold region is reduced by several times. The term for a current that operates in the sub-threshold region:

$$I_{DS}=I_O\frac{W}{L}\exp (\frac{V_{GS}-V_{th}}{\zeta V_T})[1-\exp (-\frac{V_{DS}}{V_T})]$$

(3)

where $I_O=nu{C}_{ox}{V}_T^2$ is the related parameters of process art; $n$ is the sub-threshold slope factor; $u$ is the migration rate; $C_{ox}$ is the capacitance per unit area of the gate oxide layer; $V_T=\frac{kT}{q}$ is the thermal voltage; $q$ is the charge of the electron; $k$ is the Boltzmann constant; $T$ is the thermodynamic temperature; $W/L$ is the aspect ratio of the MOS transistor; $V_{GS}$ is the gate source voltage of the MOS transistor [17,18]; $\zeta$ is a non-ideal factor; and $Vth$ is the threshold voltage of the MOS transistor.

Because of $V_{DS}>>V_T$, $\exp (-\frac{V_{DS}}{V_T})$ can be ignored. To simplify the formula, the complex part of which is selected as a parameter $\phi$:

$$\phi =\frac{q(V_{GS}-V_{th})}{\zeta K}$$

(4)

Then, Equation (3) is subjected to the Laurent expansion:

$$I_{DS}=nu{C}_{ox}\frac{W}{L}{K}^2\frac{T^2}{q^2}(1+\frac{\phi }{T}+\frac{{\phi }^2}{2T^2})$$

(5)

At the high temperature, the difference in voltage is generated across resistor R₇; resulting in a compensation current $I_{CT}$ flowing into the first-order BGR circuit. Then, $V_{CT}$ is expressed as the following equation:

$$V_{CT}=I_{CT}(R_1+R_2+2R_4)=(\frac{I_{DS}{R}_6-V_{REF}}{R_7})(R_1+R_2+2R_4)$$

(6)

when $I_{DS}{R}_6$ is greater than $V_{REF}$; the current $I_{CT}$ is drawn into the first-order BGR circuit. Combining Equations (2) and (6), the following equation can be obtained:

$$V_{REF}=VBE1+(\frac{I_{DS}{R}_6-V_{REF}}{R_7}+\frac{V_T\ln 8}{R_1})(R_1+R_2+2R_4)$$

(7)

The higher order temperature term is subjected to Taylor’s formula expansion in Equation (1):

$$V_T\ln \frac{T}{T_O}=V_{T}T[(\frac{T}{T_O}-1)-\frac{1}{2}{(\frac{T}{T_O}-1)}^2+\frac{1}{3}{(\frac{T}{T_O}-1)}^3\dots ]$$

(8)

After Taylor’s formula is expanded, the effect of the later higher order terms becomes smaller and smaller about Equation (8); thus, simply consider the first term:

$$V_T\ln \frac{T}{T_O}\approx V_{T}T(\frac{T}{T_O}-1)$$

(9)

Combining Equations (1) and (9), the following equation can be obtained:

$$\begin{array}{l}{V}_{REF}=\frac{R_7}{R_7+R_1+R_2+2R_{{}_4}}[Vgo-\frac{T}{T_O}(Vgo-VBEO)-(\eta -\delta )\frac{KT}{q}(\frac{T}{T_O}-1)+\frac{K^2}{q^2}nu{C}_{ox}\\ \frac{W}{L}(R_1+R_2+2R_{{}_4})(T^2+\phi T+\frac{1}{2}{\phi }^2)\frac{R_6}{R_7}+\frac{KT\ln 8}{q{R}_1}(R_1+R_2+2R_{{}_4})]\end{array}$$

(10)

To obtain an output voltage, which is independent of temperature; thus, $\frac{\partial V_{REF}}{\partial T}=0$.

$$\frac{R_2+2R_4}{R_1}=\frac{(V_{go}-V_{BEO})q}{K{T}_O\ln 8}+(\eta -\delta )\frac{\phi +1}{\ln 8}-1$$

(11)

$$\frac{R_7}{R_6{R}_1}=[(\eta -\delta )(V_{go}-V_{BEO})-\frac{K}{q}(\phi +T_O)]\frac{nu{C}_{ox}\frac{W}{L}}{\ln 8}$$

(12)

As a result, to obtain a reference output voltage with an approximate TC of zero, it is only necessary to set the resistors R₁~R₇ reasonably according to the constraints of Equations (11) and (12).

In the proposed BGR circuit, the differential operational amplifier (OP) is designed to be self-biased and totally symmetrical based on the traditional BGR circuit; this is the case in order to accomplish the low power consumption, which is different from the traditional operational amplifier. This is shown in Figure 4. In order to reduce power consumption, the bias circuit is lowered to the bias voltage for the gate voltage of a tail-current transistor [19,20]. To further reduce the supply voltage, this BGR amplifier employs the transistor structure such that the length of the trench splits in place of the original transistor; this is illustrated in Figure 5. If only the transistor MP0 is used at the input port of OP, the minimum supply voltage ($V_{DD}(min)$) is given by:

$$V_{DD}\left(min\right)=V_{BE2}+\left|Vthp\right|+V_{DS0}+V_{DS10}$$

(13)

where $V_{BE2}$ is the base-emitter voltage of transistor Q2, which is limited by the properties of the device itself and generally takes a value around 0.7 V; $Vthp$ is the threshold voltage of PMOS transistor, which is limited by the device process; $V_{DS0}$ is the drain–source voltage of MP0; and $V_{DS10}$ is the drain–source voltage of MP10.

It is generally difficult to improve both $V_{BE2}$ and $Vthp$; just consider reducing the value of $V_{DS0}$ and $V_{DS10}$. Multiple transistors are stacked so that $V_{DS1}<V_{DS0}$; thus, the supply voltage is reduced.

3. Results

The design of the proposed BGR circuit is based on the Hua Hong 0.11 μm process using the software of Cadence. At a supply voltage of 1.8 V, the total current curve of the BGR circuit is shown in Figure 6; this shows that the total current consumption is 4.17 μA, so that the total power consumption is calculated to be 7.5 μW.

The output voltage variation curves of the first-order BGR circuit and second-order BGR circuit with temperature are shown in Figure 7. The maximum value is 1.1958 V and the minimum value is 1.1936 V when the temperature varies from −40 to 125 °C for the first-order BGR circuit. At the same time, the value is 1.1956 V at a temperature of 27 °C; thus, the TC of the first-order BGR circuit is 10.15 ppm/°C. Then, the maximum value is 1.19562 V and the minimum value is 1.19484 V when the temperature varies from −40 to 125 °C for the second-order BGR circuit. This temperature value is 1.1954 V at 27 °C; thus, the TC of the second-order BGR circuit is 3.95 ppm/°C. Compared with the TC of the first-order BGR circuit, the TC of the second-order BGR circuit is significantly lower.

The design of the circuit should be analyzed at various process corners, various operating voltages, and various ambient temperatures; these are the bases for determining the yield. The simulation of process corners is performed for the proposed BGR circuit; with SS, TT, and FF referring to the lower left direction of the corner, the middle of the center, and the upper right direction of the corner, respectively [21]. Trimming resistor R7 can be used to correct the deviations. The simulation of the graph is shown in Figure 8.

The robustness of the proposed BGR circuit is verified by the Monte Carlo analysis. At a normal temperature of 27 °C, the simulation results of Monte Carlo for 200 samples are shown in Figure 9. The average reference voltage is 1.19937 V and the standard deviation is 40.4338 mV with regards to the proposed BGR circuit. Due to the simulation of the 200 samples, how many heterogeneous sample values are affecting robustness is not shown. It is necessary to use the normal quantile plot, which is a basic graphical approach for checking normality. A sample from the normal distribution $N(u;{\sigma }^2)$ can result in a straight line, which is named by $x\left(i\right)=\sigma z_i+u$ on the normal quantile plot [22]. Any deviation from this line will indicate non-normality. The type of nonlinear pattern may reveal the type of departure from normality. The normal quantile plot results for 200 samples at a normal temperature of 27 °C are shown in Figure 10. The results show that the normal quantile plot successfully extracts a proper straight line. At the same time, most of the sampled result values are distributed around the straight line. Luckily, the sampled values deviate far from the straight line where the number is less than ten. This is an acceptable result, and it indicates that the overall robustness is not bad; however, it still needs improvement.

A test of the PSRR is performed to determine the effect of noise on the supply voltage of the proposed BGR circuit. The PSRR is measured by adding a sinusoidal ripple at a DC bias of 1.8 V without any off-chip filter capacitors. The ripple is swept from 0 Hz to 1 MHz and the measured PSRR is shown in Figure 11. The results of the simulation show that the PSRR is close to −103 dB at the frequency of 100 Hz.

A relatively noiseless characteristic is also required for high precision. The noise simulation of the proposed BGR circuit is shown in Figure 12, where the output noise voltage (Vnoise) is 29 μV/sqrt (Hz) at a frequency of 100 Hz; this indicates a relatively good characteristic of noise. The statistical results are shown in

Table 1. Performance under different process concerns of the proposed BGR circuit.

Performance	TT	FF	SS
Simulated TC (ppm/°C)	3.95	5	6.5
PPSR@100 Hz (dB20)	−103	−100	−102
Vnoise@100 Hz (μV)	29	22.8	0.9

.

In order to measure the dependence of the proposed BGR circuit accuracy on the supply voltage, the operating temperature is controlled in the range of −40 °C to 125 °C. Further, the supply voltage is set to 1.6 V, 1.8 V, 3 V, 4 V, and 5 V, respectively. To test the output voltage variation with temperature, the measurement results are shown in Figure 13. It can be seen from the figure that as the supply voltage increases, the output voltage value at 125 °C is increasing, even exceeding the maximum value of the output voltage in the temperature range of −40 °C to 125 °C. Given that, the TC will result in an increase and fail to meet the requirement of high accuracy. Therefore, if you want to ensure high accuracy, you need to control the supply voltage within a certain range.

Finally, the layout is reassembled by the software of Cadence and the tool of Calibre; thus, it can be verified by the design rule check (DRC) and layout versus schematics (LVS). The overall layout is shown in Figure 14, which occupied a total area of 128 μm × 229 μm.

The performance of the proposed BGR circuit designed in this paper is compared with that of similar BGR circuits in

Table 2. Performance comparison.

Type	G. Zhu et al. [18]	L. Quan et al. [23]	G. Pan et al. [24]	This Work
Power supply (V)	3.5~5	1.8	1.3~3.6	1.8
Process (μm)	0.18	0.18	0.18	0.11
VREF (V)	3.11	0.5	1	1.2
Temperature range (°C)	−40~130	−45~125	−40~125	−40~125
TC (ppm/°C)	4.6	2.61	0.918	3.95
PPSR (dB20)	−92	−107.2	-	−108
Power consumption (μW)	378	400	41.4	7.5

. As can be seen from the table, the parameters of the BGR designed in this paper are compared with the relevant BGR papers published in recent years. Due to the improvement of the traditional circuit and the second-order temperature compensation of the BGR circuit in this paper, compared to those of similar second-order BGR circuits, the temperature coefficient of the proposed BGR circuit is small and the power consumption value of the proposed BGR circuit is low; this achieves both higher accuracy and lower power consumption.

4. Conclusions

In this paper, a low-voltage, low-power, high-precision second-order BGR circuit is proposed. With the help of the software from Cadence, the design of the layout and simulation of the circuit are completed by using the Hua Hong 0.11 μm process. The simulation results show that when the supply voltage is 1.8 V, the TC of the obtained BGR circuit is 3.95 ppm/°C with a temperature range of −40~125 °C; in addition, the power consumption is only 7.5 μW. It can meet the requirements of both low-power and high-precision integrated circuit systems.