Specially-Designed Out-of-Order Processor Architecture for Microcontrollers
Round 1
Reviewer 1 Report (Previous Reviewer 1)
The authors have greatly improved their manuscript and responded to the demanded points.
There are still some small remarks to be added:
1. Row 22. The LUT abbreviation is not described
2. Chapter 4 (row 171) can start on a new page
3. Please provide more accuracy for the future work especially for row 526-528: "Therefore, software tests like SPEC2017 for individual CPUs are not convinced. Due to various situations, complete test will be complicated"
The list of references are now correctly updated and verified.
Author Response
Dear reviewer,
We would like to thank you for your efforts in reviewing our manuscript titled "Specially Designed Out-of-order Processor Architecture for Microcontroller", and providing these helpful comments and suggestions, which will all prove invaluable in the revision and improvement of our paper, as well as in guiding our research in the future.
The following is the revision of the manuscript：
Row22: The expression of “LUT utilization of 18.37%” was modified to “look up table utilization of 18.37% in FPGA implementation”.
Row 171: The layout of paragraphs in the article has been revised.
Row532-538: The future work was extended with more accuracy.
The amendments are tracked in the revised manuscript. All authors have approved the response letter and the revised version of the manuscript.
Thank you again for your valuable comments and suggestions. I look forward to hearing from you soon in due course.
Yours sincerely
Reviewer 2 Report (New Reviewer)
The paper shows interesting results regarding the enhancement of a processor targeting the improvement of its performance during hazards. It is well organized. The paper though needs a considerable effort in editing regarding the language style. The syntax in some cases needs consideration, for example the sentence in line 292 seems unfinished. So, while the results are interesting, these language details are kind of disappointing for the reader.
The equations in page 12 that are very interesting can be analyzed further. Also, Table 1 has to be presented in advance of these equations. Moreover, its first five columns can be reported and not included in the table while the last three that are of major interest can be the major content of the table.
N is used to denote the number of cycles in page 11 and number of instructions in page 12. The authors can use different symbols there.
Author Response
Dear reviewer,
We would like to thank you for your efforts in reviewing our manuscript titled "Specially Designed Out-of-order Processor Architecture for Microcontroller", and providing these helpful comments and suggestions, which will all prove invaluable in the revision and improvement of our paper, as well as in guiding our research in the future.
The following is the revision of the manuscript：
Row 408-429: The equations for theoretical analysis is extended with more details and the format of the equations are modified to be clearer.
Row 405-407: The Table 1 was modified to be more concise and understandable.
Page 12: The reuse of symbol “N” has been modified to disambiguate.
Row 292: The language style of the paper has been modified.
The amendments are tracked in the revised manuscript. All authors have approved the response letter and the revised version of the manuscript.
Thank you again for your valuable comments and suggestions. I look forward to hearing from you soon in due course.
Yours sincerely
This manuscript is a resubmission of an earlier submission. The following is a list of the peer review reports and author responses from that submission.
Round 1
Reviewer 1 Report
The authors provide a particular hardware layout for multi-cycle instruction scheduling that allows microcontrollers to operate more quickly by using VLSI system. The multi-cycle instructions software is tested on XILINX XC7A200T-2FBG484I FPGA platform. Indeed, optimization methods are required and needed in order to use the hardware at the maximum capacity.
Out-of-order execution, or more technically dynamic execution, is a paradigm employed in computer engineering that makes use of instruction cycles that would otherwise be lost in the majority of high-performance central processing units. With out-of-order execution, the processor would execute each instruction in the correct sequence before moving on to the next pipeline.
In the following section the author is kindly asked to do the required modifications:
Please do an English professional proofreading.
Write the paper in impersonal mode not in first person plural.
Row 11 . The first phrase has unclear statement “microcontroller is often implanted to schedule”
Row 96 Higher frequency? Ambiguous, please give more details…
Row 25 “Generally, the microcontroller meets the processing requirements.” Please give more details, more specifically in the processing requirements as it is known that depending on application the processing requirements are different.
Row 114 “It can be seen”-this form it is not recommended to be used in writing a scientific paper. Please rephrase…
Row 117 "it can be seen that the ability”
Row 370 Same issue. Please do a general check for the paperwork
Row 269 “If” lowercase
Row 286 please use impersonal mode
When the references are mentioned then should point clearly why is mentioned. Some of the references are hard to find. Also, the reference list needs to be synchronized with the paper list accordingly:
Row 53 reference nr [7] The reference list is wrong! I cannot find information’s in the reference nr 7 about NVDLA. Please carefully verify all the reference list accordingly.
Row 69 reference nr [9] I cannot find the details about RISC-V instructions
Row nr 69 Reference nr [10] is about “A Scalable Multi-TeraOPS Core for AI Training and Inference” I cannot find relevant informations about RISC V
Row nr 72 Reference nr 11 is about “A Configurable Cloud-Scale DNN Processor for Real-Time AI”
Row nr 72 Reference nr 12 is about “ iCFP: Tolerating all-level cache misses in in-order processors”
Row nr 72 Reference nr 13 is about FPGA. What are “other advanced architectures…
Row 110 reference 16 is about “Discerning the Dominant Out-of-Order Performance Advantage: Is it Speculation or Dynamism. In the paper the author is A. Hilton
Row 111 Reference [17] is about “A survey of techniques for designing and managing CPU register file but in the paper the author is referring to “Flea- Flicker” two-pass Pipelining
All the reference list requires to be verified!
Future work is vague. Please give more specific details!
Author Response
Dear reviewer,
We would like to thank you for your efforts in reviewing our manuscript titled "Specially-Designed Out-of-order Processor Architecture for Microcontroller", and providing these helpful comments and suggestions, which will all prove invaluable in the revision and improvement of our paper, as well as in guiding our research in the future.
We have studied your comments point by point, revised the manuscript accordingly.
Proofread and revised the language of the whole article.
Row 34, 127, 159, 207, 291: The abuse of first person plural have been modified.
Row 279: The solecisms have been corrected.
Row 120 & 123: Phrases which are inappropriate in a scientific paper like “it can be seen” have been deleted or replaced.
Supplementing more details and reorganized the description for some ambiguities.
Row 11: explanation was given to eliminate some confusing concepts in results.
Row 27: Details in the processing requirements are given.
Row 245: Future work is more specific now. “Further research is needed to explore a dependable benchmark considering the impact of the AI algorithm, compiler optimization, and the compute pattern of the different sub-modules.”
A Conclusions section was added to summarize and illustrate the work of the paper in order to present the findings more clearly.
Row 407-424
All the references and the list have been verified.
The references are dislocated and not synchronized with the list because of wrong data formats in the former vision. Now you can find corresponding information in references and paper list.
The amendments are tracked in the revised manuscript. All authors have approved the response letter and the revised version of the manuscript.
Thank you again for your valuable comments and suggestions. I look forward to hearing from you soon in due course.
Yours sincerely
Reviewer 2 Report
The article discusses the design of a processor architecture for very large-scale integration circuits (VLSI) systems. The introduction of the problem is informative and situates the problem well. The reading is enjoyable, however, the presentation of results is brief, it is not easy to understand the relevance of many of the data provided and there is no in-depth discussion of the value of the findings. There is neither a discussion section nor a conclusion section. This part should be extensively improved. In its present form the paper is an interesting introduction to a problem but both the analysis and the results do not live up to the good level of informative explanation that exists at the beginning.
The presentation of the concept of "depth" is confusing and not well clarified, being that Figures 7 and 8 which are crucial for the results use this concept, it would be necessary to explain more about it. Figure 7 uses different colors in the bars than in the legend.
Author Response
Dear reviewer,
We would like to thank you for your efforts in reviewing our manuscript titled "Specially-Designed Out-of-order Processor Architecture for Microcontroller", and providing these helpful comments and suggestions, which will all prove invaluable in the revision and improvement of our paper, as well as in guiding our research in the future.
We have studied your comments point by point, revised the manuscript accordingly.
Row 407: We have supplemented the Results with a Conclusions section summarizing and illustrating the work of the paper in order to present the findings more clearly.
Row 351 & 376: In-depth explanation was given to eliminate some confusing concepts in results.
Row 386: Figure 7 has been redrawn to correct the mistake and reduce ambiguity for easier understanding.
Additionally, We have also corrected the language throughout the article and reorganized the description for some other ambiguities.
The amendments are tracked in the revised manuscript. All authors have approved the response letter and the revised version of the manuscript.
Thank you again for your valuable comments and suggestions. I look forward to hearing from you soon in due course.
Yours sincerely
