Novel Motor-Kinetic-Energy-Based Power Pulsation Buffer Concept for Single-Phase-Input Electrolytic-Capacitor-Less Motor-Integrated Inverter System

Abstract

The motor integration of singe-phase-supplied Variable-Speed Drives (VSDs) is prevented by the significant volume, short lifetime, and operating temperature limit of the electrolytic capacitors required to buffer the pulsating power grid. The DC-link energy storage requirement is eliminated by using the kinetic energy of the motor as a buffer. The proposed concept is called the Motor-Integrated Power Pulsation Buffer (MPPB), and a control technique and structure are detailed that meet the requirements for nominal and faulted operation with a simple reconfiguration of existing controller blocks. A 7.5 KW, motor-integrated hardware demonstrator validated the proposed MPPB concept and loss models for a scroll compressor drive used in auxiliary railway applications. The MPPB drive with a front-end CISPR 11/Class A EMI filter, PFC rectifier stage, and output-side inverter stage achieved a power density of 0.91 KW L⁻¹ (15 W in⁻³). The grid-to-motor-shaft efficiency exceeded 90% for all loads over 5 kW or 66% of nominal load, with a worst-case loss penalty over a conventional system of only 17%.

1. Introduction

Mobility, transportation, and industrial systems are increasingly electric, from the drivetrain to the auxiliaries, driven by improvements in battery performance and lifetime, government and private mandates to reduce greenhouse gas emissions, and an improved user experience. This electrification includes the traction systems in electric vehicles, but the auxiliary systems must also be electrified with power-dense, efficient, and reliable power conversion stages under unique operating conditions and constraints. In particular, electromechanical systems—including pumps, compressors, and blowers—are required on nearly every vehicle and require VSDs for efficient operation.

An on-board compressor system for the air brakes of railway vehicles was considered here, as shown in Figure 1a. This oil-free scroll compressor [1]—selected for high pressure, low noise, and long maintenance intervals (see [2] for a comparison of compressors)—was used to charge the pressure tank that supplies the air brakes, pantograph, and other critical loads driven by air pressure, necessitating ultra-high reliability. As such, the compressor system is supplied from a tertiary traction transformer winding during normal operation (“grid operation”), as is typical for auxiliary railway applications [3], and from an on-board battery during startup or extended grid interruptions, with a reduced output power. The key specifications for this particular application are given in Table 1. While, in this work, the focus was on the single-phase to three-phase VSD power conversion system for this particular application, the requirements for single-phase to three-phase variable-speed conversion are quite general (e.g., a 10 $\mathrm{k}$$\mathrm{W}$, 230 Vrms, single-phase VSD in [4], or a single-phase to three-phase VSD with Power Factor Correction (PFC) operation in [5]).

With a VSD system required to increase compressor performance [6], the application needs a power electronics system to convert the single-phase AC—or DC, under battery operation—input voltage into a symmetrical three-phase voltage system, where the magnitude and frequency can be adjusted to control the motor speed (and, accordingly, output power). A three-phase Permanent Magnet Synchronous Motor (PMSM) was selected for high torque, low weight, high efficiency, and compactness [7]. The VSD was designed for 9 $\mathrm{k}$$\mathrm{W}$ of output power (see Figure 1b), to meet the required $7.5$ $\mathrm{k}$$\mathrm{W}$ of mechanical output power (Table 1) while accounting for system losses and acceleration, must comply with CISPR 11/Class A [8], and must operate under unity power factor operation to minimize harmonic distortion and reactive grid power [9].

Table 1. Key system specifications.

Air Flow Rate at Pressure	850 L min−1, 0.83 MPa
Nominal Speed ($n_{\mathrm{N}}$)	3700 rpm
Nominal Mech. Power, Grid ($P_{0,\mathrm{N}}$)	$7.5$ kW
Nominal Mech. Power, Batt. ($P_{0\mathrm{DC},\mathrm{N}}$)	$1.0$ kW
Nominal Grid Voltage ($V_{\mathrm{G},\mathrm{N}}$)	400 Vrms
Grid Voltage Range ($V_{\mathrm{G}}$)	280 Vrms to 530 Vrms
Grid Frequency ($f_{\mathrm{G}}$)	50 Hz
Battery Voltage Range ($V_{\mathrm{B}}$)	70 Vdc to 120 Vdc
EMI Standard (Input)	CISPR 11/Class A [8]

Table 1. Key system specifications.

Air Flow Rate at Pressure	850 L min−1, 0.83 MPa
Nominal Speed ($n_{\mathrm{N}}$)	3700 rpm
Nominal Mech. Power, Grid ($P_{0,\mathrm{N}}$)	$7.5$ kW
Nominal Mech. Power, Batt. ($P_{0\mathrm{DC},\mathrm{N}}$)	$1.0$ kW
Nominal Grid Voltage ($V_{\mathrm{G},\mathrm{N}}$)	400 Vrms
Grid Voltage Range ($V_{\mathrm{G}}$)	280 Vrms to 530 Vrms
Grid Frequency ($f_{\mathrm{G}}$)	50 Hz
Battery Voltage Range ($V_{\mathrm{B}}$)	70 Vdc to 120 Vdc
EMI Standard (Input)	CISPR 11/Class A [8]

Conventionally, these power conversion systems are realized with a two-stage system [10] comprising a front-end PFC rectifier, an electrolytic DC-link capacitor to buffer the power pulsation from the single-phase grid supply, and a VSD inverter to drive the motor and compressor [11]. For auxiliary motor drive applications, though, efficiency is not the primary concern—due to the low duty-cycle of operation—and the power density should be maximized for the space- and weight-constrained mobility application. The highest-power-density solution, in the end, is a motor-integrated drive system [12], which eliminates expensive shielded cables [13] and cable reflections [14], which allows for higher slew rates of the inverter stage power semiconductor switching voltage transitions and/or lower switching losses, exhibits better Electromagnetic Interference (EMI) behavior [12] from integration in a single housing, and allows for combined cooling of the electronics and motor [15]. Motor-integrated VSDs, in sum, result in lower installation and operating costs, but require the integration of all drive components—even the EMI input filter [16]. The requirement for electrolytic capacitors as the single-phase power buffer, though, prevents motor integration, with the elevated operating temperatures [17] of the integrated converter (85 ${}^{\circ }\mathrm{C}$ to 105 ${}^{\circ }\mathrm{C}$) [18] degrading lifetime [19] and/or requiring substantial overdimensioning of these large capacitors.

For the highly desired motor integration of the converter system for these single-phase to three-phase drive applications, then, alternatives to the traditional two-stage approach with an electrolytic capacitor are required. Solutions that synergistically employ the components are considered first. Ultra-low-cost implementations use the grid voltage effectively as one of the motor line-to-line voltages and employ four power MOSFETs and a TRIAC [20], but do not allow a wider range of speed control. To utilize the motor star point as one of the connecting points to the single-phase grid, the motor leakage inductance may be utilized as a boost inductor [21], but this results in unacceptably high voltage stresses (twice the grid peak voltage) for this application, which already features a high-grid-input voltage. The same issue occurs in a low-cost implementation that employs a front-end PFC rectifier with only one bridge-leg and a split DC-link [22]. Coupled power electronics (rectifier to inverter) approaches, such as Z-source-based concepts [23] or matrix converters [24], typically feature an (integrated) active buffer for power decoupling [25], a basic requirement since the matrix converter does not include energy storage [26], which drives the complexity and high component stresses. Current-source structures [27], in the end, only replace the boost inductor with a DC-link inductor (since voltage-source inverters do not require an output filter here) while requiring bidirectional switches, and therefore do not improve the potential for integration. The synergistic approaches, then, do not hold the promise of eliminating the large energy storage components required to buffer the single-phase power pulsation—and if they do start to alleviate the requirement, the penalties appear unacceptably high.

Accordingly, this work proposes to use the motor (and load) inertia as a power buffer, eliminating the need for power buffering in the DC-link capacitors, an approach called the MPPB and introduced in [28]. A conventional two-stage structure was utilized, with a single-phase front-end PFC rectifier and a three-phase VSD inverter, with the power flow for a conventional system and the MPPB system shown in Figure 2a. Although particular rectifier and inverter topologies were selected and demonstrated here, the findings are applicable to any specific implementation of the rectifier and inverter.

The MPPB concept was previously proposed with the PFC rectifier omitted and the inverter stage directly supplied from a single-phase-grid diode bridge rectifier [29]. This concept results in a rectifier sine wave voltage at the DC-link, so the input current is only sinusoidal if the motor voltage stays below the rectified input voltage [30]. This concept, then, is limited to motors with a low back Electromotive Force (EMF) and/or applications where a large speed variation is acceptable—but in both cases, a unity power factor cannot be achieved. In [31], a solution to this problem was proposed, where a reactive current component was injected into the motor to keep the back EMF of the motor below the input voltage. Here, the PFC rectifier can indeed be omitted, but the small motor inductance leads to large motor currents and excessive losses. With this constraint and the large fluctuating DC-link voltage, which increase the system complexity, applications for this approach are restricted to drive systems with special low-voltage motors that do not operate at common voltages.

In this work, a single-phase-supplied electrolytic-less VSD system with dedicated rectifier and inverter stages that realizes a high lifetime and reduced volume for motor integration is designed, modeled, and implemented. In Section 2, the rectifier and inverter topologies are selected, introduced, and evaluated with the concept and control of the novel proposed MPPB approach to eliminate electrolytic capacitors. In this section, the operational limits for the proposed approach are evaluated for different load cases. The novel control concept for MPPB operation is derived and explained in detail, with verification based on circuit simulation, and finally, the phase currents are investigated in detail to compare the performance of the novel MPPB approach to a conventional system. Section 3 details the implementation of the motor-integrated drive system with volume and loss distributions, including showcasing the motor integration that is uniquely enabled by the novel, proposed MPPB approach. Section 4 verifies the system operation in the time domain for the steady-state and transients, loss models across the full torque range, and EMI requirements and compares the system losses between the MPPB and conventional systems. In Section 5, the extended functionality required for the considered application is demonstrated, including ride-through and battery-supplied operation. The novel control structure can also be employed for DC-supply operation with a single structure that simplifies the implementation and maintenance effort of the system. Section 6 concludes and summarizes the MPPB approach and results of the work, with Appendices that specifically investigate low-speed operation in the context of the proposed approach (Appendix A), controller design and future enhancements (Appendix B) to reduce the DC-link voltage ripple (including novel feedforward terms), and the detailed phase currents under MPPB operation (Appendix C).

2. Topology Selection and Proposed MPPB Concept and Control

2.1. Topology

Although the proposed MPPB concept is applicable to a broad range of inverter and rectifier topologies, a particular configuration for the demonstration was selected in this paper to explain and, later, showcase the MPPB concept. Conventional systems in these applications utilize a two-stage design with a single-phase PFC rectifier, a large low- and high-frequency-decoupling DC-link capacitor, and a three-phase VSD inverter. A similar two-stage topology was desired here for a straightforward comparison and implementation of the MPPB concept relative to the state-of-the-art.

A single-phase PFC rectifier can be implemented with multiple topologies, components, and control schemes, and these options were reviewed extensively in [32]. A unidirectional boost PFC rectifier with a diode bridge, boost inductor, and transistor and diode pair is widely used for simplicity and low-cost [33]; here, instead, a totem-pole PFC with an unfolder bridge-leg (see Figure 2a) was selected to improve the performance by avoiding the diode conduction losses [34]. While Zero-Voltage Switching (ZVS) triangular-current-mode schemes could further reduce the semiconductor switching losses [35], a simple Pulse-Width-Modulation (PWM) scheme with a constant switching frequency is preferred for the simplicity of interleaving and operation across a wide AC input voltage range (see Figure 1b). Finally, with a DC-link voltage above 750 $\mathrm{V}$ (the peak voltage of the maximum grid voltage), 1200 $\mathrm{V}$ power semiconductors must be used, and Silicon Carbide (SiC) Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) were chosen over Insulated Gate Bipolar Transistors (IGBTs) for the lower loss characteristics.

Similarly, a straightforward two-level, three-phase inverter utilizing SiC MOSFETs and directly connected to the motor [36] was selected for the power topology. With SiC MOSFETs and no output filter, a voltage slew rate limitation was required to prevent motor insulating aging [37], with the options and tradeoffs for this slew rate value and implementation highlighted in [38].

The resulting structure with the indicated power flow is shown in Figure 2a, with the grid and rectifier input waveforms under conventional operation shown in Figure 2b,c (see [34] for a more detailed explanation). This structure also supports the necessary DC-input operation, with the battery terminals directly connected to x and y. In this mode, the PFC rectifier operates as a conventional DC/DC boost converter.

2.2. MPPB Concept

At the single-phase grid input, the unity power factor operation dictates that the drive system behaves as an ohmic load with a sinusoidal input current $i_{\mathrm{G}}\left(t\right)={\widehat{I}}_{\mathrm{G}}cos\left(2\pi f_{\mathrm{G}}t\right)$ in phase with the grid voltage $v_{\mathrm{G}}\left(t\right)={\widehat{V}}_{\mathrm{G}}cos\left(2\pi f_{\mathrm{G}}t\right)$, as shown in Figure 2b. The instantaneous input power, however, varies as:

$$p_{\mathrm{G}}\left(t\right)=v_{\mathrm{G}}\left(t\right)i_{\mathrm{G}}\left(t\right)=P_0+{\tilde{p}}_{\mathrm{G}}\left(t\right),$$

(1)

with $P_0={\widehat{V}}_{\mathrm{G}}{\widehat{I}}_{\mathrm{G}}/2$ (see Figure 2c). A lossless system implies that $p_{\mathrm{G}}\left(t\right)=p_{\mathrm{PFC}}\left(t\right)$ and $p_{\mathrm{M}}\left(t\right)=p_{\mathrm{INV}}\left(t\right)$, and an instantaneous power balance results in:

$$p_{\mathrm{G}}\left(t\right)=p_{\mathrm{C}}\left(t\right)+p_{\mathrm{M}}\left(t\right).$$

(2)

Thus, the twice-grid-frequency pulsation ${\tilde{p}}_{\mathrm{G}}\left(t\right)=P_{0}cos\left(2\pi f_{\mathrm{P}}t\right)$ with $f_{\mathrm{P}}=2f_{\mathrm{G}}$ is then forwarded to the DC-link capacitor $C_{\mathrm{DC}}$, under conventional operation, or, under the proposed MPPB approach, through the DC-link and the inverter to the motor.

2.2.1. Conventional Operation with an Electrolytic Capacitor

First, system operation with a conventional approach, utilizing a large electrolytic capacitor at the DC-link, is outlined. The waveforms are shown in Figure 2(d.i),(e.i) for each stage.

Under constant speed $\omega \left(t\right)=\overline{\omega }$ and constant torque $t_{\mathrm{M}}\left(t\right)=T_{\mathrm{L}}$ operation, the motor power is constant ($p_{\mathrm{M}}\left(t\right)=\omega \left(t\right)t_{\mathrm{M}}\left(t\right)=p_{\mathrm{INV}}\left(t\right)\equiv P_0$), as shown in Figure 2(e.i). With this constant power $P_0$ and the twice-line-frequency power pulsation, from the grid input, a large intermediate DC-link capacitor $C_{\mathrm{DC}}$ was used to cover the active power mismatch between the two stages, where the instantaneous capacitor power is:

$$p_{\mathrm{C}}\left(t\right)\equiv p_{\mathrm{G}}\left(t\right)-p_{\mathrm{M}}\left(t\right)={\tilde{p}}_{\mathrm{G}}\left(t\right)=P_{0}cos\left(2\pi f_{\mathrm{P}}t\right)$$

(3)

and the average capacitor power is zero, $P_{\mathrm{C}}={\overline{p}}_{\mathrm{C}}\left(t\right)=0\mathrm{W}$, as it must be for the periodic steady-state (see Figure 2(d.i)).

With a nearly constant DC-link voltage $v_{\mathrm{DC}}\left(t\right)\approx {\overline{v}}_{\mathrm{DC}}$ and under the power balance of the capacitor $p_{\mathrm{C}}\left(t\right)=v_{\mathrm{DC}}\left(t\right)i_{\mathrm{C}}\left(t\right)$, the capacitor current must have an approximately sinusoidal waveform $i_{\mathrm{C}}\approx {\tilde{p}}_{\mathrm{G}}\left(t\right)/{\overline{v}}_{\mathrm{DC}}$ with amplitude ${\widehat{I}}_{\mathrm{C}}\approx P_0/{\overline{v}}_{\mathrm{DC}}$. This capacitor current causes a voltage ripple with amplitude $\Delta v_{\mathrm{DC}}$, which is typically limited to a certain percentage of the DC-link voltage $v_{\mathrm{DC}}$ to provide a nearly constant voltage (as previously assumed) to the inverter. The required capacitance value $C_{\mathrm{DC}}$ is:

$$C_{\mathrm{DC}}=\frac{P_0}{2\pi f_{\mathrm{P}}}\frac{1}{{\overline{v}}_{\mathrm{DC}}\Delta v_{\mathrm{DC}}},$$

(4)

and for this application, a value in the $\mathrm{m}$$\mathrm{F}$ range is required. This large capacitance value is, therefore, typically realized with electrolytic capacitors. The capacitor current, in addition to causing the voltage ripple, also results in a low-frequency Root Mean Square (RMS) current stress of the capacitor of $I_{\mathrm{C},\mathrm{LFrms}}={\widehat{I}}_{\mathrm{C}}/\sqrt{2}=P_0/{\overline{v}}_{\mathrm{DC}}1/\sqrt{2}$.

For the nominal operating point of $f_{\mathrm{G}}=50\mathrm{Hz}$, ${\overline{v}}_{\mathrm{DC}}=650\mathrm{V}$ (see

Table 2. Nominal operating point.

Nominal Speed ($n_{\mathrm{N}}$)	3700 rpm
Nominal Mech. Power, Grid ($P_{0,\mathrm{N}}$)	$7.5$ kW
Nominal Grid Voltage ($V_{\mathrm{G},\mathrm{N}}$)	400 Vrms
Grid Frequency ($f_{\mathrm{G}}$)	50 Hz
DC-Link Voltage ($V_{\mathrm{DC}}$)	650 Vdc

), $P_0=8\mathrm{kW}$, and a selected $\Delta v_{\mathrm{DC}}=20\mathrm{V}$ (see Figure 2(d.i)), the required capacitance is $C_{\mathrm{DC}}=0.98\mathrm{mF}$ with a current stress of $I_{\mathrm{C},\mathrm{LFrms}}=8.7\mathrm{A}$. This DC-link capacitance can be realized with four 1 mF capacitors B43742A6108M000 [39] (rated for 500 V and $4.9$ A at 105 ${}^{\circ }\mathrm{C}$), which are connected in a 2 × 2 array. This DC-link capacitor alone corresponds to a box volume of 1 L (61 in³) and 6 W of losses before including the PFC and VSD high-frequency currents. This large—and required—electrolytic DC-link capacitor is a major limitation for power density, motor integration, and converter lifetime [40].

To overcome these limitations, alternate capacitor-based Power Pulsation Buffer (PPB) buffer concepts have been proposed in the literature [41]. These circuits all contain an active switching stage and a buffer capacitor stage [42] (often separate, in series [43], or in parallel [44], from the existing DC-link capacitor) with a capacitor cycled with a large voltage ripple $\Delta v_{\mathrm{C}}$. With a larger voltage ripple, the required capacitance value is much smaller (according to Equation (4)) and enables foil- or ceramic-based capacitor implementations, but the additional active switching stages incur significant realization effort, complexity, and cost for the overall drive system.

2.2.2. Motor Power Pulsation Buffer Concept

Rather than adding complexity to the drive system’s electronics, the pulsating power component ${\tilde{p}}_{\mathrm{G}}$ can be removed from the converter system by enforcing $p_{\mathrm{C}}\left(t\right)\equiv 0\mathrm{W}$, rather than only enforcing the periodic steady-state condition ${\overline{p}}_{\mathrm{C}}\left(t\right)\equiv 0\mathrm{W}$. This condition is shown in Figure 2(d.ii). With this constraint and the power balance of Equation (2), the only possible result is to forward to complete the input power through the DC-link and the inverter to the motor [28]. The motor, then, is no longer operated with a constant output power, but with the pulsating grid power itself as $p_{\mathrm{M}}\left(t\right)=\omega \left(t\right)t_{\mathrm{M}}\left(t\right)\equiv p_{\mathrm{G}}=P_0\left[1+cos\left(2\pi f_{\mathrm{P}}t\right)\right]$.

Due to the motor inertia $J_{\mathrm{M}}$ (and any additional load inertia), the speed $\omega$ changes slowly ($\omega \left(t\right)\approx \overline{\omega }$), resulting in a pulsating torque $t_{\mathrm{M}}\left(t\right)\approx p_{\mathrm{G}}\left(t\right)/\overline{\omega }$ at twice the grid frequency (Figure 2(e.ii)). When the instantaneous input power is larger than the average power, positive torque is applied to the inertia, and the rotating mass is accelerated (speed increases), with the excessive power stored as an increase in kinetic energy $e_{\mathrm{KIN}}=J_{\mathrm{M}}{\omega }^2/2$. In the other part of the mains period, when the input power drops below the average power, negative torque is applied and the rotating mass is decelerated. This causes a pulsating rotational speed $\omega \left(t\right)$ with an average $\overline{\omega }$, analogous to the DC-link voltage in the conventional system, where the amplitude of the speed ripple $\Delta \omega$ is (and recalling $P_0=\overline{\omega }{T}_{\mathrm{L}}$, where $T_{\mathrm{L}}$ is the load torque):

$$\Delta \omega \approx \frac{1}{2\pi f_{\mathrm{P}}}\frac{P_0}{\overline{\omega }{J}_{\mathrm{M}}}=\frac{1}{2\pi f_{\mathrm{P}}}\frac{T_{\mathrm{L}}}{J_{\mathrm{M}}}.$$

(5)

This concept buffers the pulsating power in the inertia of the motor, an approach called the Motor-Integrated Power Pulsation Buffer. The basic operation is similar to the working principle of conventional single-phase motors [45], although with the VSD capabilities required here and for most modern motors.

Another way to conceive of the approach, then, is that the motor acts as both a drive and a flywheel, which are used independently for peak power reduction in traction systems [46], peak power supply within railway grids [47], smoothing of the output power of renewable power sources such as wind power [48], or within dynamic voltage restorers [49]. Because low-speed motors have a large moment of inertia $J_{\mathrm{M}}$ and high-speed motors have high rotational speeds $\omega$, the stored kinetic energy of the mechanical system is typically orders of magnitude larger than the required energy to buffer the electric power pulsation at the input, leading to a very small variation in the rotational speed $\omega$ around its average value $\overline{\omega }$ (for $J_{\mathrm{M}}$ according to Table 3, $\Delta \omega =7.3\mathrm{rad}/\mathrm{s}=70\mathrm{rpm}$ or 1.9%). Analogous to the capacitor current, though—although here with a DC offset of the average torque—the MPPB concept results in a large twice-line-frequency variation in the mechanical torque between zero and twice the average torque value. The MPPB concept offers a fundamental simplicity with the potential to significantly reduce or, theoretically, even eliminate the DC-link capacitor as the energy storage.

In Equation (5), a linear relationship between the speed ripple amplitude $\Delta \omega$ and the load torque $T_{\mathrm{L}}$ is observed, and the validity of the MPPB concept across the complete range of motor speeds must be investigated. Under variable speed operation, the load torque may also depend on the current speed based on the load torque speed characteristic. This relationship is defined around the nominal load torque $T_{\mathrm{L},\mathrm{N}}$ at a nominal average speed ${\omega }_{\mathrm{N}}$, with an exponential dependence between torque and speed as $T_{\mathrm{L}}=T_{\mathrm{L},\mathrm{N}}{\left(\overline{\omega }/{\omega }_{\mathrm{N}}\right)}^k$. The speed ripple under the MPPB operation can then be defined as:

$$\Delta \omega \approx \frac{1}{2\pi f_{\mathrm{P}}}\frac{T_{\mathrm{L}},\mathrm{N}}{J_{\mathrm{M}}{\omega }_{\mathrm{N}}^k}{\overline{\omega }}^k.$$

(6)

For $k>1$, which includes fans, blowers, or centrifugal pumps ($k=2$), the load torque and speed ripple grow faster than the average speed ($\Delta \omega \propto {\overline{\omega }}^2$), so the worst-case ripple in both absolute and relative terms occurs at the nominal speed and nominal torque operating point. For $k=1$, the ripple amplitude scales linearly with speed ($\Delta \omega \propto \overline{\omega }$), resulting in a constant relative ripple. It is important to point out that in both cases, i.e., for $k\ge 1$, the speed ripple will be much less than the average speed ($\Delta \omega <<\overline{\omega }$) at all operating points—including speeds close to zero—if the condition is met at the nominal operating point, and the time-varying speed is defined as $\omega \left(t\right)\approx \overline{\omega }$.

For applications where $0\le k<1$, however, the absolute speed ripple grows slower than the average speed ($\Delta \omega \propto {\overline{\omega }}^k$). This may occur for a constant torque load $T_{\mathrm{L}}$ (the $k=0$ condition), for which an application could be a compressor with constant back pressure [50]—the use case considered in this paper. In this case, the absolute speed ripple amplitude is in a first approximation (see Equation (6)) independent of the speed and constant. This condition results in a lower limit on the average speed, since an instantaneous negative speed needs to be prevented for the MPPB operation (to avoid a transfer of energy from the motor to the DC-link). To a first approximation, this implies a lower absolute speed limit of $\overline{\omega }-\Delta \omega =0\mathrm{rad}/\mathrm{s}$ and a lower speed limit for continuous operation of ${\overline{\omega }}_{\min }\approx \Delta \omega$ (this limit does not apply to transient operation). In the vicinity of ${\overline{\omega }}_{\min }$, however, the approximation $\omega \left(t\right)\approx \overline{\omega }$ is no longer valid. Therefore, this lower speed limit is investigated in detail in Appendix A.

2.3. Control

Relative to the conventional control technique for a two-stage system, the MPPB control can be realized with identical high-frequency current control and a modification of only the coupling in the top-level structure between the PFC rectifier and the inverter. Therefore, the control structure of a conventional system is detailed first before moving to the needed modifications for the MPPB technique.

2.3.1. Conventional Control Overview

In conventional single-phase-supplied VSD systems, the PFC rectifier and the inverter stage are decoupled from one another by the large intermediate DC-link capacitor. The control structures are also mostly decoupled, as shown in Figure 3a.

The PFC rectifier control provides a constant DC-link voltage while drawing a sinusoidal current from the grid. Firstly, the power-pulsation-associated voltage ripple in the measured signal is eliminated, either by a Moving-Average Filter (MAF) [51] (shown here) or a conventional low-pass filter. The output of this filter, the obtained average value ${\overline{v}}_{\mathrm{DC}}$, is then compared to the reference $V_{\mathrm{DC}}^{\ast }$, and the DC-link voltage control derives the average capacitor power $P_{\mathrm{C}}^{\ast }$, which can be taken as the average grid power $P_{\mathrm{G}}^{\ast }$, and is then used to generate the input current reference $i_{\mathrm{G}}^{\ast }$ for the grid current controller [52]. This results in the duty-cycle for the boost stage $d_{\mathrm{B}}$ and the corresponding switching state of the unfolder leg $S_{\mathrm{UN}}$.

The task of the inverter control is to track the speed reference ${\omega }^{\ast }$, a target that is typically accomplished with a control structure in the dq-coordinate system [53]. The speed control results in the reference motor torque $T_{\mathrm{M}}^{\ast }$, or as shown here, in the reference motor power $P_{\mathrm{M}}^{\ast }={\omega }^{\ast }{T}_{\mathrm{M}}^{\ast }$. Considering a rotor field-oriented control in a rotating dq-reference frame [54], this request can be translated to the torque-generating current $I_{\mathrm{Mq}}^{\ast }$ by the torque constant $k_{\mathrm{T}}$ or, based on the power balance $P_{\mathrm{M}}^{\ast }=3V_{\mathrm{P}}{I}_{\mathrm{Mq}}^{\ast }/2$, where $V_{\mathrm{P}}$ is the induced voltage (assumed proportional to the reference speed and aligned with the q-axis), and the dq-quantities correspond to the phase amplitudes. The motor current control, in the end, determines the duty-cycles $d_{\mathrm{a}}$, $d_{\mathrm{b}}$ and $d_{\mathrm{c}}$ of the inverter switching stages.

In the conventional approach, the DC-link capacitor compensates the difference of the instantaneous grid power $p_{\mathrm{G}}\left(t\right)$ and motor power $P_{\mathrm{M}}$, so only the average power of the grid $P_{\mathrm{G}}$ and the inverter $P_{\mathrm{M}}$ have to be equal. To achieve this, the conventional control structure typically employs a feedforward of the average motor power $P_{\mathrm{M}}^{\ast }$, where the inverter stage directly informs the rectifier stage about the needed output power (Figure 3a) and thus improves the control performance of the PFC rectifier. For PFC operation, $P_{\mathrm{G}}^{\ast }$ is not allowed to vary within a grid period $T_{\mathrm{G}}$, which requires a slow DC-link voltage control and a bandwidth-limited feedforward (or this could be achieved with an additional low-pass filter, which is not shown here).

2.3.2. MPPB Control Overview

For the proposed MPPB control structure, the average grid power $P_{\mathrm{G}}$ must still match the average motor power $P_{\mathrm{M}}$, as $P_{\mathrm{G}}=P_{\mathrm{M}}=P_0$. Here, though, the power pulsation is buffered by the motor inertia, causing a (small) speed ripple that should be eliminated in the signal measurement, as the DC-link voltage ripple was in the conventional control scheme.

The speed controller, then—which drives the required average motor power $P_{\mathrm{M}}^{\ast }$ from the difference between the reference speed ${\omega }^{\ast }$ and average speed $\overline{\omega }$—defines the grid power $P_{\mathrm{M}}^{\ast }=P_{\mathrm{G}}^{\ast }$ and, therefore, the grid current $i_{\mathrm{G}}^{\ast }$ (see Figure 3b). Again, $P_{\mathrm{G}}^{\ast }$ must be bandwidth limited (here, slow speed control) to prevent a distortion of the grid current.

The instantaneous input power $p_{\mathrm{G}}^{\ast }=v_{\mathrm{G}}{i}_{\mathrm{G}}^{\ast }$ is derived and feed-forwarded to the motor control, resulting in the time-varying q-current $i_{\mathrm{Mq}}^{\ast }$, which causes the torque pulsation. Here, though, a stable DC-link voltage $v_{\mathrm{DC}}$ must be ensured, and the DC-link voltage control block achieves this by deriving the instantaneous reference power $p_{\mathrm{C}}^{\ast }$ from the reference value $V_{\mathrm{DC}}^{\ast }$ and the unfiltered measurement $v_{\mathrm{DC}}$.

According to the power balance Equation (2), this quantity is then subtracted for the instantaneous motor power request:

$$p_{\mathrm{M}}^{\ast }\left(t\right)=p_{\mathrm{G}}^{\ast }\left(t\right)-p_{\mathrm{C}}^{\ast }\left(t\right).$$

(7)

The elegance of the MPPB approach, then, is the utilization of identical control blocks that are simply connected in a different configuration. The MPPB control, then, can be implemented with only software modifications and could even be retrofitted into existing deployments.

2.3.3. MPPB Control Details

In the proposed approach, the primary challenge is that the speed control defines the average grid power, but the inverter must ensure that the instantaneous input power is forwarded to the motor; otherwise, with a small DC-link capacitance, the difference could charge the DC-link capacitor rapidly and lead to catastrophic failures. To address this critical challenge and highlight the other details of the MPPB control technique, the simplified control structure of Figure 3b is extended and shown together with the power topology in Figure 4.

To achieve a high quality for both the power and current alongside a high dynamic control at the output, the control structures were realized in a cascaded fashion. The outer loops for speed and DC-link voltage control provide the current setpoints for the grid and motor current control inner loops, with the motor current control implemented in the dq-coordinate system [53] using the mechanical rotor angle $\epsilon$ [54] provided by the encoder of the PMSM.

This encoder angle is also used to derive the instantaneous speed $\omega$, shown at the bottom of Figure 4, which is then filtered by a MAF [51] with $T_{\mathrm{MAF}}=T_{\mathrm{P}}=T_{\mathrm{G}}/2$ to eliminate the speed ripple in the measured signal. Inside the speed control block, $\overline{\omega }$ is compared to the reference ${\omega }^{\ast }$, and the speed controller $\mathrm{R}\omega$ derives the reference average motor torque $T_{\mathrm{M}}^{\ast }$, which results in the reference average motor power $P_{\mathrm{M}}^{\ast }=T_{\mathrm{M}}^{\ast }{\omega }^{\ast }$ and the average grid power as $P_{\mathrm{G}}^{\ast }=P_{\mathrm{M}}^{\ast }$.

The grid current controller requires the grid current reference as an input, which is translated from $P_{\mathrm{G}}^{\ast }$ using the power balance of the grid ${\widehat{I}}_{\mathrm{G}}^{\ast }=2P_{\mathrm{G}}^{\ast }/{\widehat{V}}_{\mathrm{G}}$. This result is then limited to a maximum current amplitude ${\widehat{I}}_{\mathrm{Gmax}}$, which is the minimum of (a) the maximum rectifier input current and (b) the current amplitude that corresponds to the power the inverter can deliver to the motor (the sum of the instantaneous mechanical output power and the system losses). The instantaneous grid current request, then, results from $i_{\mathrm{G}}^{\ast }=v_{\mathrm{G}}{\widehat{I}}_{\mathrm{G}}^{\ast }/{\widehat{V}}_{\mathrm{G}}$ and equals the inductor current as $i_{\mathrm{L}}^{\ast }=i_{\mathrm{G}}^{\ast }$. The grid current controller $\mathrm{RiL}$ compares the requested current to the measured inductor current, adds the the resulting boost inductor voltage $v_{\mathrm{LB}}^{\ast }$ to the measured terminal voltage $v_{\mathrm{G}}$, and translates this sum to the boost duty-cycle $d_{\mathrm{B}}$ and the switching state of the unfolder $S_{\mathrm{UN}}$. For interleaved boost bridge-legs, an additional balancer control unit would need to be included [55].

The power feedforward term $p_{\mathrm{G}}^{\ast }=v_{\mathrm{G}}{i}_{\mathrm{G}}^{\ast }$ to the motor current control block, subsequently, is derived from the measured terminal voltage $v_{\mathrm{G}}$ and the reference grid current $i_{\mathrm{G}}^{\ast }$. This feedforward term significantly reduces the control effort of the DC-link voltage controller, where the capacitor power request $p_{\mathrm{C}}^{\ast }$ is derived from the DC-link voltage reference $V_{\mathrm{DC}}^{\ast }$ and the measured and unfiltered DC-link voltage $v_{\mathrm{DC}}$. The reference motor power $p_{\mathrm{M}}^{\ast }$, the input to the motor current controller, results then from Equation (7).

The motor current controller, here, avoids field weakening [56] for simplicity; therefore, $i_{\mathrm{Md}}^{\ast }=0\mathrm{A}$ is selected, and the produced torque is only proportional to the q-current $i_{\mathrm{Mq}}$. The motor power balance results in $p_{\mathrm{M}}^{\ast }=3v_0{\mathrm{q}}^{\ast }{i}_{\mathrm{Mq}}^{\ast }/2$ as $i_{\mathrm{Md}}^{\ast }=0\mathrm{A}$, with $v_0{\mathrm{q}}^{\ast }\approx V_{\mathrm{P}}=p{\Psi }_{\mathrm{PM}}{\omega }^{\ast }$ as the induced voltage, which is dependent on the speed, the number of pole pairs p, and the permanent magnet flux ${\Psi }_{\mathrm{PM}}$ (or, more conventionally, the product of the latter two, the motor constant $k_{\mathrm{V}}=V_{\mathrm{P}}/{\omega }^{\ast }=p{\Psi }_{\mathrm{PM}}$).

Inside the motor current controller, the current setpoints $i_{\mathrm{Md}}^{\ast }=0\mathrm{A}$ and $i_{\mathrm{Mq}}^{\ast }$ are compared to the the instantaneous current values $i_{\mathrm{Md}}$ and $i_{\mathrm{Mq}}$, which are derived from the phase current measurements by the Park transform. The current controllers $\mathrm{Rid}$ and $\mathrm{Riq}$ then derive the reference motor inner inductor voltages $v_{\mathrm{Ld}}^{\ast }$ and $v_{\mathrm{Lq}}^{\ast }$, which are translated to the inverter duty-cycles $d_{\mathrm{a}}$, $d_{\mathrm{b}}$, and $d_{\mathrm{c}}$ after including the motor voltage feedforward $V_{\mathrm{P}}$ and the decoupling terms $v_{\mathrm{Dd}}=-\omega p{L}_{\mathrm{q}}{i}_{\mathrm{Mq}}^{\ast }$ and $v_{\mathrm{Dq}}=\omega p{L}_{\mathrm{d}}{i}_{\mathrm{Md}}^{\ast }$ (which depend on the reference currents and the motor inductances $L_{\mathrm{d}}$ and $L_{\mathrm{q}}$) for the required motor voltages $v_{\mathrm{Md}}$ and $v_{\mathrm{Mq}}$. The motor current control supports the inclusion of an additional Common-Mode (CM) voltage component for overmodulation [57], if desired.

2.3.4. Simulation Results

With the concept and the detailed control structure for the proposed MPPB concept each outlined, the approach was verified through simulation for the nominal operating point of Table 2. The circuit parameters of Table 3 were used, highlighting especially that only 60 μF of the DC-link capacitance is required for an 8 kW system. The controller design for the simulation (and later, for the implementation) is described in further detail in Appendix B.

The corresponding waveforms at a mechanical output power of $7.5$ kW and 3700 rpm are shown in Figure 5, where the grid current $i_{\mathrm{G}}$ is in phase with the grid voltage $v_{\mathrm{G}}$ for unity power factor operation and the product of the grid current and grid voltage resulting in pulsating input power, translated to a torque pulsation. The torque $t_{\mathrm{M}}$ pulsated, as expected, around the average of $T_{\mathrm{L}}=19.4\mathrm{Nm}$. When $t_{\mathrm{M}}\left(t\right)>T_{\mathrm{L}}$, the motor speed increased, and when $t_{\mathrm{M}}\left(t\right)<T_{\mathrm{L}}$, the motor speed decreased, resulting here in a symmetric speed ripple amplitude of $\Delta n=\pm 61\mathrm{rpm}$ around the average of 3700 rpm. The DC-link voltage contains a low-frequency peak-to-peak ripple of around 34 Vpkpk, a direct consequence of the limited control bandwidth of the DC-link voltage control and a limitation that can be addressed through the improvements discussed in Appendix B. Overall, the simulation results verified the correct and expected operation, and next, the performance of the MPPB-operated system was evaluated.

2.4. Performance Evaluation

Aside from the significant reduction in required DC-link capacitance, the MPPB concept has no effect on the performance of the PFC rectifier or on the performance of the EMI filter. The effect of the proposed concept can be analyzed on only the motor and the inverter, then starting with the time-domain impact and subsequently moving to an analysis of the losses.

2.4.1. Time-Domain Waveforms

Under conventional operation, the magnitude of the q-current is given by $I_{\mathrm{M}0}=2P_0/\left(3V_{\mathrm{P}}\right)$, and thus, $i_{\mathrm{Md}}\left(t\right)\equiv 0\mathrm{A}$ and $i_{\mathrm{Mq}}\left(t\right)=I_{\mathrm{M}0}$. The phase currents are derived using the inverse Park transform [54] with $\epsilon =p\overline{\omega }t+{\epsilon }_0$:

$$\left[\begin{array}{c}\hfill i_{\mathrm{Ma}}\\ \hfill i_{\mathrm{Mb}}\\ \hfill i_{\mathrm{Mc}}\end{array}\right]=\left[\begin{array}{cc}cos\left(\epsilon \right)& -sin\left(\epsilon \right)\\ cos\left(\epsilon -\frac{2\pi }{3}\right)& -sin\left(\epsilon -\frac{2\pi }{3}\right)\\ cos\left(\epsilon +\frac{2\pi }{3}\right)& -sin\left(\epsilon +\frac{2\pi }{3}\right)\end{array}\right]\left[\begin{array}{c}\hfill i_{\mathrm{Md}}\\ \hfill i_{\mathrm{Mq}}\end{array}\right]$$

(8)

This results in three purely sinusoidal and symmetrical phase currents, each with the peak value $I_{\mathrm{M}0}$, as shown in Figure 6a. These phase currents are evaluated—and later, compared to the same values under MPPB operation—by the absolute average current $I_{\mathrm{PH}0\mathrm{avg}}$, the RMS value $I_{\mathrm{PH}0\mathrm{rms}}$, and the peak current $I_{\mathrm{PH}0\mathrm{pk}}$ as (with T the minimum period of the signal):

$$\begin{array}{ccc}\hfill I_{\mathrm{PH}0\mathrm{avg}}& =& \frac{1}{T}{\int }_0^T\left|i_{\mathrm{Ma}}\left(\tau \right)\right|d\tau =\frac{2}{\pi }{I}_{\mathrm{M}0}\hfill \end{array}$$

(9)

$$\begin{array}{ccc}\hfill I_{\mathrm{PH}0\mathrm{rms}}& =& \sqrt{\frac{1}{T}{\int }_0^T{i}_{\mathrm{Ma}}^2\left(\tau \right)d\tau }=\frac{1}{\sqrt{2}}{I}_{\mathrm{M}0}\hfill \end{array}$$

(10)

$$\begin{array}{ccc}\hfill I_{\mathrm{PH}0\mathrm{pk}}& =& \max i_{\mathrm{Ma}}\left(t\right)=I_{\mathrm{M}0}.\hfill \end{array}$$

(11)

To analyze the proposed MPPB operation, constant speed (with $\omega \left(t\right)\approx \overline{\omega }$) was assumed, which resulted in a constant induced voltage $V_{\mathrm{P}}=k_{\mathrm{V}}\omega \approx k_{\mathrm{V}}\overline{\omega }$, and the instantaneous q-current was $i_{\mathrm{Mq}}\left(t\right)=2p_{\mathrm{M}}\left(t\right)/\left(3V_{\mathrm{P}}\right)$. Using $p_{\mathrm{M}}\left(t\right)=P_0\left[1+cos\left(2\pi f_{\mathrm{P}}t\right)\right]$, the q-current proportional relationship to the instantaneous torque is:

$$i_{\mathrm{Mq}}\left(t\right)\approx I_{\mathrm{M}0}\left[1+cos\left(2\pi f_{\mathrm{P}}t\right)\right]\propto t_{\mathrm{M}}\left(t\right),$$

(12)

where the magnitude $I_{\mathrm{M}0}$ is the same as under conventional operation.

Because the q-current is now, under MPPB operation, pulsating at twice line frequency, the phase currents $i_{\mathrm{Ma}}$, $i_{\mathrm{Mb}}$ and $i_{\mathrm{Mc}}$ into the motor are no longer purely sinusoidal. These phase currents were found by applying the inverse Park transform to the q-current and are shown in Figure 6b for $f_{\mathrm{P}}=100\mathrm{Hz}$ and $p\overline{\omega }=2\pi 120\mathrm{Hz}$. The phase current, more precisely, is then $i_{\mathrm{Ma}}=-i_{\mathrm{Mq}}sin\left(p\overline{\omega }t+{\epsilon }_0\right)$, or:

$$\begin{array}{ccc}\hfill i_{\mathrm{Ma}}\left(t\right)& =& -I_{\mathrm{M}0}sin\left(p\overline{\omega }t+{\epsilon }_0\right)\hfill \\ & & -\frac{I_{\mathrm{M}}0}{2}\left[sin\left(p\overline{\omega }t+2\pi f_{\mathrm{P}}t+{\epsilon }_0\right)+sin\left(p\overline{\omega }t-2\pi f_{\mathrm{P}}t+{\epsilon }_0\right)\right].\hfill \end{array}$$

(13)

In addition to the fundamental $p\overline{\omega }$ frequency, the phase currents now contain two additional harmonic components at the frequencies $\left|p\overline{\omega }+2\pi f_{\mathrm{P}}\right|$ and $\left|p\overline{\omega }-2\pi f_{\mathrm{P}}\right|$ with amplitude $I_{\mathrm{M}0}/2$, as shown with the spectral decomposition of the phase current for phase a in Figure 6c. For certain frequency ratios, these individual sines may collapse into a single frequency, become DC components, or even result in standing waves and an asymmetric phase stress. The precise effect of different frequency ratios is discussed in Appendix C, with the result that such effects occur only in the vicinity of certain speed values $\overline{\omega }$, which are all below or equal to the angular pulsation frequency ${\omega }_{\mathrm{P}}=2\pi f_P$, and the assumption $|p\overline{\omega }|>{\omega }_{\mathrm{P}}$ was used for the remaining analysis here.

Only the sinusoid with frequency $p\overline{\omega }$ is phase aligned with the induced voltage of the corresponding phase, and therefore, only this component generates average torque to drive the load. Because this component is not influenced by the pulsating q-current, there is, as expected, no degradation in the mechanical average torque—but the additional components do increase current stress in the inverter and motor. The RMS current stress was calculated by a superposition of the purely sinusoidal waveforms, with a $\sqrt{3/2}$ factor increase in RMS current. The average current remains unchanged while the peak current doubles as a result of the pulsating q-current. This large increase in peak current has a limited effect on the iron in the motor, since motors are typically designed in the thermal (rather than the saturation) limit and the flux is primarily defined by the permanent magnet ${\Psi }_{\mathrm{PM}}$. The key current equations are summarized below, and the relative increase of each current is shown in Figure 7a.

$$\begin{array}{ccc}\hfill I_{\mathrm{PHavg}}& =& \frac{1}{T}{\int }_0^T\left|i_{\mathrm{Ma}}\left(\tau \right)\right|d\tau =\frac{2}{\pi }{I}_{\mathrm{M}0}\hfill \end{array}$$

(14)

$$\begin{array}{ccc}\hfill I_{\mathrm{PHrms}}& =& \sqrt{\frac{1}{T}{\int }_0^T{i}_{\mathrm{Ma}}^2\left(\tau \right)d\tau }=\frac{1}{\sqrt{2}}\sqrt{\frac{3}{2}}{I}_{\mathrm{M}0}\hfill \end{array}$$

(15)

$$\begin{array}{ccc}\hfill I_{\mathrm{PHpk}}& =& \max i_{\mathrm{Ma}}\left(t\right)=2I_{\mathrm{M}0}.\hfill \end{array}$$

(16)

With the key current ratios defined, the relative inverter and motor losses between conventional and MPPB operation were analyzed.

2.4.2. Motor Loss Analysis

The motor losses $P_{\mathrm{VM}}$ include both speed-dependent no-load losses $P_{\mathrm{VMnl}}$ and load-dependent conduction losses $P_{\mathrm{VMcond}}=3R_{\mathrm{s}}{I}_{\mathrm{PHrms}}^2$, with $R_{\mathrm{s}}$ as the stator winding resistance. The motor losses under conventional operation $P_{\mathrm{VM}0}$ and under the proposed MPPB operation $P_{\mathrm{VM}}$ are:

$$\begin{array}{ccc}\hfill P_{\mathrm{VM}0}& =& P_{\mathrm{VMnl}}+\frac{3}{2}{R}_{\mathrm{s}}{I}_{\mathrm{M}0}^2\hfill \end{array}$$

(17)

$$\begin{array}{ccc}\hfill P_{\mathrm{VM}}& =& P_{\mathrm{VMnl}}+\frac{9}{4}{R}_{\mathrm{s}}{I}_{\mathrm{M}0}^2,\hfill \end{array}$$

(18)

where the MPPB operation incurs a 50% loss increase in conduction losses due to the increase in the RMS current. If an equal loss distribution between the no-load losses and the load-dependent conduction losses at the nominal operation point is assumed, which is typically close to an optimum design, MPPB operation incurs a motor loss penalty of only 25%. This loss ratio, along with the inverter loss ratios of the next section, is shown in Figure 7b.

2.4.3. Inverter Loss Analysis

The inverter semiconductor losses $P_{\mathrm{VI}}$ comprise conduction $P_{\mathrm{VIcond}}$ and switching losses $P_{\mathrm{VIsw}}$. The conduction losses are, most generally, written as $P_{\mathrm{VIcond}}=3V_{\mathrm{f}}{I}_{\mathrm{PHavg}}+3R_{\mathrm{on}}{I}_{\mathrm{PHrms}}^2$, where $V_{\mathrm{f}}$ is the on-state voltage drop and $R_{\mathrm{on}}$ is the (differential) on-resistance. The switching losses are written with a quadratic loss function $e_{\mathrm{sw}}\left(i\right)=k_0+k_{1}i+k_2{i}^2$ [59], which leads to $P_{\mathrm{VIsw}}=3f_{\mathrm{Isw}}\left(k_0+k_1{I}_{\mathrm{PHavg}}+k_2{I}_{\mathrm{PHrms}}^2\right)$ with the inverter switching frequency $f_{\mathrm{Isw}}$. A quick review of these equations shows that the MPPB concept would only affect the ohmic part of the conduction losses and the quadratic part of the switching losses, both with an increase of 50%, through the increase in the RMS current.

If the semiconductors are implemented as IGBTs, conduction losses are given—to a first approximation—by the on-state voltage drop, and the switching losses can be approximated by the linear part alone. For an IGBT-implemented inverter, then, the inverter losses are identical between conventional ($P_{\mathrm{VI}0\mathrm{igbt}}$) and MPPB operation ($P_{\mathrm{VIigbt}}$):

$$P_{\mathrm{VI}0\mathrm{igbt}}=\frac{6}{\pi }{V}_{\mathrm{f}}{I}_{\mathrm{M}0}+3f_{\mathrm{Isw}}\frac{2}{\pi }{k}_1{I}_{\mathrm{M}0}=P_{\mathrm{VIigbt}}.$$

(19)

IGBTs, however, suffer from high overall losses [60], and inverters with SiC MOSFET-based bridge-legs and a $\mathrm{d}{v}_{\mathrm{DS}}/\mathrm{d}t$ limitation should be considered as well.

For a SiC MOSFET-based bridge-leg and external Miller capacitors to limit the voltage slew rate, the conduction losses can be considered ohmic, and the switching losses are described well by the constant and linear part [61], for inverter losses under conventional ($P_{\mathrm{VI}0\mathrm{fet},\mathrm{i}}$) and MPPB operation ($P_{\mathrm{VIfet},\mathrm{i}}$), as:

$$\begin{array}{ccc}\hfill P_{\mathrm{VI}0\mathrm{fet},\mathrm{i}}& =& \frac{3}{2}{R}_{\mathrm{on}}{I}_{\mathrm{M}0}^2+3f_{\mathrm{Isw}}\left(k_0+\frac{2}{\pi }{k}_1{I}_{\mathrm{M}0}\right)\hfill \end{array}$$

(20)

$$\begin{array}{ccc}\hfill P_{\mathrm{VIfet},\mathrm{i}}& =& \frac{9}{4}{R}_{\mathrm{on}}{I}_{\mathrm{M}0}^2+3f_{\mathrm{Isw}}\left(k_0+\frac{2}{\pi }{k}_1{I}_{\mathrm{M}0}\right).\hfill \end{array}$$

(21)

The motor acts as a resistive–inductive load with a reactive power demand and, therefore, requires a current commutation path for the freewheeling current. The high voltage drop of the body diode of the utilized SiC MOSFETs is typically overcome with an anti-parallel SiC Schottky diode, but the MOSFET itself can also be utilized as a synchronous rectifier. In this case, the freewheeling diode only conducts during the dead time, and the additional losses from the body diode conduction can be neglected (this assumption was extensively analyzed in [62] and verified in Section 3). In this context, it should be also mentioned that early high-voltage SiC MOSFETs were associated with bipolar degradation on their intrinsic body diodes [63], but this problem has been solved for state-of-the-art $1.2$ kV devices [64].

Conduction losses increase by 50% under the proposed MPPB operation. If each loss contribution (conduction, constant switching losses, and current-dependent switching losses) is assumed to be $1/3$ of the overall inverter losses [61] at nominal operation, the inverter loss penalty is around 17% for MPPB operation with a SiC MOSFET-based bridge-leg and external Miller capacitors to limit the voltage slew rate.

Finally, a realization with a hard-switching SiC MOSFET-based bridge-leg with an LC output filter designed for a $\mathrm{d}v/\mathrm{d}t$-limitation of the voltage applied to the motor terminals [58] or full-sine-wave output voltage shaping was analyzed. The doubling of the peak current will negatively impact the performance of the filter inductor. Here, conduction losses remain ohmic and the switching losses contain all of the terms, for conventional ($P_{\mathrm{VI}0\mathrm{fet},\mathrm{ii}}$) and MPPB inverter losses ($P_{\mathrm{VIfet},\mathrm{ii}}$) of:

$$\begin{array}{ccc}\hfill P_{\mathrm{VI}0\mathrm{fet},\mathrm{ii}}& =& \frac{3}{2}{R}_{\mathrm{on}}{I}_{\mathrm{M}0}^2+3f_{\mathrm{Isw}}\left(k_0+\frac{2}{\pi }{k}_1{I}_{\mathrm{M}0}+\frac{1}{2}{k}_2{I}_{\mathrm{M}0}^2\right)\hfill \end{array}$$

(22)

$$\begin{array}{ccc}\hfill P_{\mathrm{VIfet},\mathrm{ii}}& =& \frac{9}{4}{R}_{\mathrm{on}}{I}_{\mathrm{M}0}^2+3f_{\mathrm{Isw}}\left(k_0+\frac{2}{\pi }{k}_1{I}_{\mathrm{M}0}+\frac{3}{4}{k}_2{I}_{\mathrm{M}0}^2\right).\hfill \end{array}$$

(23)

If an equal loss contribution is assumed for all four loss components (conduction losses and the three switching loss terms) at nominal operation, MPPB operation carries a 25% loss penalty over conventional operation for the inverter, similar to the penalty in the motor.

A summary of these inverter loss penalties for different bridge-leg implementations is shown in Figure 7b, where, although the MPPB concept increases the conduction losses by 50%, the maximum total loss penalty is 25%—while realizing a potential volume reduction of up to 1 $\mathrm{L}$ (or 61 in${}^3$) by eliminating the DC-link electrolytic capacitors.

3. System Design and Implementation

With the power density improvements—and the possibility of motor integration—of the MPPB-operated system attractive, the system proposed in Figure 2a was next designed and implemented. This hardware demonstrator allows a direct comparison between conventional and MPPB systems on the volume and loss distributions. The motor-integrated converter system is the focus of this section, with brief guidelines given for motor selection and PFC rectifier and inverter designs.

3.1. Motor Selection and Characterization

With the output power $P_{0,\mathrm{N}}=7.5\mathrm{k}\mathrm{W}$ and speed requirements $n_{\mathrm{N}}=3700\mathrm{rpm}$ leading to a torque specification of $T_{\mathrm{L},\mathrm{N}}=19.4\mathrm{Nm}$, the 1FT7-084 from Siemens [65] was selected.

At nominal operation $n_{\mathrm{N}}=3700\mathrm{rpm}$, the motor frequency with $p=5$ is $p{\omega }_{\mathrm{N}}=2\pi 308\mathrm{Hz}$, which is sufficiently above $f_{\mathrm{P}}=100\mathrm{Hz}$ to guarantee symmetric phase stresses in the motor and inverter (see Appendix C). The motor inertia of $J_{\mathrm{M}}=4.5\mathrm{mkg}{\mathrm{m}}^2$ corresponds to a speed ripple amplitude, using Equation (5), of $\Delta \omega =7.3\mathrm{rad}/\mathrm{s}=70\mathrm{rpm}$, or 1.9% of the nominal speed. The minimal achievable speed in stationary operation for constant torque $T_{\mathrm{L}}\left(\omega \right)=T_{\mathrm{L},\mathrm{N}}$ is, according to Appendix A, ${\overline{\omega }}_{\min }=5\mathrm{rad}/\mathrm{s}\approx 50\mathrm{rpm}$. The torque constant is given with $k_{\mathrm{T}}=T/I_{\mathrm{M}0}=0.92\mathrm{Nm}/\mathrm{A}$ and the given speed constant $k_{\mathrm{V}}$, which relates the induced pole-wheel peak voltage $V_{\mathrm{P}}$ to the speed n as $k_{\mathrm{V}}=V_{\mathrm{P}}/n=67.8\mathrm{mV}/\mathrm{rpm}$, resulting in a nominal phase voltage amplitude of $V_{\mathrm{P},\mathrm{N}}=250\mathrm{Vpk}$. The nominal DC-link voltage can then be selected as $V_{\mathrm{DC},\mathrm{N}}=650\mathrm{V}$ (cf. Table 2, allowing boost PFC operation up to the nominal input voltage of $V_{\mathrm{G},\mathrm{N}}=400\mathrm{Vrms}$ with a 15% margin. For input voltages above nominal, the DC-link voltage is linearly increased up to 800 V at $V_{\mathrm{Gmax}}=530\mathrm{Vrms}$, or a peak voltage of 750 Vpk.

The motor was measured to validate the datasheet and build a complete loss model. The stator phase resistance was measured at $R_{\mathrm{s}}=0.2\Omega$ at 40 ${}^{\circ }\mathrm{C}$ (close to ambient since the winding temperature does not significantly increase during short-time operation and was also respected for the experimental analyses), and the motor inductances were measured at $L_{\mathrm{d}}\approx L_{\mathrm{q}}\approx 3.0\mathrm{mH}$, both within 10% of the datasheet values. The speed-dependent, no-load losses from iron losses and friction [66] were measured with the motor driven mechanically and the torque measured at nominal speed $n_{\mathrm{N}}$, resulting in a no-load torque of $T_{\mathrm{Mnl}}=0.765\mathrm{Nm}$ and no-load losses of $P_{\mathrm{VMnl}}={\omega }_{\mathrm{N}}{T}_{\mathrm{Mnl}}=296\mathrm{W}$.

At nominal speed, the motor current amplitude is $I_{\mathrm{M}0}=\left(T_{\mathrm{L}}+T_{\mathrm{Mnl}}\right)/k_{\mathrm{T}}$, which at nominal load is $I_{\mathrm{M}0,\mathrm{N}}=21.9\mathrm{A}$. Under conventional operation, this RMS phase current is $I_{\mathrm{PH}0\mathrm{rms},\mathrm{N}}=I_{\mathrm{M}0,\mathrm{N}}/\sqrt{2}=15.5\mathrm{Arms}$ (cf. Equation (10)), and under the proposed MPPB operation, the phase current is $I_{\mathrm{PHrms},\mathrm{N}}=\sqrt{3}{I}_{\mathrm{M}0,\mathrm{N}}/2=19\mathrm{Arms}$ (cf. Equation (15)). With the no-load losses summed with the conduction losses for the total motor losses, $P_{\mathrm{VM}}=P_{\mathrm{VMnl}}+P_{\mathrm{VMcond}}$, or:

$$P_{\mathrm{VM}}={\omega }_{\mathrm{N}}{T}_{\mathrm{Mnl}}+\frac{9}{4}{R}_{\mathrm{s}}{\left(\frac{T_{\mathrm{L}}+T_{\mathrm{Mnl}}}{k_{\mathrm{T}}}\right)}^2.$$

(24)

The no-load torque increases the motor losses $P_{\mathrm{VM}}$ twice—once directly, through the $P_{\mathrm{VMnl}}$ term, and additionally by increasing the motor current as $T_{\mathrm{Mnl}}/k_{\mathrm{T}}$ and, therefore, increasing the conduction losses $P_{\mathrm{VMcond}}=9R_{\mathrm{s}}{I}_{\mathrm{M}0}^2/4$.

The MPPB-operated motor losses at the average torque are shown in Figure 8, with the nominal losses under MPPB operation of $P_{\mathrm{VM},\mathrm{N}}=517\mathrm{W}$ compared to 443 W under conventional operation. This motor loss increase is 16.7%, less than the 25% predicted in Figure 7b since the no-load losses comprise more than half of the total motor losses.

3.2. Converter Design

The complete converter topology is shown in Figure 9 with the components of Table 3, and here, the key pieces of the component selection are highlighted.

3.2.1. Inverter Design

The inverter switching frequency must be outside the audible range (above 16 kHz [67]), but is determined more strictly by the control bandwidth. With a pulsation frequency of $f_{\mathrm{P}}=100\mathrm{Hz}$, the DC-link voltage control bandwidth was designed to be $5\times$ higher at 500 Hz, the motor current control bandwidth $5\times$ higher than that at 2500 Hz, and the inverter switching frequency $10\times$ higher for an inverter switching frequency of $f_{\mathrm{Isw}}\approx 25\mathrm{kHz}$. Due to EMI considerations [68], $f_{\mathrm{Isw}}=24\mathrm{kHz}$ was selected.

The 1200 $\mathrm{V}$ power semiconductors are required to withstand a DC-link voltage that will be as high as 800 V (plus low- and high-frequency voltage ripple), and SiC MOSFETs are employed instead of IGBTs for high performance [60]. These MOSFETs operate at high voltage slew rates, or $\mathrm{d}{v}_{\mathrm{DS}}/\mathrm{d}t$ values, which can lead to an unequal distribution of the voltage across the motor windings and partial discharge phenomena [69], resulting in progressive aging of the motor winding insulation [37]. Different solutions to this challenge were discussed and compared in [38], with gate drive modifications preferred [61], for motor-integrated drives that support $\mathrm{d}{v}_{\mathrm{DS}}/\mathrm{d}t$ values as high as 15 $\mathrm{V}$ $\mathrm{n}$$\mathrm{s}$⁻¹ (since there are no cable reflections to consider).

Table 3. Component list.

Motor Inertia	$J_{\mathrm{M}}$	$4.5$ mkgm2	Siemens 1FT7-084 [65]
CM-Motor Capacitance	$C_{\mathrm{CM}0}$	$1.9$ nF	Siemens 1FT7-084 (measured)
Inverter Transistors	${\mathrm{T}}_{\mathrm{aH}}$, ${\mathrm{T}}_{\mathrm{aL}}$, ${\mathrm{T}}_{\mathrm{bH}}$, ${\mathrm{T}}_{\mathrm{bL}}$, ${\mathrm{T}}_{\mathrm{cH}}$, ${\mathrm{T}}_{\mathrm{cL}}$	16 m$\Omega /1.2$ kV	Cree C3M0016120K [70]
PFC Unfolder Transistors	${\mathrm{T}}_{\mathrm{uH}}$, ${\mathrm{T}}_{\mathrm{uL}}$	16 m$\Omega /1.2$ kV	Cree C3M0016120K [70]
PFC Boost Transistors	${\mathrm{T}}_{\mathrm{iH}}$, ${\mathrm{T}}_{\mathrm{iL}}$, ${\mathrm{T}}_{\mathrm{iiH}}$, ${\mathrm{T}}_{\mathrm{iiL}}$, ${\mathrm{T}}_{\mathrm{iiiH}}$, ${\mathrm{T}}_{\mathrm{iiiL}}$	$32\mathrm{m}\Omega$/$1.2$ kV	Cree C3M0032120K [71]
DC-Link Capacitance	$C_{\mathrm{DC}}$	3 × 20 μF/900 V	Epcos B32776E9206K000, Foil
Boost Inductor	$L_{\mathrm{B}}$	428 μH (each)	4 E-Cores/30 Turns Flat Wire
DM-Filter Capacitance	$C_1$	4 × 1 μF	Epcos B32914A5105M000, X1
DM-Filter Capacitance	$C_2$	1 μF	Epcos B32914A5105M000, X1
DM-Filter Inductance	$L_{\mathrm{DM}}$	$4.7\mathsf{\mu }\mathrm{H}$ (each)	Wuerth 74436410470
CM-Filter Capacitance	$C_{\mathrm{CM}1}$	2 × 20 n F	Vishay 440LS20-R, Y1
CM-Filter Capacitance	$C_{\mathrm{CM}2}$	2 × 20 n F (each)	Vishay 440LS20-R, Y1
CM-Filter Inductance	$L_{\mathrm{CM}0}$	$75\mathsf{\mu }\mathrm{H}$	6 × VAC L2025-W380, 1 Turn
CM-Filter Inductance	$L_{\mathrm{CM}1}$	$1.6$ mH	VAC L2045-V102, 9 Turns
CM-Filter Inductance	$L_{\mathrm{CM}2}$	$1.0$ mH	VAC L2045-V102, 7 Turns

Table 3. Component list.

Motor Inertia	$J_{\mathrm{M}}$	$4.5$ mkgm2	Siemens 1FT7-084 [65]
CM-Motor Capacitance	$C_{\mathrm{CM}0}$	$1.9$ nF	Siemens 1FT7-084 (measured)
Inverter Transistors	${\mathrm{T}}_{\mathrm{aH}}$, ${\mathrm{T}}_{\mathrm{aL}}$, ${\mathrm{T}}_{\mathrm{bH}}$, ${\mathrm{T}}_{\mathrm{bL}}$, ${\mathrm{T}}_{\mathrm{cH}}$, ${\mathrm{T}}_{\mathrm{cL}}$	16 m$\Omega /1.2$ kV	Cree C3M0016120K [70]
PFC Unfolder Transistors	${\mathrm{T}}_{\mathrm{uH}}$, ${\mathrm{T}}_{\mathrm{uL}}$	16 m$\Omega /1.2$ kV	Cree C3M0016120K [70]
PFC Boost Transistors	${\mathrm{T}}_{\mathrm{iH}}$, ${\mathrm{T}}_{\mathrm{iL}}$, ${\mathrm{T}}_{\mathrm{iiH}}$, ${\mathrm{T}}_{\mathrm{iiL}}$, ${\mathrm{T}}_{\mathrm{iiiH}}$, ${\mathrm{T}}_{\mathrm{iiiL}}$	$32\mathrm{m}\Omega$/$1.2$ kV	Cree C3M0032120K [71]
DC-Link Capacitance	$C_{\mathrm{DC}}$	3 × 20 μF/900 V	Epcos B32776E9206K000, Foil
Boost Inductor	$L_{\mathrm{B}}$	428 μH (each)	4 E-Cores/30 Turns Flat Wire
DM-Filter Capacitance	$C_1$	4 × 1 μF	Epcos B32914A5105M000, X1
DM-Filter Capacitance	$C_2$	1 μF	Epcos B32914A5105M000, X1
DM-Filter Inductance	$L_{\mathrm{DM}}$	$4.7\mathsf{\mu }\mathrm{H}$ (each)	Wuerth 74436410470
CM-Filter Capacitance	$C_{\mathrm{CM}1}$	2 × 20 n F	Vishay 440LS20-R, Y1
CM-Filter Capacitance	$C_{\mathrm{CM}2}$	2 × 20 n F (each)	Vishay 440LS20-R, Y1
CM-Filter Inductance	$L_{\mathrm{CM}0}$	$75\mathsf{\mu }\mathrm{H}$	6 × VAC L2025-W380, 1 Turn
CM-Filter Inductance	$L_{\mathrm{CM}1}$	$1.6$ mH	VAC L2045-V102, 9 Turns
CM-Filter Inductance	$L_{\mathrm{CM}2}$	$1.0$ mH	VAC L2045-V102, 7 Turns

The optimal chip area was selected for the inverter power semiconductors, all of which were implemented as next-generation $16\mathrm{m}\Omega$ SiC MOSFETs (C3M0016120K [70]). A gate driver with an output clamp variant was selected [72] that drives the transistors at the maximum positive ($V_{\mathrm{G},\mathrm{on}}=15\mathrm{V}$) and minimum negative ($V_{\mathrm{G},\mathrm{off}}=-4\mathrm{V}$) gate drive voltages for enhanced noise immunity. A $15\Omega$ gate resistor was added for turn-on and turn-off to stay below $\mathrm{d}v/\mathrm{d}t=15\mathrm{V}\mathrm{n}\mathrm{s}$⁻¹, as investigated in [61].

As previously mentioned, synchronous rectification was employed for the MOSFETs within the inverter [62], with the body diode therefore only conducting during the dead time $t_{\mathrm{D}}$. Under the worst-case condition, where the body diode conducts the full-phase current within both dead time intervals of a switching period and with the diode forward voltage drop $V_{\mathrm{F}}=4.6\mathrm{V}$ [70] and the selected inverter dead time of $t_{\mathrm{D}}=400\mathrm{ns}$, the losses under nominal operation are $P_{\mathrm{VIdiode}}=3f_{\mathrm{Isw}}2t_{\mathrm{D}}{\mathrm{V}}_{\mathrm{F}}{I}_{\mathrm{PHavg}}=3.7\mathrm{W}$ (where $I_{\mathrm{PHavg}}$ is from Equation (14)). These losses represent less then 5% of the calculated inverter losses $P_{\mathrm{VI}}=81.6\mathrm{W}$ and can be safely neglected.

3.2.2. DC-Link Capacitor Selection

The minimum DC-link capacitance was determined by the high-frequency-voltage ripple caused by the PFC rectifier and the inverter [73]. Due to disturbances and the limited control bandwidth of the DC-link voltage control, though, there was a remaining low-frequency voltage ripple (see Figure 5). This ripple could be addressed with increased bandwidth; however, in the end, this would require an increase in switching frequency, and the corresponding increase in switching losses would eliminate this option. Instead, to keep the peak-to-peak voltage ripple below 40 $\mathrm{V}$, an increased DC-link capacitance of $C_{\mathrm{DC}}=60\mathsf{\mu }\mathrm{F}$ was selected based on circuit simulations. This capacitance requirement was only $7.5$ $\mathsf{\mu }$$\mathrm{F}$ $\mathrm{k}$$\mathrm{W}$ ⁻¹.

The chosen capacitors must be rated for at least 800 V, eliminating both ceramic X6S capacitors (which are only available up to 400 $\mathrm{V}$, and would therefore require hundreds of series-stacked capacitors) and CeraLink capacitors, where only small capacitance values are available. Three 20 $\mathsf{\mu }$$\mathrm{F}$ foil capacitors B32776E9206K000 [74] were selected, resulting in a total volume of only $0.13$ $\mathrm{L}$ (or 8 in${}^3$)—equal to just 13% of the required electrolytic capacitor volume under conventional operation.

3.2.3. PFC Rectifier Design

Because the rectifier is not affected by the MPPB approach, a conventional PFC rectifier design was implemented (even in [75], the electrolytic capacitors comprised 25% of the overall converter volume). This rectifier must be designed to provide the maximum power across the entire input voltage range (see Figure 1b), with a maximum input current of 32 Arms (or 45 Apk).

The unfolder was implemented with the lowest-possible $R_{\mathrm{DS},\mathrm{on}}$ device C3M0016120K [70], which resulted in a maximum of $19.6$ W of conduction losses at the voltage minimum and $9.6$ $\mathrm{W}$ at nominal operation. To limit the component stresses of the high-frequency bridge-leg, which is subject to high-frequency switching losses, an interleaved design with three branches was selected. This supports an increase in effective switching frequency for the same semiconductor losses [76], an improved loss distribution, and the reuse of the design for future three-phase-supplied VSD systems. Each bridge-leg was operated with a switching frequency of 48 $\mathrm{k}$$\mathrm{Hz}$ to keep the frequency multiple below the stricter EMI considerations at 150 $\mathrm{k}$$\mathrm{Hz}$. The high-frequency bridge-leg power semiconductors were again selected with the optimal chip area and implemented with $32\mathrm{m}\Omega$ four-pin devices (C3M0032120K [71]) for bridge-leg losses of $P_{\mathrm{VRhb}}=8.8\mathrm{W}$ at nominal operation.

The PFC rectifier inductor design was selected from the optimal front of a Pareto optimization based on the guidelines of [77], and this selected inductor was implemented with four stacked K4317E040 Kool-Mu cores with a relative permeability of forty and thirty turns of flat wire ($7\mathrm{mm}\times 0.5\mathrm{mm}$) (note that the permeability of Kool-Mu is current-dependent, and the inductance varies between 428 μH and 342 μH [78]). The inductor has a boxed volume of $100\mathrm{c}{\mathrm{m}}^3$ (33.6 × 41.5 × 72 mm) and $P_{\mathrm{VRind}}=9.5\mathrm{W}$ of expected losses at the nominal operating point. The filter capacitor $C_1$ is subject to a current ripple at the interleaved frequency of 144 kHz, with the first and second harmonic canceled, and a 4 μF capacitance was selected with an implementation of four parallel X-rated 1 μF capacitors.

3.2.4. EMI Filter

This high-frequency bridge-leg interleaving also eliminates the fourth and fifth harmonic components, and the Differential-Mode (DM) EMI filter therefore needs to be designed to meet CISPR 11/Class A [8] at the DM noise of the PFC rectifier at 288 kHz. With the design guidelines of [79], CISPR 11/Class A can be met with $C_2=1\mathsf{\mu }\mathrm{F}$ and $L_{\mathrm{DM}}=4.7\mathsf{\mu }\mathrm{H}$.

The common-mode noise is typically defined by the parasitic capacitance to the Earth, which is often dominated by the thermal interface material layer between the power semiconductors and the grounded heat sink. Here, the largest parasitic capacitance originates from the motor [80] at $C_{\mathrm{CM}0}=1.9\mathrm{nF}$. The CM EMI filter, therefore, is designed for the inverter noise occurring at the $7\mathrm{th}$ harmonic of 168 kHz. Again, following the design of [79], $C_{\mathrm{CM}1}=C_{\mathrm{CM}2}=40\mathrm{nF}$, $L_{\mathrm{CM}1}=1.2\mathrm{mH}$, and $L_{\mathrm{CM}2}=0.8\mathrm{mH}$ meets CISPR 11/Class A at 168 kHz. Both CM inductors were evaluated at 168 kHz, and they employ L2045-V102 nanocrystalline cores [81] with seven and nine turns, respectively. An additional CM choke on the motor side $L_{\mathrm{CM}0}$—to damp high-frequency CM currents inside the system and reduce the potential for radiated emissions [82]—was implemented with six L2025-W380 [81] cores with one turn each and provided a series impedance of $75\mathsf{\mu }\mathrm{H}$ inductance and a damping resistance of $100\Omega$ at 168 kHz.

3.3. Volume and Loss Distribution

These selected components are summarized in Table 3, resulting in the system loss breakdown at the nominal operating point (Table 2) of Figure 10a. The rectifier ($P_{\mathrm{VR}}=74.9\mathrm{W}$) and inverter ($P_{\mathrm{VI}}=81.6\mathrm{W}$) stages comprise a nearly equal contribution to the system losses, which are dominated by the motor ($P_{\mathrm{VM}}=534\mathrm{W}$). Beyond the no-load and conduction losses characterized in Figure 8, the motor incurs an additional 17 W of capacitive switching losses, where the parasitic motor capacitance is charged and discharged with the PWM voltage impressed by the inverter bridge-legs. The total drive system losses are $P_{\mathrm{VDS}}=703\mathrm{W}$, corresponding to a system efficiency at nominal operation of ${\eta }_{\mathrm{DS}}=91.4\%$.

The volume distribution of the system is shown in Figure 10b, with a boxed volume of the complete drive system at $8.2$ $\mathrm{L}$ (or 500 in${}^3$) resulting in a power density of 0.91 KW L⁻¹ (15 W in⁻³). The outer motor dimensions are 205 mm × 105 mm × 105 mm, for a total boxed volume of $4.9$ $\mathrm{L}$ (or 300 in${}^3$), that is 60% of the system. The converter, at $3.3$ $\mathrm{L}$ (or 200 in${}^3$), accounts for the remaining 40% of the system volume (including the encoder). Without the MPPB concept, the electrolytic capacitor volume alone would account for 1 $\mathrm{L}$ (or 61 in${}^3$), adding 30% to the converter and 12% to the total system—and preventing integration due to the lifetime considerations discussed previously.

3.4. Detailed Motor Integration and Implementation

The motor integration must allow a retrofitting of an existing motor within the same flange dimension, mandating an axial stator mount of the power electronics system (options for motor integration were surveyed in [83]). The implementation is shown in Figure 11, with the three-level stack up and construction detailed side by side.

Firstly, the end plate was replaced to provide an interface for the converter system. The first level of the integrated drive system (Figure 11a) contains the EMI filter components, which were distributed around the encoder. Cables were mounted to the corresponding side walls to connect to the grid CM inductors, which were also connected to the filter Printed Circuit Board (PCB). The filter PCB contains all of the remaining DM and CM filter components and was connected to the Earth and the motor housing. An Earth- and housing-connected copper plate (not shown) was installed between the EMI filter and the motor-side CM inductor to provide shielding, and similarly, an aluminum plate was installed between the first and second levels to (a) shield the filter from the bridge-leg high-frequency noise and (b) provide mechanical stability.

The second converter level (Figure 11b) contains all power components, including the power semiconductor bridge-legs, the boost inductors, and the DC-link capacitors. The bridge-legs were connected to the DC-link capacitors through the power PCB and to the motor windings through the motor-side CM inductor. Critically, the vast majority of the converter losses were generated in this second level, resulting in the highest temperature, and this was where the electrolytic capacitors would need to be placed to connect to the DC-link—making a system with electrolytic capacitors infeasible.

The third level (Figure 11c) contains the gate drive, measurement, control, and logic circuitry on two separate PCBs, with the control unit on the top. Converter losses are cooled via the surface—and the thermal resistance (and insulation) can be improved through potting, if desired—with the large thermal capacitance improving the thermal characteristics significantly, since the system is not operated at full power for extended periods. The final motor-integrated drive is shown in Figure 12.

4. Hardware Demonstration Verification

To evaluate the motor-integrated hardware demonstrator of Figure 12, the overall operation of the drive system across the continuously varying operating points, motor drive speeds, and torque fluctuation was evaluated. Full operation cannot be validated with a resistor–inductor (RL) load alone, and a complete motor test bench was employed here (instead of driving the compressor itself). This test bench comprises a motor bed, the Device-Under-Test (DUT), a speed and torque sensor (TM310 with a maximum torque bandwidth of 5 kHz from Magtrol [84]), and a load motor operated with a commercially available drive system from Siemens with a constant load torque [50]. An identical setup was employed for the no-load measurements of Section 3. First, the concept was validated with time-domain measurements and waveforms. Then, the loss model was verified, and EMI measurements were taken before validating the extended functionality (distorted grid voltage, ride-through operation, and battery supply operation) in Section 5.

Note that, due to the limited availability of the optimal $16\mathrm{m}\Omega$ power semiconductors specified in Table 3, all transistors were implemented as the $32\mathrm{m}\Omega$ device (C3M0032120K [71]) for the following measurements.

4.1. Time-Domain Waveforms and Operation

Firstly, the theoretical aspects of Section 2 were verified for the nominal operating point, as described in Table 2. The measured waveforms are shown in Figure 13, where the grid current ($20.6$ Arms) and voltage were in-phase for unity power factor operation (measured at 99.95%) at $8.2$ $\mathrm{k}$$\mathrm{W}$ input power, a steady DC-link voltage near the reference of 650 $\mathrm{V}$, and a speed equal to the reference of 3700 rpm with a speed ripple so small that it is not visible on this oscilloscope capture. The low-frequency ripple of the DC-link voltage is investigated in depth in Appendix B and corresponds here to 35 Vpkpk, nearly identical to the simulation results of 34 Vpkpk shown in Figure 5. The measured motor currents are shown in Figure 14, corresponding to a phase current stress of $18.5$ Arms and, again, matching the theoretical results in both behavior and predicted amplitude. Overall, the system behavior was correct and expected, validating the MPPB approach and the predicted operation.

4.2. Efficiency

With the foundational operation of the MPPB approach verified, the introduced loss model was verified at nominal speed and DC-link voltage across the required mechanical output power range. Grid power input was measured with the Yokogawa WT3000 precision power analyzer, and the mechanical quantities were measured with a speed and torque sensor. For all calculations, the measured stator phase resistance of $R_{\mathrm{s}}=0.2\Omega$ was used, as the system was verified for the short-time operation needed for this particular application. With the MPPB approach encompassing the complete system, the difference in the measured input (grid) and mechanical output powers was the drive system losses $P_{\mathrm{VDS}}$. These measured losses are shown across load torque—and, accordingly, mechanical output power—as the bullet points in Figure 15a. These measurements match the proposed loss model nearly precisely, validating both the proposed power converter and motor loss models under the proposed MPPB operation.

Next, the efficiency penalty associated with the significant power density increase of the MPPB concept was quantified, and the constructed MPPB system was compared to a conventional system with an electrolytic capacitor. The conventional system features lower phase current stresses, leading to lower currents and lower conduction losses in the motor and the inverter bridge-legs, but suffers from additional losses in the DC-link electrolytic capacitors. At the nominal output power, the system losses increase from 600 $\mathrm{W}$ for a grid-to-motor-shaft efficiency of 92.6% in the conventional system with an electrolytic capacitor to 703 $\mathrm{W}$ (91.4%) with the MPPB approach, for a loss increase of 103 $\mathrm{W}$, or 17%. This loss increase is the maximum across the operating load area, both in absolute and relative terms, with the load-dependent difference highlighted in blue in Figure 15a.

Figure 15b shows the motor, converter, and drive system efficiencies for conventional and MPPB operation over the output power range, where the converter efficiencies are nearly identical at around 98%. The overall efficiency is primarily limited by the motor itself, with the extra losses in MPPB operation contributed mostly by the additional phase current stresses. The MPPB system achieves a grid-to-motor-shaft efficiency above 90% for all loads above 5 kW (66% of the nominal load), a high and flat efficiency for the exceptional power density of the motor-integrated, electrolytic capacitor-less MPPB-operated system.

4.3. Conducted EMI

Because the drive system was tested in full operation on the motor bed, all measurements for EMI were conducted according to CISPR 16 for floor-standing equipment [85]. As discussed in the Introduction and highlighted in Table 1, the conducted EMI of the drive system in the frequency range of 150 kHz to 30 MHz must comply with the CISPR 11/Class A QP limit [8] (limits shown in Figure 16).

Both phases x and y of the drive system were scanned with a maximum peak detector with a step size of 1%, a bandwidth of 9 $\mathrm{k}$$\mathrm{Hz}$, and a measurement time of 10 $\mathrm{m}$$\mathrm{s}$, and we report the results in Figure 16.

Compliance with CISPR 11/Class A across the vast majority of the frequency space was verified, with only certain frequencies above 15 $\mathrm{M}$$\mathrm{Hz}$ exceeding the limit and the largest QP violation of $4.6$ dB at $19.3$ MHz in phase y. Selected measurement points in this regime were verified with a CISPR 11 quasi-peak detector (“QP”) with a 1 $\mathrm{s}$ measurement time. These peaks, however, are only caused by the EMI test condition, where the converter and motor were separated and connected with a cable for safety and measurement, and the completed system would achieve CISPR 11/Class A compliance across the full considered frequency range.

4.4. Transient Response

To this point, steady-state operation was assumed. Next, the transient behavior of the system was analyzed to verify the controller performance of the MPPB approach. Figure 17 shows the system behavior for both a change in the reference speed and a step change in the instantaneous load torque.

The system begins in steady-state operation at 3000 rpm and with a nominal load torque of $T_{\mathrm{L},\mathrm{N}}=19.4\mathrm{Nm}$, and there are steady-state speed, torque, and DC-link voltage ripples, as previously discussed. At $t=1\mathrm{s}$, the reference speed was increased linearly to $n^{\ast }=3700\mathrm{rpm}$ over $20\mathrm{ms}$, and the input power and average motor power increased to ramp the motor speed to match this reference. The maximum applied instantaneous torque reaches 56 Nm, and this transient causes a small disturbance in the DC-link voltage with a maximum deviation of 40 V. This voltage disturbance decays after around 100 ms, and the speed reaches steady-state after 350 ms.

At $t=1.4\mathrm{s}$, the load torque decays instantaneously to 10 Nm, which is approximately half of the nominal torque. Again, the MPPB approach elegantly controls the system, with a short speed increase to 4169 rpm. The motor torque reaches steady-state after 100 ms, and the speed reaches steady-state after 350 ms. It should be noted that the DC-link voltage ripple will scale with the motor torque; cf. Figure 17.

5. Extended Functionality

To this point, the assumption was that the system operates with a purely sinusoidal grid input voltage, which is the nominal operating condition, but not sufficient to meet the complete set of application requirements. In this section, drive system functionality was validated under three abnormal conditions that were required for the application—with a distorted grid voltage, with a voltage sag on the grid, and with short- or long-term grid interruptions. These were analyzed and verified in turn.

5.1. Operation with a Distorted Grid Voltage

Industrial voltage supplies—and especially railway grids [86]—can be heavily distorted [87], with a grid voltage better described with the addition of a noise term $v_{\mathrm{noise}}$ as $v_{\mathrm{G}}={\widehat{V}}_{\mathrm{G}}sin\left(2\pi f_{\mathrm{G}}\right)+v_{\mathrm{noise}}$. Under these conditions, a sinusoidal input current must still be drawn to minimize the grid stress [88]. While the noise components could be eliminated with a low-pass filter, this filter necessarily introduces an additional phase shift ($v_{\mathrm{G}}^{\ast }={\widehat{V}}_{\mathrm{G}}sin\left(2\pi f_{\mathrm{G}}+\phi \right)$) that degrades the power factor away from unity. Therefore, operation with a distorted grid voltage is addressed by reconstructing the fundamental of the grid voltage $v_{\mathrm{G}}^{\ast }$ around a Phase-Locked Loop (PLL) [89].

The PLL results in the input to the grid-current controller as $v_{\mathrm{G}}^{\ast }={\widehat{V}}_{\mathrm{G}}^{\ast }sin\left(2\pi f_{\mathrm{G}}\right)$, as shown in Figure 18. While PLLs based on a three-phase grid are simple to generate based on the orthogonal $\alpha \beta$-voltage system, the single-phase grid here requires an alternate approach. Instead, a Second-Order Generalized Integrator (SOGI) was used to derive $v_{\mathrm{ff}}$ and $v_{\mathrm{fi}}$ from the single-phase input voltage [90] based on the measured grid voltage $v_{\mathrm{G}}$ as the input. The SOGI outputs $v_{\mathrm{ff}}$, $v_{\mathrm{fi}}$, and $v_{\mathrm{pk}}$ to the PLL block, which is used to derive the grid frequency $f_{\mathrm{PLL}}$—fed back as the second input of the SOGI in a coupled system.

The PLL derives the phase angle $\theta =2\pi f_{\mathrm{G}}t$, and following ${\widehat{V}}_{\mathrm{G}}^{\ast }=v_{\mathrm{pk}}$, $v_{\mathrm{G}}^{\ast }/{\widehat{V}}_{\mathrm{G}}^{\ast }=sin\theta =sin\left(2\pi f_{\mathrm{G}}t\right)$, the grid voltage is reconstructed $v_{\mathrm{G}}^{\ast }={\widehat{V}}_{\mathrm{G}}^{\ast }sin\left(2\pi f_{\mathrm{G}}+\phi \right)$. This $v_{\mathrm{G}}^{\ast }$ was used for the grid current controller input and was also used for the power feedforward term, as shown in Figure 18.

5.2. Operation under Grid Voltage Sag or Interruption

More specifically, the drive must operate correctly under two additional fault conditions: voltage sags, where the input voltage falls below the specified range, and grid interruption, where the grid provides no voltage for a period. The exact conditions for each of these faults were discussed comprehensively in [91].

Continued operation under fault conditions increases system reliability, uptime, safety, and financial payback, and grid-tied industrial applications often require ride-through operation to minimize downtime (e.g., in general converter systems [92] or for drives [93]). Under a fault, the system must both (a) not trip, keeping the system operational, and (b) apply the full requested torque, without significant delay, after the interruption or sag. This effect on the MPPB concept, where no significant electrical or electrochemical energy storage is included, must be analyzed.

5.2.1. Voltage Sag

The proposed MPPB system achieves the required operation under grid voltage sag by design, with:

• A large specified grid tolerance (of approximately $\pm 30\%$; see Figure 1b) to cover the majority of sag cases with full-power operation;
• Even with the voltage outside of the specifications, the control structure detailed in Figure 18 will cover the voltage sag condition at reduced power, where the grid current limiter freezes speed control once the limit is reached. The control scheme guarantees rapid recovery, as shown later.

5.2.2. Grid Interruption

Railway systems regularly experience short-term grid interruptions in the range of several tens of milliseconds [94]. In conventional systems, these interruptions are easily covered by the DC-link capacitance energy storage—which is not present in the proposed MPPB approach, requiring a further investigation of the operation under grid interruption.

During grid interruption, there is no sinusoidal input voltage and no power can be extracted from the grid. When the phase lock of the PLL is lost, the PFC rectifier stops operating (all gates are turned off) and an idle power semiconductor state is entered, similar to the first state of startup. The PFC operation flag switches from ${\mathrm{ON}}_{\mathrm{PFC}}=1$ (normal operation) to ${\mathrm{ON}}_{\mathrm{PFC}}=0$, and the grid power request drops from the motor power $P_{\mathrm{G}}^{\ast }=P_{\mathrm{M}}^{\ast }$ to zero, $P_{\mathrm{G}}^{\ast }=0\mathrm{W}$, as shown in Figure 19 for ride-through operation.

Without electrical (or other) energy storage within the system, the compressor can no longer be driven, and the load torque of the compressor slows the rotational speed of the motor (the compressor is supplied from the kinetic energy storage of the motor inertia). During this period, the speed controller is frozen—all stored variables are continuously initialized with the instantaneous values to prevent triggered step responses—but the inverter remains turned on (${\mathrm{ON}}_{\mathrm{INV}}=1$) to maintain the DC-link voltage control, which is now decoupled from the grid input (since the feedforward term is now $p_{\mathrm{G}}^{\ast }=0\mathrm{W}$). The DC-link voltage control, then, continues to ensure that the DC-link voltage is driven to the reference voltage, which is supplied again by the motor inertia, and the rotating mass decelerates more quickly (and even more quickly if additional loads, such as discharge resistors or logic supply or fans, are connected to the DC-link).

At this point, with the decelerating motor supplying the DC-link to maintain the reference voltage, two cases—short-term and long-term interruptions—were analyzed separately.

Short-term interruption: If the grid returns while the system is still rotating (and supplying the DC-link), only the PFC rectifier needs to be re-synchronized, and the grid power can be ramped to stabilize the mechanical speed of the motor. Because the DC-link voltage is maintained above the voltage peak of the grid, no pre-charging state is required and the response time is fast.

This performance is verified in Figure 20, where a 100 ms interruption at a power level of $3.4$ kW results in a fast and stable recovery to the mechanical speed request. When the grid is interrupted, PFC operation stops and the grid current goes to zero. The speed drops linearly with $\mathrm{d}\omega /\mathrm{d}t=T_{\mathrm{L}}/J_{\mathrm{M}}$ (under constant torque operation, which is the worst-case condition). When the grid returns after 100 ms, the PFC synchronizes and ramps up the motor power, and there is a reduction in the rate of the speed decay, which becomes zero at $\omega T_{\mathrm{L}}=P_{\mathrm{G}}$ (the speed minimum). From there, the control returns the motor to the desired steady-state speed, which occurs without significant DC-link voltage oscillations—even with the elimination of the DC-link energy storage capacitors provided by the MPPB approach. The recovery time could be even further shortened with the addition of a non-linear speed controller.

The survivable ride-through time depends primarily on the speed before the interruption, the total kinetic energy, and the instantaneous load torque (or the pressure of the tank; see Figure 1). If the motor stops rotating, the battery supply starts, the final extended functionality case explored here.

Long-term interruption and battery supply operation: The system will enter standstill if the motor speed decays to zero and the DC-link voltage can no longer be maintained (with no remaining kinetic energy). At this point, the DC-link and inverter control are turned off and the systems returns to a state similar to before the initial startup.

The DC-link voltage controller was implemented with a hysteresis control based on the ratio of the instantaneous and reference DC-link voltages, and this supports the direct utilization of this concept for startup.

If the grid interruption is sustained, the switching network of Figure 1a connects the battery supply instead of the grid, and the “DC grid” is detected by the grid detection and reconstruction unit (see Figure 19b). The identical control structure, with identical controller gains, is reused for DC grid operation, with the grid-dependent variables in AC operation replaced by their DC equivalents (see the replacements between Figure 19a,b). This implementation requires a single software code base for both operation modes, simplifying the implementation, testing, and maintenance. Of course, the traditional approach, similar to Figure 3a, could also be followed for DC operation, but this would increase the software effort for the design, validation, maintenance, and operation, where the two modes of operation would need to be actively switched during an extended grid voltage interruption. Because this introduces further complexity to the system, the approach of Figure 19 is preferred.

DC grid operation with a battery voltage of 100 V and a DC-link voltage of 150 $\mathrm{V}$ is validated in Figure 21 and Figure 22, with sinusoidal motor currents as shown in Figure 6 at a mechanical power of $1.2$ kW at 1000 rpm. DC grid operation and control was validated, and the MPPB system supports the required operation under fault conditions—even without DC-link energy storage.

6. Conclusions

Motor integration of Variable-Speed Drive (VSD) systems is desired for power density, integration, cost, and reliability—but for single-phase-supplied applications, is limited by the need to provide buffering energy storage on the DC-link, which is typically accomplished with electrolytic capacitors. These electrolytic capacitors occupy significant converter volume and cannot be operated across a wide temperature range with a high lifetime, preventing these VSDs from motor integration for the next-generation of electrified mobility.

This work proposed that the kinetic energy stored in the motor inertia itself be used to buffer the pulsating power from the single-phase grid, translating DC-link voltage and current ripple to motor speed and torque ripple. This concept is named the Motor-Integrated Power Pulsation Buffer (MPPB), and the control technique and structure required for nominal and grid fault condition operation were analyzed deeply. The control was realized by rearranging the connections between the same top-level controllers—without changing the core controllers themselves—supporting retrofitting and a simple software change.

A hardware demonstrator was constructed to verify the proposed MPPB concept for a single-phase-supplied railway application that drives a scroll compressor for air brakes (and other loads that require high reliability). The $7.5$ $\mathrm{k}$$\mathrm{W}$ demonstrator realized complete Permanent Magnet Synchronous Motor (PMSM) integration in a total volume of $8.2$ $\mathrm{L}$ (or 500 in${}^3$)—and without the DC-link capacitors that would occupy an additional 1 $\mathrm{L}$ (or 61 in${}^3$) and prevent integration. The MPPB system achieved over 90% grid-to-motor-shaft efficiency for all loads over 5 kW or 66% of the nominal load, with a worst-case loss penalty over a conventional electrolytic-capacitor-based system of only 17%. The demonstrator will achieve CISPR 11/Class A compliance at full integration and operates across the required suite of extended functionality, including for ride-through and sustained grid faults.

The proposed MPPB concept shifts the required grid-buffering energy storage from an additional electrical element—large DC-link capacitors—to the motor, which is already required for the mechanical drive, achieving otherwise unobtainable power densities and integration levels for single-phase-supplied variable-speed electric drives.